[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Register_Address_Translation_unit_function_one_save_transition.cpp 145 2010-10-13 18:15:51Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace register_address_translation_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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[139] | 22 | #define FUNCTION "Register_Address_Translation_unit::function_one_save_transition" |
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| 23 | void Register_Address_Translation_unit::function_one_save_transition (void) |
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[78] | 24 | { |
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[88] | 25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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| 26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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[78] | 27 | |
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| 28 | if (PORT_READ(in_NRESET) == 0) |
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| 29 | { |
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| 30 | uint32_t gpr = 1; |
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| 31 | uint32_t spr = 0; |
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| 32 | |
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| 33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 35 | { |
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[145] | 36 | RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0; |
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| 37 | RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false; |
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| 38 | RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary |
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[78] | 39 | |
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| 40 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
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[100] | 41 | { |
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[145] | 42 | RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++; |
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| 43 | RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; |
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| 44 | RAT_GPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary |
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[100] | 45 | } |
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[78] | 46 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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[100] | 47 | { |
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[145] | 48 | RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++; |
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| 49 | RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; |
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| 50 | RAT_SPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary |
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[100] | 51 | } |
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[78] | 52 | } |
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| 53 | } |
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| 54 | else |
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| 55 | { |
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| 56 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
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| 57 | |
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| 58 | // ===================================================== |
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[122] | 59 | // ====[ RETIRE_EVENT ]================================= |
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| 60 | // ===================================================== |
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| 61 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 62 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 63 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
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| 64 | // Test if event have just occure |
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| 65 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
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| 66 | { |
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| 67 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table"); |
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| 68 | |
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[139] | 69 | // Reset validity table |
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[122] | 70 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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[145] | 71 | RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false; |
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[122] | 72 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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[145] | 73 | RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false; |
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[122] | 74 | } |
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| 75 | |
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| 76 | // ===================================================== |
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[78] | 77 | // ====[ INSERT ]======================================= |
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| 78 | // ===================================================== |
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| 79 | // First : interface insert |
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[122] | 80 | // this instruction is speculative !!! |
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[78] | 81 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 82 | // Test transaction |
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| 83 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
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| 84 | { |
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[104] | 85 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
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| 86 | |
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[78] | 87 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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| 88 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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[122] | 89 | Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); |
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| 90 | Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); |
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[106] | 91 | |
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[122] | 92 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); |
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| 93 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); |
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[78] | 94 | |
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[122] | 95 | // Test if write and modifie RAT |
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| 96 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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| 97 | if (write_rd == 1) |
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[106] | 98 | { |
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[122] | 99 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]); |
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| 100 | Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
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| 101 | |
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| 102 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log); |
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| 103 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); |
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| 104 | |
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[145] | 105 | RAT_GPR_SPECULATIVE [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy; |
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| 106 | RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true; |
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[106] | 107 | } |
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| 108 | |
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[122] | 109 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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| 110 | if (write_re == 1) |
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[106] | 111 | { |
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[122] | 112 | Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]); |
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| 113 | Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
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| 114 | |
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| 115 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log); |
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| 116 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); |
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| 117 | |
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[145] | 118 | RAT_SPR_SPECULATIVE [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy; |
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| 119 | RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true; |
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[106] | 120 | } |
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[78] | 121 | } |
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| 122 | |
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| 123 | // ===================================================== |
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| 124 | // ====[ RETIRE ]======================================= |
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| 125 | // ===================================================== |
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| 126 | // Second : interface retire |
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| 127 | // (because if an event on the same thread : the instruction is already renamed) |
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| 128 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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| 129 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
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| 130 | { |
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[104] | 131 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
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| 132 | |
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[78] | 133 | // if no event : no effect, because the RAT content the most recently register |
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| 134 | // but if they have a event (exception or miss speculation), the rat must restore the oldest value |
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| 135 | // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register |
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| 136 | // the retire interface became of the Re Order Buffer, also is in program sequence ! |
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[104] | 137 | |
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[122] | 138 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
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| 139 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
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| 140 | Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); |
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| 141 | Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); |
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[139] | 142 | Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); |
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[104] | 143 | |
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[122] | 144 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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| 145 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); |
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| 146 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore ); |
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[106] | 147 | |
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[122] | 148 | // Test if write and have not a previous update |
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| 149 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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[139] | 150 | if (write_rd == 1) |
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[122] | 151 | { |
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| 152 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
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| 153 | |
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| 154 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); |
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| 155 | |
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| 156 | if (not restore) |
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| 157 | { |
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| 158 | Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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| 159 | |
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| 160 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); |
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| 161 | |
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[145] | 162 | RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; |
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[122] | 163 | } |
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| 164 | } |
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[112] | 165 | |
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[122] | 166 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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[139] | 167 | if (write_re == 1) |
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[122] | 168 | { |
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| 169 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
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[78] | 170 | |
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[122] | 171 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); |
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[78] | 172 | |
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[122] | 173 | if (not restore) |
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| 174 | { |
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| 175 | Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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[104] | 176 | |
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[122] | 177 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); |
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[112] | 178 | |
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[145] | 179 | RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; |
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[122] | 180 | } |
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| 181 | } |
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| 182 | |
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[78] | 183 | } |
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| 184 | } |
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| 185 | |
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[88] | 186 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
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[106] | 187 | { |
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| 188 | uint32_t limit = 4; |
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| 189 | |
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| 190 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
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| 191 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 192 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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| 193 | { |
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| 194 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); |
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| 195 | |
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| 196 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) |
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| 197 | { |
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| 198 | std::string str = ""; |
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| 199 | for (uint32_t x=0; x<limit; x++) |
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| 200 | { |
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| 201 | uint32_t index = k+x; |
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| 202 | if (index >= _param->_nb_general_register_logic) |
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| 203 | break; |
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| 204 | else |
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[145] | 205 | str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]); |
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[106] | 206 | } |
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| 207 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 208 | } |
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| 209 | |
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| 210 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) |
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| 211 | { |
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| 212 | std::string str = ""; |
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| 213 | |
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| 214 | for (uint32_t x=0; x<limit; x++) |
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| 215 | { |
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| 216 | uint32_t index = k+x; |
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| 217 | if (index >= _param->_nb_special_register_logic) |
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| 218 | break; |
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| 219 | else |
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[145] | 220 | str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) | ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]); |
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[106] | 221 | } |
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| 222 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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| 223 | } |
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| 224 | } |
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| 225 | } |
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| 226 | #endif |
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[88] | 227 | |
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[106] | 228 | #ifdef DEBUG_TEST |
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[122] | 229 | # if 1 |
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| 230 | { |
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| 231 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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| 232 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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[106] | 233 | { |
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[122] | 234 | for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) |
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| 235 | for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) |
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[106] | 236 | { |
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[145] | 237 | if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and |
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| 238 | RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and |
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| 239 | (RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y])) |
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| 240 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x])); |
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| 241 | if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y]) |
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| 242 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x])); |
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[122] | 243 | |
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[106] | 244 | } |
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[122] | 245 | for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) |
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| 246 | for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) |
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| 247 | { |
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[145] | 248 | if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and |
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| 249 | RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and |
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| 250 | (RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y])) |
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| 251 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x])); |
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| 252 | if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y]) |
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| 253 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x])); |
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[122] | 254 | |
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| 255 | } |
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[106] | 256 | } |
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[122] | 257 | |
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| 258 | } |
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| 259 | # endif |
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[88] | 260 | #endif |
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| 261 | |
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| 262 | log_end(Register_Address_Translation_unit,FUNCTION); |
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[78] | 263 | }; |
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| 264 | |
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| 265 | }; // end namespace register_address_translation_unit |
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| 266 | }; // end namespace register_translation_unit |
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| 267 | }; // end namespace rename_unit |
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| 268 | }; // end namespace ooo_engine |
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| 269 | }; // end namespace multi_ooo_engine |
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| 270 | }; // end namespace core |
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| 271 | |
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| 272 | }; // end namespace behavioural |
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| 273 | }; // end namespace morpheo |
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| 274 | #endif |
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