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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 17 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 35.2 KB

Line
1	/*
2	* $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (128*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15	#include <list>
16
17
18	class entry_t
19	{
20	public : bool _is_free ;
21	public : bool _is_link ;
22	public : bool _is_valid;
23	public : uint32_t _counter ;
24	};
25
26
27	void test (string name,
28	morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::stat_list_unit::Parameters * _param)
29	{
30	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
31
32	#ifdef STATISTICS
33	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
34	#endif
35
36	Tusage_t _usage = USE_ALL;
37
38	// _usage = usage_unset(_usage,USE_SYSTEMC );
39	// _usage = usage_unset(_usage,USE_VHDL );
40	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
41	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
42	// _usage = usage_unset(_usage,USE_POSITION );
43	// _usage = usage_unset(_usage,USE_STATISTICS );
44	// _usage = usage_unset(_usage,USE_INFORMATION );
45
46	Stat_List_unit * _Stat_List_unit = new Stat_List_unit
47	(name.c_str(),
48	#ifdef STATISTICS
49	_parameters_statistics,
50	#endif
51	_param,
52	_usage);
53
54	#ifdef SYSTEMC
55	/*********************************************************************
56	* Déclarations des signaux
57	*********************************************************************/
58	string rename;
59
60	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
61	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
62
63	sc_signal<Tcontrol_t > ** in_INSERT_VAL ;//[nb_inst_insert]
64	sc_signal<Tcontrol_t > ** out_INSERT_ACK ;//[nb_inst_insert]
65	sc_signal<Tcontrol_t > ** in_INSERT_READ_RA ;//[nb_inst_insert]
66	sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RA_PHY ;//[nb_inst_insert]
67	sc_signal<Tcontrol_t > ** in_INSERT_READ_RB ;//[nb_inst_insert]
68	sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RB_PHY ;//[nb_inst_insert]
69	sc_signal<Tcontrol_t > ** in_INSERT_READ_RC ;//[nb_inst_insert]
70	sc_signal<Tspecial_address_t> ** in_INSERT_NUM_REG_RC_PHY ;//[nb_inst_insert]
71	sc_signal<Tcontrol_t > ** in_INSERT_WRITE_RD ;//[nb_inst_insert]
72	sc_signal<Tgeneral_address_t> ** in_INSERT_NUM_REG_RD_PHY_NEW;//[nb_inst_insert]
73	sc_signal<Tcontrol_t > ** in_INSERT_WRITE_RE ;//[nb_inst_insert]
74	sc_signal<Tspecial_address_t> ** in_INSERT_NUM_REG_RE_PHY_NEW;//[nb_inst_insert]
75	sc_signal<Tcontrol_t > ** in_RETIRE_VAL ;//[nb_inst_retire]
76	sc_signal<Tcontrol_t > ** out_RETIRE_ACK ;//[nb_inst_retire]
77	sc_signal<Tcontrol_t > ** in_RETIRE_RESTORE ;//[nb_inst_retire]
78	sc_signal<Tcontrol_t > ** in_RETIRE_READ_RA ;//[nb_inst_retire]
79	sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire]
80	sc_signal<Tcontrol_t > ** in_RETIRE_READ_RB ;//[nb_inst_retire]
81	sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RB_PHY ;//[nb_inst_retire]
82	sc_signal<Tcontrol_t > ** in_RETIRE_READ_RC ;//[nb_inst_retire]
83	sc_signal<Tspecial_address_t> ** in_RETIRE_NUM_REG_RC_PHY ;//[nb_inst_retire]
84	sc_signal<Tcontrol_t > ** in_RETIRE_WRITE_RD ;//[nb_inst_retire]
85	sc_signal<Tcontrol_t > ** in_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire]
86	sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RD_PHY_OLD;//[nb_inst_retire]
87	sc_signal<Tgeneral_address_t> ** in_RETIRE_NUM_REG_RD_PHY_NEW;//[nb_inst_retire]
88	sc_signal<Tcontrol_t > ** in_RETIRE_WRITE_RE ;//[nb_inst_retire]
89	sc_signal<Tcontrol_t > ** in_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire]
90	sc_signal<Tspecial_address_t> ** in_RETIRE_NUM_REG_RE_PHY_OLD;//[nb_inst_retire]
91	sc_signal<Tspecial_address_t> ** in_RETIRE_NUM_REG_RE_PHY_NEW;//[nb_inst_retire]
92	sc_signal<Tcontrol_t > ** out_PUSH_GPR_VAL ;//[nb_reg_free]
93	sc_signal<Tcontrol_t > ** in_PUSH_GPR_ACK ;//[nb_reg_free]
94	sc_signal<Tgeneral_address_t> ** out_PUSH_GPR_NUM_REG ;//[nb_reg_free]
95	sc_signal<Tcontrol_t > ** out_PUSH_SPR_VAL ;//[nb_reg_free]
96	sc_signal<Tcontrol_t > ** in_PUSH_SPR_ACK ;//[nb_reg_free]
97	sc_signal<Tspecial_address_t> ** out_PUSH_SPR_NUM_REG ;//[nb_reg_free]
98
99	ALLOC1_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert);
100	ALLOC1_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert);
101	ALLOC1_SC_SIGNAL( in_INSERT_READ_RA ," in_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert);
102	ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RA_PHY ," in_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
103	ALLOC1_SC_SIGNAL( in_INSERT_READ_RB ," in_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert);
104	ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RB_PHY ," in_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
105	ALLOC1_SC_SIGNAL( in_INSERT_READ_RC ," in_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert);
106	ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RC_PHY ," in_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert);
107	ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RD ," in_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert);
108	ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW," in_INSERT_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_insert);
109	ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RE ," in_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert);
110	ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW," in_INSERT_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert);
111	ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire);
112	ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire);
113	ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE ," in_RETIRE_RESTORE ",Tcontrol_t ,_param->_nb_inst_retire);
114	ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire);
115	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire);
116	ALLOC1_SC_SIGNAL( in_RETIRE_READ_RB ," in_RETIRE_READ_RB ",Tcontrol_t ,_param->_nb_inst_retire);
117	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ," in_RETIRE_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_retire);
118	ALLOC1_SC_SIGNAL( in_RETIRE_READ_RC ," in_RETIRE_READ_RC ",Tcontrol_t ,_param->_nb_inst_retire);
119	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ," in_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_retire);
120	ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire);
121	ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD," in_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire);
122	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire);
123	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW," in_RETIRE_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_retire);
124	ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RE ," in_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire);
125	ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE_RE_PHY_OLD," in_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire);
126	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire);
127	ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire);
128	ALLOC1_SC_SIGNAL(out_PUSH_GPR_VAL ,"out_PUSH_GPR_VAL ",Tcontrol_t ,_param->_nb_reg_free);
129	ALLOC1_SC_SIGNAL( in_PUSH_GPR_ACK ," in_PUSH_GPR_ACK ",Tcontrol_t ,_param->_nb_reg_free);
130	ALLOC1_SC_SIGNAL(out_PUSH_GPR_NUM_REG ,"out_PUSH_GPR_NUM_REG ",Tgeneral_address_t,_param->_nb_reg_free);
131	ALLOC1_SC_SIGNAL(out_PUSH_SPR_VAL ,"out_PUSH_SPR_VAL ",Tcontrol_t ,_param->_nb_reg_free);
132	ALLOC1_SC_SIGNAL( in_PUSH_SPR_ACK ," in_PUSH_SPR_ACK ",Tcontrol_t ,_param->_nb_reg_free);
133	ALLOC1_SC_SIGNAL(out_PUSH_SPR_NUM_REG ,"out_PUSH_SPR_NUM_REG ",Tspecial_address_t,_param->_nb_reg_free);
134
135
136	/********************************************************
137	* Instanciation
138	********************************************************/
139
140	msg(_("<%s> : Instanciation of _Stat_List_unit.\n"),name.c_str());
141
142	((_Stat_List_unit->in_CLOCK)) ((in_CLOCK));
143	((_Stat_List_unit->in_NRESET)) ((in_NRESET));
144
145	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_VAL ,_param->_nb_inst_insert);
146	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_INSERT_ACK ,_param->_nb_inst_insert);
147	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RA ,_param->_nb_inst_insert);
148	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
149	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RB ,_param->_nb_inst_insert);
150	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
151	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RC ,_param->_nb_inst_insert);
152	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
153	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RD ,_param->_nb_inst_insert);
154	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert);
155	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RE ,_param->_nb_inst_insert);
156	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert);
157
158	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_VAL ,_param->_nb_inst_retire);
159	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire);
160	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE ,_param->_nb_inst_retire);
161	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire);
162	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire);
163	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RB ,_param->_nb_inst_retire);
164	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire);
165	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RC ,_param->_nb_inst_retire);
166	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire);
167	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire);
168	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire);
169	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire);
170	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire);
171	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RE ,_param->_nb_inst_retire);
172	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire);
173	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire);
174	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire);
175
176	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_GPR_VAL ,_param->_nb_reg_free);
177	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_PUSH_GPR_ACK ,_param->_nb_reg_free);
178	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_GPR_NUM_REG ,_param->_nb_reg_free);
179
180	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_SPR_VAL ,_param->_nb_reg_free);
181	INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_PUSH_SPR_ACK ,_param->_nb_reg_free);
182	INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_SPR_NUM_REG ,_param->_nb_reg_free);
183
184	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
185
186	Time * _time = new Time();
187
188	/********************************************************
189	* Simulation - Begin
190	********************************************************/
191
192	// Initialisation
193
194	const uint32_t seed = 0;
195	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
196
197	srand(seed);
198
199	int32_t percent_transaction_insert = 95;
200	int32_t percent_transaction_retire = 95;
201	int32_t percent_transaction_push = 95;
202
203	uint32_t nb_thread = 0;
204	for (uint32_t i=0; i<_param->_nb_front_end; i++)
205	nb_thread += _param->_nb_context [i];
206
207	SC_START(0);
208	LABEL("Initialisation");
209
210	LABEL("Reset");
211	in_NRESET->write(0);
212	SC_START(5);
213	in_NRESET->write(1);
214
215	LABEL("Loop of Test");
216
217	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
218	{
219	LABEL("Iteration %d",iteration);
220
221	entry_t gpr_status [_param->_nb_general_register];
222	entry_t spr_status [_param->_nb_special_register];
223
224	for (uint32_t i=0; i<_param->_nb_general_register; i++)
225	{
226	gpr_status[i]._is_free = false;
227	gpr_status[i]._is_link = (i<(nb_thread*31+1));
228	gpr_status[i]._is_valid = true;
229	gpr_status[i]._counter = 0;
230	}
231	for (uint32_t i=0; i<_param->_nb_special_register; i++)
232	{
233	spr_status[i]._is_free = false;
234	spr_status[i]._is_link = (i<(nb_thread*2));
235	spr_status[i]._is_valid = true;
236	spr_status[i]._counter = 0;
237	}
238
239	std::list<Tgeneral_address_t> free_list_gpr;
240	std::list<Tgeneral_address_t> free_list_spr;
241
242	// Test free register
243	while ((free_list_gpr.size() < (_param->_nb_general_register - (nb_thread*31+1))) and
244	(free_list_spr.size() < (_param->_nb_special_register - (nb_thread*2 ))))
245	{
246	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
247	in_INSERT_VAL [i]->write(0);
248	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
249	in_RETIRE_VAL [i]->write(0);
250
251	for (uint32_t i=0; i<_param->_nb_reg_free; i++)
252	{
253	in_PUSH_GPR_ACK [i]->write((rand()%100)<percent_transaction_push);
254	in_PUSH_SPR_ACK [i]->write((rand()%100)<percent_transaction_push);
255	}
256
257	SC_START(0);
258
259	for (uint32_t i=0; i<_param->_nb_reg_free; i++)
260	{
261	if (out_PUSH_GPR_VAL [i]->read() and in_PUSH_GPR_ACK [i]->read())
262	{
263	Tgeneral_address_t reg = out_PUSH_GPR_NUM_REG [i]->read();
264
265	LABEL("PUSH_GPR [%d] - Accepted",i);
266	LABEL(" * reg : %d",reg);
267	LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free );
268	LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link );
269	LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid);
270	LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter );
271
272	TEST(bool, true,((gpr_status[reg]._is_free == 0) and
273	(gpr_status[reg]._is_link == 0) and
274	(gpr_status[reg]._is_valid == 1)// and
275	// (gpr_status[reg]._counter == 0)
276	));
277
278	gpr_status[reg]._is_free = 1;
279	free_list_gpr.push_back(reg);
280	}
281
282	if (out_PUSH_SPR_VAL [i]->read() and in_PUSH_SPR_ACK [i]->read())
283	{
284	Tspecial_address_t reg = out_PUSH_SPR_NUM_REG [i]->read();
285
286	LABEL("PUSH_SPR [%d] - Accepted",i);
287	LABEL(" * reg : %d",reg);
288	LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free );
289	LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link );
290	LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid);
291	LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter );
292
293	TEST(bool, true,((spr_status[reg]._is_free == 0) and
294	(spr_status[reg]._is_link == 0) and
295	(spr_status[reg]._is_valid == 1)// and
296	// (spr_status[reg]._counter == 0)
297	));
298
299	spr_status[reg]._is_free = 1;
300	free_list_spr.push_back(reg);
301	}
302	}
303
304	SC_START(1);
305	}
306
307	LABEL("=======================");
308	LABEL("===== END OF INIT =====");
309	LABEL("=======================");
310
311	int32_t nb_cycle = 64;
312
313	while (nb_cycle > 0)
314	{
315	std::list<Tgeneral_address_t>::iterator it_gpr = free_list_gpr.begin();
316	std::list<Tspecial_address_t>::iterator it_spr = free_list_spr.begin();
317
318
319	entry_t gpr_status_insert [_param->_nb_general_register];
320	entry_t spr_status_insert [_param->_nb_special_register];
321	entry_t gpr_status_retire [_param->_nb_general_register];
322	entry_t spr_status_retire [_param->_nb_special_register];
323
324	for (uint32_t i=0; i<_param->_nb_general_register; i++)
325	{
326	gpr_status_insert [i] = gpr_status[i];
327	gpr_status_retire [i] = gpr_status[i];
328	}
329	for (uint32_t i=0; i<_param->_nb_special_register; i++)
330	{
331	spr_status_insert [i] = spr_status[i];
332	spr_status_retire [i] = spr_status[i];
333	}
334
335	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
336	{
337	Tgeneral_address_t ra = (rand()%(_param->_nb_general_register-1))+1;
338	Tgeneral_address_t rb = (rand()%(_param->_nb_general_register-1))+1;
339	Tspecial_address_t rc = (rand()%(_param->_nb_special_register )) ;
340	Tgeneral_address_t rd = (it_gpr != free_list_gpr.end())?*it_gpr:0;
341	Tspecial_address_t re = (it_spr != free_list_spr.end())?*it_spr:0;
342
343	Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link); // and (gpr_status_insert[ra]._counter < _param->_max_reader);
344	Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link); // and (gpr_status_insert[rb]._counter < _param->_max_reader);
345	Tcontrol_t read_rc = (spr_status_insert[rc]._is_link); // and (spr_status_insert[rc]._counter < _param->_max_reader);
346	Tcontrol_t write_rd = (it_gpr != free_list_gpr.end());
347	Tcontrol_t write_re = (it_spr != free_list_spr.end());
348
349	in_INSERT_VAL [i]->write((rand()%100) < percent_transaction_insert);
350	in_INSERT_READ_RA [i]->write(read_ra );
351	in_INSERT_NUM_REG_RA_PHY [i]->write(ra);
352	in_INSERT_READ_RB [i]->write(read_rb );
353	in_INSERT_NUM_REG_RB_PHY [i]->write(rb);
354	in_INSERT_READ_RC [i]->write(read_rc );
355	in_INSERT_NUM_REG_RC_PHY [i]->write(rc);
356	in_INSERT_WRITE_RD [i]->write(write_rd);
357	in_INSERT_NUM_REG_RD_PHY_NEW [i]->write(rd);
358	in_INSERT_WRITE_RE [i]->write(write_re);
359	in_INSERT_NUM_REG_RE_PHY_NEW [i]->write(re);
360
361	if (read_ra)
362	gpr_status_insert[ra]._counter++;
363	if (read_rb)
364	gpr_status_insert[rb]._counter++;
365	if (read_rc)
366	spr_status_insert[rc]._counter++;
367	if (write_rd)
368	it_gpr ++;
369	if (write_re)
370	it_spr ++;
371	}
372
373	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
374	{
375	Tgeneral_address_t ra = (rand()%(_param->_nb_general_register-1))+1;
376	Tgeneral_address_t rb = (rand()%(_param->_nb_general_register-1))+1;
377	Tspecial_address_t rc = (rand()%(_param->_nb_special_register )) ;
378	Tgeneral_address_t rd_old = (rand()%(_param->_nb_general_register-1))+1;
379	Tgeneral_address_t rd_new = (rand()%(_param->_nb_general_register-1))+1;
380	Tspecial_address_t re_old = (rand()%(_param->_nb_special_register )) ;
381	Tspecial_address_t re_new = (rand()%(_param->_nb_special_register )) ;
382
383	Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link); // and (gpr_status_retire[ra]._counter > 0);
384	Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link); // and (gpr_status_retire[rb]._counter > 0);
385	Tcontrol_t read_rc = (spr_status_retire[rc]._is_link); // and (spr_status_retire[rc]._counter > 0);
386	Tcontrol_t write_rd = ( (gpr_status_retire[rd_old]._is_link ) and
387	(gpr_status_retire[rd_old]._is_valid) and
388	(gpr_status_retire[rd_new]._is_link ) and
389	not (gpr_status_retire[rd_new]._is_valid));
390	Tcontrol_t write_re = ( (spr_status_retire[re_old]._is_link ) and
391	(spr_status_retire[re_old]._is_valid) and
392	(spr_status_retire[re_new]._is_link ) and
393	not (spr_status_retire[re_new]._is_valid));
394
395	in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire);
396	in_RETIRE_READ_RA [i]->write(read_ra );
397	in_RETIRE_RESTORE [i]->write(0);
398	in_RETIRE_NUM_REG_RA_PHY [i]->write(ra);
399	in_RETIRE_READ_RB [i]->write(read_rb );
400	in_RETIRE_NUM_REG_RB_PHY [i]->write(rb);
401	in_RETIRE_READ_RC [i]->write(read_rc );
402	in_RETIRE_NUM_REG_RC_PHY [i]->write(rc);
403	in_RETIRE_WRITE_RD [i]->write(write_rd);
404	in_RETIRE_RESTORE_RD_PHY_OLD [i]->write(0);
405	in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rd_old);
406	in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rd_new);
407	in_RETIRE_WRITE_RE [i]->write(write_re);
408	in_RETIRE_RESTORE_RE_PHY_OLD [i]->write(0);
409	in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(re_old);
410	in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(re_new);
411
412	if (read_ra)
413	{
414	gpr_status_retire[ra]._counter --;
415	}
416	if (read_rb)
417	{
418	gpr_status_retire[rb]._counter --;
419	}
420	if (read_rc)
421	{
422	spr_status_retire[rc]._counter --;
423	}
424	if (write_rd)
425	{
426	gpr_status_retire[rd_old]._is_link = 0;
427	gpr_status_retire[rd_new]._is_valid = 1;
428	}
429	if (write_re)
430	{
431	spr_status_retire[re_old]._is_link = 0;
432	spr_status_retire[re_new]._is_valid = 1;
433	}
434
435	}
436
437
438	for (uint32_t i=0; i<_param->_nb_reg_free; i++)
439	{
440	in_PUSH_GPR_ACK [i]->write((rand()%100)<percent_transaction_push);
441	in_PUSH_SPR_ACK [i]->write((rand()%100)<percent_transaction_push);
442	}
443
444	SC_START(0);
445
446	it_gpr = free_list_gpr.begin();
447	it_spr = free_list_spr.begin();
448
449	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
450	{
451	Tcontrol_t write_rd = in_INSERT_WRITE_RD [i]->read();
452	Tcontrol_t write_re = in_INSERT_WRITE_RE [i]->read();
453
454	if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read())
455	{
456	Tcontrol_t read_ra = in_INSERT_READ_RA [i]->read();
457	Tgeneral_address_t ra = in_INSERT_NUM_REG_RA_PHY [i]->read();
458	Tcontrol_t read_rb = in_INSERT_READ_RB [i]->read();
459	Tgeneral_address_t rb = in_INSERT_NUM_REG_RB_PHY [i]->read();
460	Tcontrol_t read_rc = in_INSERT_READ_RC [i]->read();
461	Tspecial_address_t rc = in_INSERT_NUM_REG_RC_PHY [i]->read();
462	Tgeneral_address_t rd_new = in_INSERT_NUM_REG_RD_PHY_NEW [i]->read();
463	Tspecial_address_t re_new = in_INSERT_NUM_REG_RE_PHY_NEW [i]->read();
464
465	LABEL("INSERT [%d] - Accepted",i);
466	LABEL(" * read_ra : %d",read_ra );
467	LABEL(" * reg_ra : %d",ra );
468	LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free );
469	LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link );
470	LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid);
471	LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter );
472	LABEL(" * read_rb : %d",read_rb );
473	LABEL(" * reg_rb : %d",rb );
474	LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free );
475	LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link );
476	LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid);
477	LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter );
478	LABEL(" * read_rc : %d",read_rc );
479	LABEL(" * reg_rc : %d",rc );
480	LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free );
481	LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link );
482	LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid);
483	LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter );
484	LABEL(" * read_rd : %d",write_rd);
485	LABEL(" * reg_rd_new : %d",rd_new );
486	LABEL(" * status[%d]._is_free : %d",rd_new,spr_status[rd_new]._is_free );
487	LABEL(" * status[%d]._is_link : %d",rd_new,spr_status[rd_new]._is_link );
488	LABEL(" * status[%d]._is_valid : %d",rd_new,spr_status[rd_new]._is_valid);
489	LABEL(" * status[%d]._counter : %d",rd_new,spr_status[rd_new]._counter );
490	LABEL(" * read_re : %d",write_re);
491	LABEL(" * reg_re_new : %d",re_new );
492	LABEL(" * status[%d]._is_free : %d",re_new,spr_status[re_new]._is_free );
493	LABEL(" * status[%d]._is_link : %d",re_new,spr_status[re_new]._is_link );
494	LABEL(" * status[%d]._is_valid : %d",re_new,spr_status[re_new]._is_valid);
495	LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter );
496
497	if (read_ra)
498	{
499	gpr_status[ra]._counter ++;
500	}
501	if (read_rb)
502	{
503	gpr_status[rb]._counter ++;
504	}
505	if (read_rc)
506	{
507	spr_status[rc]._counter ++;
508	}
509	if (write_rd)
510	{
511	Tgeneral_address_t reg = *it_gpr;
512	TEST(Tgeneral_address_t,reg,rd_new);
513
514	it_gpr = free_list_gpr.erase(it_gpr);
515
516	gpr_status[reg]._is_free = 0;
517	gpr_status[reg]._is_link = 1;
518	gpr_status[reg]._is_valid = 0;
519	}
520
521	if (write_re)
522	{
523	Tspecial_address_t reg = *it_spr;
524	TEST(Tspecial_address_t,reg,re_new);
525
526	it_spr = free_list_spr.erase(it_spr);
527
528	spr_status[reg]._is_free = 0;
529	spr_status[reg]._is_link = 1;
530	spr_status[reg]._is_valid = 0;
531	}
532	}
533	else
534	{
535	if (write_rd)
536	it_gpr ++;
537	if (write_re)
538	it_spr ++;
539	}
540	}
541
542	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
543	if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read())
544	{
545	Tcontrol_t restore = in_RETIRE_RESTORE [i]->read();
546	Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read();
547	Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read();
548	Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read();
549	Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read();
550	Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read();
551	Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read();
552	Tcontrol_t write_rd = in_RETIRE_WRITE_RD [i]->read();
553	Tcontrol_t restore_rd_old = in_RETIRE_RESTORE_RD_PHY_OLD [i]->read();
554	Tgeneral_address_t rd_old = in_RETIRE_NUM_REG_RD_PHY_OLD [i]->read();
555	Tgeneral_address_t rd_new = in_RETIRE_NUM_REG_RD_PHY_NEW [i]->read();
556	Tcontrol_t write_re = in_RETIRE_WRITE_RE [i]->read();
557	Tcontrol_t restore_re_old = in_RETIRE_RESTORE_RE_PHY_OLD [i]->read();
558	Tgeneral_address_t re_old = in_RETIRE_NUM_REG_RE_PHY_OLD [i]->read();
559	Tgeneral_address_t re_new = in_RETIRE_NUM_REG_RE_PHY_NEW [i]->read();
560
561	LABEL("RETIRE [%d] - Accepted",i);
562	LABEL(" * restore : %d",restore);
563	LABEL(" * read_ra : %d",read_ra );
564	LABEL(" * reg_ra : %d",ra );
565	LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free );
566	LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link );
567	LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid);
568	LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter );
569	LABEL(" * read_rb : %d",read_rb );
570	LABEL(" * reg_rb : %d",rb );
571	LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free );
572	LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link );
573	LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid);
574	LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter );
575	LABEL(" * read_rc : %d",read_rc );
576	LABEL(" * reg_rc : %d",rc );
577	LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free );
578	LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link );
579	LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid);
580	LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter );
581	LABEL(" * read_rd : %d",write_rd);
582	LABEL(" * restore_rd_old : %d",restore_rd_old);
583	LABEL(" * reg_rd_old : %d",rd_old );
584	LABEL(" * status[%d]._is_free : %d",rd_old,spr_status[rd_old]._is_free );
585	LABEL(" * status[%d]._is_link : %d",rd_old,spr_status[rd_old]._is_link );
586	LABEL(" * status[%d]._is_valid : %d",rd_old,spr_status[rd_old]._is_valid);
587	LABEL(" * status[%d]._counter : %d",rd_old,spr_status[rd_old]._counter );
588	LABEL(" * reg_rd_new : %d",rd_new );
589	LABEL(" * status[%d]._is_free : %d",rd_new,spr_status[rd_new]._is_free );
590	LABEL(" * status[%d]._is_link : %d",rd_new,spr_status[rd_new]._is_link );
591	LABEL(" * status[%d]._is_valid : %d",rd_new,spr_status[rd_new]._is_valid);
592	LABEL(" * status[%d]._counter : %d",rd_new,spr_status[rd_new]._counter );
593	LABEL(" * read_re : %d",write_re);
594	LABEL(" * restore_re_old : %d",restore_re_old);
595	LABEL(" * reg_re_old : %d",re_old );
596	LABEL(" * status[%d]._is_free : %d",re_old,spr_status[re_old]._is_free );
597	LABEL(" * status[%d]._is_link : %d",re_old,spr_status[re_old]._is_link );
598	LABEL(" * status[%d]._is_valid : %d",re_old,spr_status[re_old]._is_valid);
599	LABEL(" * status[%d]._counter : %d",re_old,spr_status[re_old]._counter );
600	LABEL(" * reg_re_new : %d",re_new );
601	LABEL(" * status[%d]._is_free : %d",re_new,spr_status[re_new]._is_free );
602	LABEL(" * status[%d]._is_link : %d",re_new,spr_status[re_new]._is_link );
603	LABEL(" * status[%d]._is_valid : %d",re_new,spr_status[re_new]._is_valid);
604	LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter );
605
606	if (read_ra)
607	{
608	gpr_status[ra]._counter --;
609	}
610	if (read_rb)
611	{
612	gpr_status[rb]._counter --;
613	}
614	if (read_rc)
615	{
616	spr_status[rc]._counter --;
617	}
618	if (write_rd)
619	{
620	if (restore)
621	{
622	if (restore_rd_old)
623	{
624	gpr_status[rd_old]._is_link = 1;
625	gpr_status[rd_new]._is_link = 0;
626	gpr_status[rd_new]._is_valid = 1;
627	}
628	else
629	{
630	gpr_status[rd_old]._is_link = 0;
631	gpr_status[rd_new]._is_link = 0;
632	gpr_status[rd_new]._is_valid = 1;
633	}
634	}
635	else
636	{
637	gpr_status[rd_old]._is_link = 0;
638	gpr_status[rd_new]._is_valid = 1;
639	}
640
641	}
642	if (write_re)
643	{
644	if (restore_re_old)
645	{
646	spr_status[re_old]._is_link = 1;
647	spr_status[re_new]._is_link = 0;
648	spr_status[re_new]._is_valid = 1;
649	}
650	else
651	{
652	spr_status[re_old]._is_link = 0;
653	spr_status[re_new]._is_valid = 1;
654	}
655	}
656	}
657
658
659	for (uint32_t i=0; i<_param->_nb_reg_free; i++)
660	{
661	if (out_PUSH_GPR_VAL [i]->read() and in_PUSH_GPR_ACK [i]->read())
662	{
663	Tgeneral_address_t reg = out_PUSH_GPR_NUM_REG [i]->read();
664
665	LABEL("PUSH_GPR [%d] - Accepted",i);
666	LABEL(" * reg : %d",reg);
667	LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free );
668	LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link );
669	LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid);
670	LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter );
671
672	TEST(bool, true,((gpr_status[reg]._is_free == 0) and
673	(gpr_status[reg]._is_link == 0) and
674	(gpr_status[reg]._is_valid == 1)// and
675	// (gpr_status[reg]._counter == 0)
676	));
677
678	gpr_status[reg]._is_free = 1;
679	free_list_gpr.push_back(reg);
680	}
681
682	if (out_PUSH_SPR_VAL [i]->read() and in_PUSH_SPR_ACK [i]->read())
683	{
684	Tspecial_address_t reg = out_PUSH_SPR_NUM_REG [i]->read();
685
686	LABEL("PUSH_SPR [%d] - Accepted",i);
687	LABEL(" * reg : %d",reg);
688	LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free );
689	LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link );
690	LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid);
691	LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter );
692
693	TEST(bool, true,((spr_status[reg]._is_free == 0) and
694	(spr_status[reg]._is_link == 0) and
695	(spr_status[reg]._is_valid == 1)// and
696	// (spr_status[reg]._counter == 0)
697	));
698
699	spr_status[reg]._is_free = 1;
700	free_list_spr.push_back(reg);
701	}
702	}
703
704	SC_START(1);
705	nb_cycle --;
706	}
707	}
708
709	/********************************************************
710	* Simulation - End
711	********************************************************/
712
713	TEST_OK ("End of Simulation");
714	delete _time;
715
716	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
717
718	delete in_CLOCK;
719	delete in_NRESET;
720
721	delete [] in_INSERT_VAL ;
722	delete [] out_INSERT_ACK ;
723	delete [] in_INSERT_READ_RA ;
724	delete [] in_INSERT_NUM_REG_RA_PHY ;
725	delete [] in_INSERT_READ_RB ;
726	delete [] in_INSERT_NUM_REG_RB_PHY ;
727	delete [] in_INSERT_READ_RC ;
728	delete [] in_INSERT_NUM_REG_RC_PHY ;
729	delete [] in_INSERT_WRITE_RD ;
730	delete [] in_INSERT_NUM_REG_RD_PHY_NEW;
731	delete [] in_INSERT_WRITE_RE ;
732	delete [] in_INSERT_NUM_REG_RE_PHY_NEW;
733	delete [] in_RETIRE_VAL ;
734	delete [] out_RETIRE_ACK ;
735	delete [] in_RETIRE_RESTORE ;
736	delete [] in_RETIRE_READ_RA ;
737	delete [] in_RETIRE_NUM_REG_RA_PHY ;
738	delete [] in_RETIRE_READ_RB ;
739	delete [] in_RETIRE_NUM_REG_RB_PHY ;
740	delete [] in_RETIRE_READ_RC ;
741	delete [] in_RETIRE_NUM_REG_RC_PHY ;
742	delete [] in_RETIRE_WRITE_RD ;
743	delete [] in_RETIRE_RESTORE_RD_PHY_OLD;
744	delete [] in_RETIRE_NUM_REG_RD_PHY_OLD;
745	delete [] in_RETIRE_NUM_REG_RD_PHY_NEW;
746	delete [] in_RETIRE_WRITE_RE ;
747	delete [] in_RETIRE_RESTORE_RE_PHY_OLD;
748	delete [] in_RETIRE_NUM_REG_RE_PHY_OLD;
749	delete [] in_RETIRE_NUM_REG_RE_PHY_NEW;
750	delete [] out_PUSH_GPR_VAL ;
751	delete [] in_PUSH_GPR_ACK ;
752	delete [] out_PUSH_GPR_NUM_REG ;
753	delete [] out_PUSH_SPR_VAL ;
754	delete [] in_PUSH_SPR_ACK ;
755	delete [] out_PUSH_SPR_NUM_REG ;
756
757	#endif
758
759	delete _Stat_List_unit;
760	#ifdef STATISTICS
761	delete _parameters_statistics;
762	#endif
763	}

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