[78] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Stat_List_unit_transition.cpp 118 2009-05-20 22:01:32Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_ooo_engine { |
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| 15 | namespace ooo_engine { |
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| 16 | namespace rename_unit { |
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| 17 | namespace register_translation_unit { |
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| 18 | namespace stat_list_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Stat_List_unit::transition" |
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| 23 | void Stat_List_unit::transition (void) |
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| 24 | { |
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[88] | 25 | log_begin(Stat_List_unit,FUNCTION); |
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| 26 | log_function(Stat_List_unit,FUNCTION,_name.c_str()); |
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[78] | 27 | |
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| 28 | if (PORT_READ(in_NRESET) == 0) |
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| 29 | { |
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| 30 | uint32_t gpr = 0; |
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| 31 | uint32_t spr = 0; |
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| 32 | |
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| 33 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 34 | { |
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| 35 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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| 36 | gpr_stat_list [i][j].reset((gpr++)<_param->_nb_gpr_use_init); |
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| 37 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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| 38 | spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); |
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| 39 | } |
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[112] | 40 | reg_GPR_PTR_FREE = 0; |
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| 41 | reg_SPR_PTR_FREE = 0; |
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[78] | 42 | } |
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| 43 | else |
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| 44 | { |
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| 45 | // ===================================================== |
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| 46 | // =====[ INSERT ]====================================== |
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| 47 | // ===================================================== |
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| 48 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 49 | if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) |
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| 50 | { |
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[106] | 51 | log_printf(TRACE,Stat_List_unit,FUNCTION," * INSERT [%d]",i); |
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| 52 | |
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[112] | 53 | // if (PORT_READ(in_INSERT_READ_RA [i])) |
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| 54 | // { |
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| 55 | // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); |
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[106] | 56 | |
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[112] | 57 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); |
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[106] | 58 | |
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[112] | 59 | // uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 60 | // uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 61 | // gpr_stat_list [bank][reg].insert_read(); |
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| 62 | // } |
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[78] | 63 | |
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[112] | 64 | // if (PORT_READ(in_INSERT_READ_RB [i])) |
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| 65 | // { |
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| 66 | // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); |
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[106] | 67 | |
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[112] | 68 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); |
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[106] | 69 | |
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[112] | 70 | // uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 71 | // uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 72 | // gpr_stat_list [bank][reg].insert_read(); |
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| 73 | // } |
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[78] | 74 | |
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[112] | 75 | // if (PORT_READ(in_INSERT_READ_RC [i])) |
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| 76 | // { |
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| 77 | // Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); |
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[106] | 78 | |
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[112] | 79 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); |
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[106] | 80 | |
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[112] | 81 | // uint32_t bank = num_reg >> _param->_shift_spr; |
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| 82 | // uint32_t reg = num_reg & _param->_mask_spr ; |
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| 83 | // spr_stat_list [bank][reg].insert_read(); |
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| 84 | // } |
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[78] | 85 | |
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| 86 | if (PORT_READ(in_INSERT_WRITE_RD [i])) |
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| 87 | { |
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[117] | 88 | { |
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| 89 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [i]); |
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| 90 | |
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| 91 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg old : %d",num_reg); |
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| 92 | |
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| 93 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 94 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 95 | gpr_stat_list [bank][reg].insert_write_old(); |
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| 96 | } |
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| 97 | { |
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| 98 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); |
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| 99 | |
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| 100 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - num_reg new : %d",num_reg); |
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| 101 | |
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| 102 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 103 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 104 | gpr_stat_list [bank][reg].insert_write_new(); |
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| 105 | } |
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[78] | 106 | } |
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| 107 | |
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| 108 | if (PORT_READ(in_INSERT_WRITE_RE [i])) |
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| 109 | { |
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[117] | 110 | { |
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| 111 | Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [i]); |
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| 112 | |
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| 113 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg old : %d",num_reg); |
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| 114 | |
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| 115 | uint32_t bank = num_reg >> _param->_shift_spr; |
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| 116 | uint32_t reg = num_reg & _param->_mask_spr ; |
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| 117 | spr_stat_list [bank][reg].insert_write_old(); |
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| 118 | } |
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| 119 | { |
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| 120 | Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); |
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| 121 | |
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| 122 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - num_reg new : %d",num_reg); |
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| 123 | |
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| 124 | uint32_t bank = num_reg >> _param->_shift_spr; |
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| 125 | uint32_t reg = num_reg & _param->_mask_spr ; |
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| 126 | spr_stat_list [bank][reg].insert_write_new(); |
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| 127 | } |
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| 128 | } |
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[78] | 129 | } |
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| 130 | |
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| 131 | // ===================================================== |
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| 132 | // =====[ RETIRE ]====================================== |
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| 133 | // ===================================================== |
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| 134 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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| 135 | if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) |
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| 136 | { |
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[106] | 137 | log_printf(TRACE,Stat_List_unit,FUNCTION," * RETIRE [%d]",i); |
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| 138 | |
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[112] | 139 | Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]); |
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[106] | 140 | |
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[112] | 141 | log_printf(TRACE,Stat_List_unit,FUNCTION," * restore : %d",restore); |
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[106] | 142 | |
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[112] | 143 | // if (PORT_READ(in_RETIRE_READ_RA [i])) |
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| 144 | // { |
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| 145 | // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); |
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[78] | 146 | |
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[112] | 147 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RA - num_reg : %d",num_reg); |
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[106] | 148 | |
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[112] | 149 | // uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 150 | // uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 151 | // gpr_stat_list [bank][reg].retire_read(); |
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| 152 | // } |
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[106] | 153 | |
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[112] | 154 | // if (PORT_READ(in_RETIRE_READ_RB [i])) |
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| 155 | // { |
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| 156 | // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); |
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[78] | 157 | |
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[112] | 158 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RB - num_reg : %d",num_reg); |
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[106] | 159 | |
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[112] | 160 | // uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 161 | // uint32_t reg = num_reg & _param->_mask_gpr ; |
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| 162 | // gpr_stat_list [bank][reg].retire_read(); |
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| 163 | // } |
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[106] | 164 | |
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[112] | 165 | // if (PORT_READ(in_RETIRE_READ_RC [i])) |
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| 166 | // { |
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| 167 | // Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); |
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[78] | 168 | |
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[112] | 169 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * READ_RC - num_reg : %d",num_reg); |
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| 170 | |
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| 171 | // uint32_t bank = num_reg >> _param->_shift_spr; |
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| 172 | // uint32_t reg = num_reg & _param->_mask_spr ; |
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| 173 | // spr_stat_list [bank][reg].retire_read(); |
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| 174 | // } |
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| 175 | |
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[78] | 176 | if (PORT_READ(in_RETIRE_WRITE_RD [i])) |
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| 177 | { |
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[88] | 178 | Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); |
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[106] | 179 | |
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| 180 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RD - restore_old : %d",restore_old); |
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| 181 | |
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[78] | 182 | { |
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| 183 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); |
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[106] | 184 | |
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[112] | 185 | log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); |
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[106] | 186 | |
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[78] | 187 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 188 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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[112] | 189 | gpr_stat_list [bank][reg].retire_write_old(restore, restore_old); |
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[78] | 190 | } |
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| 191 | { |
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| 192 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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[106] | 193 | |
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[112] | 194 | log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); |
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[106] | 195 | |
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[78] | 196 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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| 197 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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[112] | 198 | gpr_stat_list [bank][reg].retire_write_new(restore, restore_old); |
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[78] | 199 | } |
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| 200 | } |
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| 201 | |
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| 202 | if (PORT_READ(in_RETIRE_WRITE_RE [i])) |
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| 203 | { |
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[88] | 204 | Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); |
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[106] | 205 | |
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| 206 | log_printf(TRACE,Stat_List_unit,FUNCTION," * WRITE_RE - restore_old : %d",restore_old); |
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| 207 | |
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[78] | 208 | { |
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[112] | 209 | Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); |
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[106] | 210 | |
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[112] | 211 | log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_old : %d",num_reg); |
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[106] | 212 | |
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[78] | 213 | uint32_t bank = num_reg >> _param->_shift_spr; |
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| 214 | uint32_t reg = num_reg & _param->_mask_spr ; |
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[112] | 215 | spr_stat_list [bank][reg].retire_write_old(restore, restore_old); |
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[78] | 216 | } |
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| 217 | { |
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[112] | 218 | Tspecial_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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[106] | 219 | |
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[112] | 220 | log_printf(TRACE,Stat_List_unit,FUNCTION," num_reg_new : %d",num_reg); |
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[106] | 221 | |
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[78] | 222 | uint32_t bank = num_reg >> _param->_shift_spr; |
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| 223 | uint32_t reg = num_reg & _param->_mask_spr ; |
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[112] | 224 | spr_stat_list [bank][reg].retire_write_new(restore, restore_old); |
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[78] | 225 | } |
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| 226 | } |
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| 227 | } |
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| 228 | |
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| 229 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
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| 230 | { |
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| 231 | // ===================================================== |
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| 232 | // =====[ PUSH_GPR ]==================================== |
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| 233 | // ===================================================== |
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| 234 | if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) |
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[118] | 235 | gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][internal_PUSH_GPR_NUM_REG [i]].free(); |
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[78] | 236 | |
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| 237 | // ===================================================== |
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| 238 | // =====[ PUSH_SPR ]==================================== |
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| 239 | // ===================================================== |
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| 240 | if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) |
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[118] | 241 | spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][internal_PUSH_SPR_NUM_REG [i]].free(); |
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[78] | 242 | } |
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| 243 | |
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| 244 | // Update pointer |
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[112] | 245 | reg_GPR_PTR_FREE = ((reg_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:reg_GPR_PTR_FREE)-1; |
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| 246 | reg_SPR_PTR_FREE = ((reg_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:reg_SPR_PTR_FREE)-1; |
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[78] | 247 | } |
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| 248 | |
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| 249 | |
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[88] | 250 | #if (DEBUG >= DEBUG_TRACE) |
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[112] | 251 | { |
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| 252 | log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); |
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| 253 | log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_GPR_PTR_FREE : %d",reg_GPR_PTR_FREE); |
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| 254 | log_printf(TRACE,Stat_List_unit,FUNCTION," * reg_SPR_PTR_FREE : %d",reg_SPR_PTR_FREE); |
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| 255 | |
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| 256 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 257 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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| 258 | log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", |
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| 259 | i, |
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| 260 | j, |
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| 261 | (i<<_param->_shift_gpr)|j, |
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| 262 | gpr_stat_list[i][j]._is_free, |
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| 263 | gpr_stat_list[i][j]._is_link// , |
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| 264 | // gpr_stat_list[i][j]._is_valid, |
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| 265 | // gpr_stat_list[i][j]._counter |
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| 266 | ); |
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| 267 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 268 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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| 269 | log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d", |
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| 270 | i, |
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| 271 | j, |
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| 272 | (i<<_param->_shift_spr)|j, |
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| 273 | spr_stat_list[i][j]._is_free, |
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| 274 | spr_stat_list[i][j]._is_link// , |
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| 275 | // spr_stat_list[i][j]._is_valid, |
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| 276 | // spr_stat_list[i][j]._counter |
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| 277 | ); |
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| 278 | } |
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[88] | 279 | #endif |
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| 280 | |
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[112] | 281 | #ifdef DEBUG_TEST |
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| 282 | # if 0 |
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| 283 | { |
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| 284 | uint32_t size_rob = 64; |
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| 285 | uint32_t nb_context = 1; |
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| 286 | |
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| 287 | { |
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| 288 | uint32_t nb_is_link = 0; |
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| 289 | uint32_t nb_reg = 32; |
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| 290 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 291 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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| 292 | if (gpr_stat_list[i][j]._is_link) |
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| 293 | nb_is_link ++; |
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| 294 | |
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| 295 | log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_GPR_IS_LINK : %d",nb_is_link); |
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| 296 | |
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| 297 | if (nb_is_link > size_rob+nb_context*nb_reg) |
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| 298 | throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked gpr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); |
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| 299 | } |
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| 300 | |
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| 301 | { |
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| 302 | uint32_t nb_is_link = 0; |
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| 303 | uint32_t nb_reg = 2; |
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| 304 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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| 305 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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| 306 | if (spr_stat_list[i][j]._is_link) |
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| 307 | nb_is_link ++; |
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| 308 | |
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| 309 | log_printf(TRACE,Stat_List_unit,FUNCTION," * nb_SPR_IS_LINK : %d",nb_is_link); |
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| 310 | |
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| 311 | if (nb_is_link > size_rob+nb_context*nb_reg) |
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| 312 | throw ERRORMORPHEO(FUNCTION,toString(_("They are %d linked spr register, but max is size_rob+nb_context*%d = %d+%d*%d = %d"),nb_is_link,nb_reg,size_rob,nb_context,nb_reg,size_rob+nb_context*nb_reg)); |
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| 313 | } |
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| 314 | } |
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| 315 | # endif |
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| 316 | #endif |
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| 317 | |
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| 318 | |
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[78] | 319 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 320 | end_cycle (); |
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| 321 | #endif |
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| 322 | |
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[88] | 323 | log_end(Stat_List_unit,FUNCTION); |
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[78] | 324 | }; |
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| 325 | |
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| 326 | }; // end namespace stat_list_unit |
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| 327 | }; // end namespace register_translation_unit |
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| 328 | }; // end namespace rename_unit |
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| 329 | }; // end namespace ooo_engine |
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| 330 | }; // end namespace multi_ooo_engine |
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| 331 | }; // end namespace core |
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| 332 | |
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| 333 | }; // end namespace behavioural |
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| 334 | }; // end namespace morpheo |
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| 335 | #endif |
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