Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp

Timestamp:

May 16, 2009, 4:42:39 PM (15 years ago)

Author:

rosiere

Message:

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench?
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp

@@ -86 +86 @@
               if (PORT_READ(in_INSERT_WRITE_RD [i]))
                 {
-                  Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]);
-
-                  log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RD - num_reg new : %d",num_reg);
-
-                  uint32_t bank = num_reg >> _param->_shift_gpr;
-                  uint32_t reg  = num_reg  & _param->_mask_gpr ;
-                  gpr_stat_list [bank][reg].insert_write();
+                  {
+                    Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [i]);
+                    
+                    log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RD - num_reg old : %d",num_reg);
+                    
+                    uint32_t bank = num_reg >> _param->_shift_gpr;
+                    uint32_t reg  = num_reg  & _param->_mask_gpr ;
+                    gpr_stat_list [bank][reg].insert_write_old();
+                  }
+                  {
+                    Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]);
+                    
+                    log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RD - num_reg new : %d",num_reg);
+                    
+                    uint32_t bank = num_reg >> _param->_shift_gpr;
+                    uint32_t reg  = num_reg  & _param->_mask_gpr ;
+                    gpr_stat_list [bank][reg].insert_write_new();
+                  }
                 }
 
               if (PORT_READ(in_INSERT_WRITE_RE [i]))
                 {
-                  Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]);
-
-                  log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RE - num_reg new : %d",num_reg);
-
-                  uint32_t bank = num_reg >> _param->_shift_spr;
-                  uint32_t reg  = num_reg  & _param->_mask_spr ;
-                  spr_stat_list [bank][reg].insert_write();
-                }
+                  {
+                    Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [i]);
+                    
+                    log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RE - num_reg old : %d",num_reg);
+                    
+                    uint32_t bank = num_reg >> _param->_shift_spr;
+                    uint32_t reg  = num_reg  & _param->_mask_spr ;
+                    spr_stat_list [bank][reg].insert_write_old();
+                  }
+                  {
+                    Tspecial_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]);
+                    
+                    log_printf(TRACE,Stat_List_unit,FUNCTION,"    * WRITE_RE - num_reg new : %d",num_reg);
+                    
+                    uint32_t bank = num_reg >> _param->_shift_spr;
+                    uint32_t reg  = num_reg  & _param->_mask_spr ;
+                    spr_stat_list [bank][reg].insert_write_new();
+                  }
+                }
             }