1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Stat_List_unit_transition.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace stat_list_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Stat_List_unit::transition" |
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23 | void Stat_List_unit::transition (void) |
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24 | { |
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25 | log_begin(Stat_List_unit,FUNCTION); |
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26 | log_function(Stat_List_unit,FUNCTION,_name.c_str()); |
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27 | |
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28 | if (PORT_READ(in_NRESET) == 0) |
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29 | { |
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30 | uint32_t gpr = 0; |
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31 | uint32_t spr = 0; |
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32 | |
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33 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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34 | { |
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35 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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36 | gpr_stat_list [i][j].reset((gpr++)<_param->_nb_gpr_use_init); |
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37 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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38 | spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); |
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39 | } |
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40 | internal_GPR_PTR_FREE = 0; |
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41 | internal_SPR_PTR_FREE = 0; |
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42 | } |
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43 | else |
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44 | { |
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45 | // ===================================================== |
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46 | // =====[ INSERT ]====================================== |
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47 | // ===================================================== |
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48 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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49 | if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) |
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50 | { |
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51 | if (PORT_READ(in_INSERT_READ_RA [i])) |
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52 | { |
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53 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); |
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54 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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55 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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56 | gpr_stat_list [bank][reg].insert_read(); |
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57 | } |
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58 | |
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59 | if (PORT_READ(in_INSERT_READ_RB [i])) |
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60 | { |
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61 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); |
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62 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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63 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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64 | gpr_stat_list [bank][reg].insert_read(); |
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65 | } |
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66 | |
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67 | if (PORT_READ(in_INSERT_READ_RC [i])) |
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68 | { |
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69 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); |
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70 | uint32_t bank = num_reg >> _param->_shift_spr; |
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71 | uint32_t reg = num_reg & _param->_mask_spr ; |
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72 | spr_stat_list [bank][reg].insert_read(); |
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73 | } |
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74 | |
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75 | if (PORT_READ(in_INSERT_WRITE_RD [i])) |
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76 | { |
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77 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); |
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78 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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79 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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80 | gpr_stat_list [bank][reg].insert_write(); |
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81 | } |
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82 | |
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83 | if (PORT_READ(in_INSERT_WRITE_RE [i])) |
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84 | { |
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85 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); |
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86 | uint32_t bank = num_reg >> _param->_shift_spr; |
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87 | uint32_t reg = num_reg & _param->_mask_spr ; |
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88 | spr_stat_list [bank][reg].insert_write(); |
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89 | } |
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90 | } |
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91 | |
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92 | // ===================================================== |
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93 | // =====[ RETIRE ]====================================== |
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94 | // ===================================================== |
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95 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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96 | if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) |
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97 | { |
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98 | if (PORT_READ(in_RETIRE_READ_RA [i])) |
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99 | { |
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100 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); |
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101 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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102 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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103 | gpr_stat_list [bank][reg].retire_read(); |
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104 | } |
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105 | |
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106 | if (PORT_READ(in_RETIRE_READ_RB [i])) |
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107 | { |
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108 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); |
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109 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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110 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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111 | gpr_stat_list [bank][reg].retire_read(); |
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112 | } |
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113 | |
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114 | if (PORT_READ(in_RETIRE_READ_RC [i])) |
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115 | { |
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116 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); |
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117 | uint32_t bank = num_reg >> _param->_shift_spr; |
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118 | uint32_t reg = num_reg & _param->_mask_spr ; |
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119 | spr_stat_list [bank][reg].retire_read(); |
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120 | } |
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121 | |
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122 | if (PORT_READ(in_RETIRE_WRITE_RD [i])) |
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123 | { |
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124 | Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); |
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125 | { |
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126 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); |
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127 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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128 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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129 | gpr_stat_list [bank][reg].retire_write_old(restore_old); |
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130 | } |
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131 | { |
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132 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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133 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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134 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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135 | gpr_stat_list [bank][reg].retire_write_new(restore_old); |
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136 | } |
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137 | } |
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138 | |
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139 | if (PORT_READ(in_RETIRE_WRITE_RE [i])) |
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140 | { |
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141 | Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); |
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142 | { |
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143 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); |
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144 | uint32_t bank = num_reg >> _param->_shift_spr; |
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145 | uint32_t reg = num_reg & _param->_mask_spr ; |
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146 | spr_stat_list [bank][reg].retire_write_old(restore_old); |
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147 | } |
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148 | { |
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149 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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150 | uint32_t bank = num_reg >> _param->_shift_spr; |
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151 | uint32_t reg = num_reg & _param->_mask_spr ; |
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152 | spr_stat_list [bank][reg].retire_write_new(restore_old); |
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153 | } |
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154 | } |
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155 | } |
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156 | |
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157 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
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158 | { |
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159 | // ===================================================== |
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160 | // =====[ PUSH_GPR ]==================================== |
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161 | // ===================================================== |
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162 | if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) |
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163 | gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][internal_GPR_PTR_FREE].free(); |
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164 | |
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165 | // ===================================================== |
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166 | // =====[ PUSH_SPR ]==================================== |
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167 | // ===================================================== |
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168 | if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) |
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169 | spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][internal_SPR_PTR_FREE].free(); |
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170 | } |
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171 | |
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172 | // Update pointer |
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173 | internal_GPR_PTR_FREE = ((internal_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:internal_GPR_PTR_FREE)-1; |
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174 | internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1; |
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175 | } |
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176 | |
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177 | |
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178 | #if (DEBUG >= DEBUG_TRACE) |
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179 | log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); |
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180 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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181 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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182 | log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", |
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183 | i, |
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184 | j, |
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185 | (i<<_param->_shift_gpr)|j, |
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186 | gpr_stat_list[i][j]._is_free, |
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187 | gpr_stat_list[i][j]._is_link, |
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188 | gpr_stat_list[i][j]._is_valid, |
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189 | gpr_stat_list[i][j]._counter); |
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190 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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191 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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192 | log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", |
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193 | i, |
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194 | j, |
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195 | (i<<_param->_shift_spr)|j, |
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196 | spr_stat_list[i][j]._is_free, |
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197 | spr_stat_list[i][j]._is_link, |
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198 | spr_stat_list[i][j]._is_valid, |
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199 | spr_stat_list[i][j]._counter); |
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200 | #endif |
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201 | |
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202 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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203 | end_cycle (); |
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204 | #endif |
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205 | |
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206 | log_end(Stat_List_unit,FUNCTION); |
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207 | }; |
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208 | |
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209 | }; // end namespace stat_list_unit |
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210 | }; // end namespace register_translation_unit |
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211 | }; // end namespace rename_unit |
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212 | }; // end namespace ooo_engine |
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213 | }; // end namespace multi_ooo_engine |
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214 | }; // end namespace core |
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215 | |
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216 | }; // end namespace behavioural |
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217 | }; // end namespace morpheo |
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218 | #endif |
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