[88] | 1 | /* |
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| 2 | * $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h" |
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| 10 | #include "Behavioural/include/Allocation.h" |
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| 11 | |
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| 12 | void test (string name, |
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| 13 | morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * _param) |
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| 14 | { |
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| 15 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 16 | |
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| 17 | #ifdef STATISTICS |
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| 18 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); |
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| 19 | #endif |
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| 20 | |
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| 21 | Tusage_t _usage = USE_ALL; |
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| 22 | |
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| 23 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 24 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 25 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 26 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 27 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 28 | _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 29 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 30 | |
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| 31 | Special_Register_unit * _Special_Register_unit = new Special_Register_unit |
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| 32 | (name.c_str(), |
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| 33 | #ifdef STATISTICS |
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| 34 | _parameters_statistics, |
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| 35 | #endif |
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| 36 | _param, |
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| 37 | _usage); |
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| 38 | |
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| 39 | #ifdef SYSTEMC |
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| 40 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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| 41 | { |
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| 42 | /********************************************************************* |
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| 43 | * Déclarations des signaux |
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| 44 | *********************************************************************/ |
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| 45 | string rename; |
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| 46 | |
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| 47 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 48 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 49 | |
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| 50 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_VAL ," in_SPR_ACCESS_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); |
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| 51 | ALLOC1_SC_SIGNAL(out_SPR_ACCESS_ACK ,"out_SPR_ACCESS_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); |
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| 52 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID," in_SPR_ACCESS_FRONT_END_ID",Tcontext_t ,_param->_nb_inst_reexecute); |
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| 53 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ," in_SPR_ACCESS_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); |
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| 54 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WEN ," in_SPR_ACCESS_WEN ",Tcontrol_t ,_param->_nb_inst_reexecute); |
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| 55 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ," in_SPR_ACCESS_NUM_GROUP ",Tspr_address_t,_param->_nb_inst_reexecute); |
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| 56 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ," in_SPR_ACCESS_NUM_REG ",Tspr_address_t,_param->_nb_inst_reexecute); |
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| 57 | ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WDATA ," in_SPR_ACCESS_WDATA ",Tspr_t ,_param->_nb_inst_reexecute); |
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| 58 | ALLOC1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,"out_SPR_ACCESS_RDATA ",Tspr_t ,_param->_nb_inst_reexecute); |
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| 59 | ALLOC1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,"out_SPR_ACCESS_INVALID ",Tcontrol_t ,_param->_nb_inst_reexecute); |
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| 60 | ALLOC2_SC_SIGNAL(out_SPR_READ_SR ,"out_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 61 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_VAL ," in_SPR_COMMIT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 62 | ALLOC2_SC_SIGNAL(out_SPR_COMMIT_ACK ,"out_SPR_COMMIT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 63 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ," in_SPR_COMMIT_SR_F_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 64 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F ," in_SPR_COMMIT_SR_F ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 65 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ," in_SPR_COMMIT_SR_CY_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 66 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ," in_SPR_COMMIT_SR_CY ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 67 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ," in_SPR_COMMIT_SR_OV_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 68 | ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ," in_SPR_COMMIT_SR_OV ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 69 | |
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| 70 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_VAL ," in_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 71 | ALLOC2_SC_SIGNAL(out_SPR_EVENT_ACK ,"out_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 72 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_EPCR ," in_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 73 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ," in_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 74 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR ," in_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 75 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ," in_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 76 | ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ," in_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); |
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| 77 | |
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| 78 | /******************************************************** |
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| 79 | * Instanciation |
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| 80 | ********************************************************/ |
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| 81 | |
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| 82 | msg(_("<%s> : Instanciation of _Special_Register_unit.\n"),name.c_str()); |
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| 83 | |
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| 84 | (*(_Special_Register_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 85 | (*(_Special_Register_unit->in_NRESET)) (*(in_NRESET)); |
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| 86 | |
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| 87 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute); |
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| 88 | INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); |
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| 89 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute); |
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| 90 | if (_param->_have_port_front_end_id) |
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| 91 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute); |
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| 92 | if (_param->_have_port_context_id) |
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| 93 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute); |
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| 94 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute); |
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| 95 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute); |
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| 96 | INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute); |
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| 97 | INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute); |
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| 98 | INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute); |
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| 99 | |
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| 100 | INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 101 | |
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| 102 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 103 | INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 104 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 105 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 106 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 107 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 108 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 109 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 110 | |
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| 111 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 112 | INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 113 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 114 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 115 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 116 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 117 | INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 118 | |
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| 119 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 120 | |
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| 121 | Time * _time = new Time(); |
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| 122 | |
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| 123 | /******************************************************** |
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| 124 | * Simulation - Begin |
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| 125 | ********************************************************/ |
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| 126 | |
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| 127 | // Initialisation |
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| 128 | |
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| 129 | const uint32_t seed = 0; |
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| 130 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 131 | |
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| 132 | srand(seed); |
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| 133 | |
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| 134 | const int32_t percent_transaction_spr_access = 75; |
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| 135 | const int32_t percent_transaction_spr_commit = 75; |
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| 136 | const int32_t percent_transaction_spr_event = 75; |
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| 137 | |
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| 138 | SC_START(0); |
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| 139 | LABEL("Initialisation"); |
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| 140 | |
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| 141 | LABEL("Reset"); |
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| 142 | in_NRESET->write(0); |
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| 143 | SC_START(5); |
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| 144 | in_NRESET->write(1); |
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| 145 | |
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| 146 | Tspr_t sr [_param->_nb_front_end][_param->_max_nb_context]; |
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| 147 | Tspr_t dccr [_param->_nb_front_end][_param->_max_nb_context]; |
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| 148 | |
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| 149 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 150 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 151 | { |
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| 152 | sr [i][j] = 0x00008001; |
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| 153 | dccr [i][j] = 0x0; |
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| 154 | TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]); |
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| 155 | } |
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| 156 | |
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| 157 | LABEL("Loop of Test"); |
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| 158 | |
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| 159 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 160 | { |
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| 161 | LABEL("Iteration %d",iteration); |
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| 162 | |
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| 163 | Tcontext_t front_end = rand()%_param->_nb_front_end; |
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| 164 | Tcontext_t context = rand()%_param->_nb_context[front_end]; |
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| 165 | uint32_t port = rand()%_param->_nb_inst_reexecute; |
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| 166 | uint32_t config = rand()%3; |
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| 167 | Tcontrol_t wen = rand()%2; |
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| 168 | Tspr_t wdata = rand(); |
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| 169 | { |
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| 170 | in_SPR_ACCESS_VAL [port]->write((rand()%100)<percent_transaction_spr_access); |
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| 171 | in_SPR_ACCESS_FRONT_END_ID [port]->write(front_end); |
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| 172 | in_SPR_ACCESS_CONTEXT_ID [port]->write(context); |
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| 173 | |
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| 174 | switch (config) |
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| 175 | { |
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| 176 | case 0 : |
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| 177 | wen = 0; |
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| 178 | in_SPR_ACCESS_NUM_GROUP [port]->write(0); |
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| 179 | in_SPR_ACCESS_NUM_REG [port]->write(17); |
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| 180 | break; |
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| 181 | case 1 : |
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| 182 | in_SPR_ACCESS_NUM_GROUP [port]->write(3); |
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| 183 | in_SPR_ACCESS_NUM_REG [port]->write(0); |
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| 184 | break; |
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| 185 | case 2 : |
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| 186 | in_SPR_ACCESS_NUM_GROUP [port]->write(5); |
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| 187 | in_SPR_ACCESS_NUM_REG [port]->write(1); |
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| 188 | break; |
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| 189 | } |
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| 190 | |
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| 191 | in_SPR_ACCESS_WEN [port]->write(wen); |
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| 192 | in_SPR_ACCESS_WDATA [port]->write(wdata); |
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| 193 | } |
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| 194 | |
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| 195 | { |
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| 196 | in_SPR_COMMIT_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit); |
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| 197 | in_SPR_COMMIT_SR_F_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit); |
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| 198 | in_SPR_COMMIT_SR_CY_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit); |
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| 199 | in_SPR_COMMIT_SR_OV_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit); |
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| 200 | in_SPR_COMMIT_SR_F [front_end][context]->write(rand()%2); |
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| 201 | in_SPR_COMMIT_SR_CY [front_end][context]->write(rand()%2); |
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| 202 | in_SPR_COMMIT_SR_OV [front_end][context]->write(rand()%2); |
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| 203 | } |
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| 204 | |
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| 205 | { |
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| 206 | in_SPR_EVENT_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_event); |
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| 207 | in_SPR_EVENT_EPCR [front_end][context]->write(rand()); |
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| 208 | in_SPR_EVENT_EEAR_WEN [front_end][context]->write(rand()%2); |
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| 209 | in_SPR_EVENT_EEAR [front_end][context]->write(rand()); |
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| 210 | in_SPR_EVENT_SR_DSX [front_end][context]->write(rand()%2); |
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| 211 | in_SPR_EVENT_SR_TO_ESR [front_end][context]->write(rand()%2); |
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| 212 | } |
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| 213 | |
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| 214 | SC_START(0); |
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| 215 | |
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| 216 | if (in_SPR_ACCESS_VAL [port]->read() and out_SPR_ACCESS_ACK [port]->read()) |
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| 217 | { |
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| 218 | LABEL("SPR_ACCESS [%d] - Transaction accepted.",port); |
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| 219 | LABEL(" * front_end : %d" ,(unsigned int)front_end); |
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| 220 | LABEL(" * context : %d" ,(unsigned int)context ); |
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| 221 | LABEL(" * config : %d" ,(unsigned int)config ); |
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| 222 | LABEL(" * wen : %d" ,(unsigned int)wen ); |
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| 223 | LABEL(" * wdata : %d" ,(unsigned int)wdata&0xff ); |
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| 224 | |
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| 225 | switch (config) |
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| 226 | { |
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| 227 | case 0 : |
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| 228 | TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),sr[front_end][context]); |
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| 229 | TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0); |
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| 230 | break; |
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| 231 | case 1 : |
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| 232 | if (sr[front_end][context] & 1) |
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| 233 | { |
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| 234 | TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),dccr[front_end][context]&0xff); |
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| 235 | TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0); |
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| 236 | |
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| 237 | if (wen) |
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| 238 | dccr[front_end][context] = wdata; |
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| 239 | } |
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| 240 | else |
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| 241 | TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1); |
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| 242 | break; |
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| 243 | case 2 : |
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| 244 | TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1); |
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| 245 | break; |
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| 246 | } |
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| 247 | } |
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| 248 | |
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| 249 | if (in_SPR_COMMIT_VAL [front_end][context]->read() and out_SPR_COMMIT_ACK [front_end][context]->read()) |
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| 250 | { |
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| 251 | LABEL("SPR_COMMIT [%d][%d] - Transaction accepted.",front_end,context); |
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| 252 | LABEL(" * cy_val : %d",in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read()); |
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| 253 | LABEL(" * cy : %d",in_SPR_COMMIT_SR_CY [front_end][context]->read()); |
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| 254 | LABEL(" * ov_val : %d",in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read()); |
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| 255 | LABEL(" * ov : %d",in_SPR_COMMIT_SR_OV [front_end][context]->read()); |
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| 256 | LABEL(" * f_val : %d",in_SPR_COMMIT_SR_F_VAL [front_end][context]->read()); |
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| 257 | LABEL(" * f : %d",in_SPR_COMMIT_SR_F [front_end][context]->read()); |
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| 258 | LABEL(" * sr (old) : 0x%d",sr[front_end][context]); |
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| 259 | if (in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read()) |
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| 260 | CHANGE_FLAG(sr[front_end][context], 10, in_SPR_COMMIT_SR_CY [front_end][context]->read()); |
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| 261 | |
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| 262 | if (in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read()) |
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| 263 | CHANGE_FLAG(sr[front_end][context], 11, in_SPR_COMMIT_SR_OV [front_end][context]->read()); |
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| 264 | |
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| 265 | if (in_SPR_COMMIT_SR_F_VAL [front_end][context]->read()) |
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| 266 | CHANGE_FLAG(sr[front_end][context], 9, in_SPR_COMMIT_SR_F [front_end][context]->read()); |
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| 267 | LABEL(" * sr (new) : 0x%d",sr[front_end][context]); |
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| 268 | } |
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| 269 | |
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| 270 | if (in_SPR_EVENT_VAL [front_end][context]->read() and out_SPR_EVENT_ACK [front_end][context]->read()) |
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| 271 | { |
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| 272 | LABEL("SPR_EVENT [%d][%d] - Transaction accepted.",front_end,context); |
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| 273 | |
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| 274 | CHANGE_FLAG(sr[front_end][context], 13, in_SPR_EVENT_SR_DSX [front_end][context]->read()); |
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| 275 | } |
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| 276 | |
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| 277 | SC_START(1); |
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| 278 | |
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| 279 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 280 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 281 | TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]); |
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| 282 | |
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| 283 | in_SPR_ACCESS_VAL [port]->write(0); |
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| 284 | in_SPR_COMMIT_VAL [front_end][context]->write(0); |
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| 285 | } |
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| 286 | |
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| 287 | /******************************************************** |
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| 288 | * Simulation - End |
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| 289 | ********************************************************/ |
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| 290 | |
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| 291 | TEST_OK ("End of Simulation"); |
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| 292 | delete _time; |
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| 293 | |
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| 294 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 295 | |
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| 296 | delete in_CLOCK; |
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| 297 | delete in_NRESET; |
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| 298 | |
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| 299 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute); |
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| 300 | DELETE1_SC_SIGNAL(out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); |
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| 301 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute); |
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| 302 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute); |
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| 303 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute); |
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| 304 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute); |
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| 305 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute); |
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| 306 | DELETE1_SC_SIGNAL( in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute); |
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| 307 | DELETE1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute); |
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| 308 | DELETE1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute); |
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| 309 | |
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| 310 | DELETE2_SC_SIGNAL(out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 311 | |
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| 312 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 313 | DELETE2_SC_SIGNAL(out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 314 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 315 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 316 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 317 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 318 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 319 | DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 320 | |
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| 321 | DELETE2_SC_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 322 | DELETE2_SC_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 323 | DELETE2_SC_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 324 | DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 325 | DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 326 | DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 327 | DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 328 | } |
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| 329 | #endif |
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| 330 | |
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| 331 | delete _Special_Register_unit; |
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| 332 | #ifdef STATISTICS |
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| 333 | delete _parameters_statistics; |
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| 334 | #endif |
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| 335 | } |
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