source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h@ 117

Last change on this file since 117 was 117, checked in by rosiere, 17 years ago

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
  • Property svn:keywords set to Id
File size: 20.0 KB
Line 
1#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_SPR_h
2#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_SPR_h
3
4/*
5 * $Id: SPR.h 117 2009-05-16 14:42:39Z rosiere $
6 *
7 * [ Description ]
8 *
9 */
10
11#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h"
12#include "Behavioural/include/SPR.h"
13
14namespace morpheo {
15namespace behavioural {
16namespace core {
17namespace multi_ooo_engine {
18namespace ooo_engine {
19namespace special_register_unit {
20
21 //----------------------------------------------------------
22 // [x][x] GENERIC
23 //----------------------------------------------------------
24 class GENERIC : public morpheo::behavioural::SPR
25 {
26 public : Tspr_t x : 32;
27
28 public : GENERIC(uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) {};
29
30 public : void reset (void )
31 {
32 x = 0;
33 };
34 public : Tspr_t read (void )
35 {
36 return x;
37 };
38 public : void write (Tspr_t x)
39 {
40 this->x = x;
41 };
42 };
43
44 //----------------------------------------------------------
45 // [0][0] VR
46 //----------------------------------------------------------
47 class VR : public morpheo::behavioural::SPR
48 {
49 public : const Tspr_t ver : 8;
50 public : const Tspr_t _res :10;
51 public : const Tspr_t cfg : 8;
52 public : const Tspr_t rev : 8;
53
54 public : VR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
55 // SPR (),
56 ver (0),
57 _res (0),
58 cfg (0),
59 rev (0){};
60
61 public : void reset (void ) {};
62 public : Tspr_t read (void )
63 {
64 return ((ver << 24) |
65 (cfg << 16) |
66 (rev << 0));
67 }
68 public : void write (Tspr_t x) {}; // All bit field is Read Only
69 };
70
71 //----------------------------------------------------------
72 // [0][1] UPR
73 //----------------------------------------------------------
74 class UPR : public morpheo::behavioural::SPR
75 {
76 public : const Tspr_t cup : 8;
77 public : const Tspr_t _res : 8;
78 public : const Tspr_t ttp : 1;
79 public : const Tspr_t pmp : 1;
80 public : const Tspr_t picp : 1;
81 public : const Tspr_t pcup : 1;
82 public : const Tspr_t dup : 1;
83 public : const Tspr_t mp : 1;
84 public : const Tspr_t imp : 1;
85 public : const Tspr_t dmp : 1;
86 public : const Tspr_t icp : 1;
87 public : const Tspr_t dcp : 1;
88 public : const Tspr_t up : 1;
89
90 public : UPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
91 SPR (),
92 cup (0),
93 _res (0),
94 ttp (0),
95 pmp (0),
96 picp (0),
97 pcup (0),
98 dup (0),
99 mp (0),
100 imp (0),
101 dmp (0),
102 icp (0),
103 dcp (0),
104 up (0)
105 {};
106
107 public : void reset (void ) {};
108 public : Tspr_t read (void )
109 {
110 return ((cup << 24) |
111 (ttp << 10) |
112 (pmp << 9) |
113 (picp << 8) |
114 (pcup << 7) |
115 (dup << 6) |
116 (mp << 5) |
117 (imp << 4) |
118 (dmp << 3) |
119 (icp << 2) |
120 (dcp << 1) |
121 (up << 0));
122 }
123 public : void write (Tspr_t x) {}; // All bit field is Read Only
124 };
125
126 //----------------------------------------------------------
127 // [0][2] CPUCFGR
128 //----------------------------------------------------------
129 class CPUCFGR : public morpheo::behavioural::SPR
130 {
131 public : const Tspr_t _res : 22;
132 public : const Tspr_t ov64s : 1;
133 public : const Tspr_t of64s : 1;
134 public : const Tspr_t of32s : 1;
135 public : const Tspr_t ob64s : 1;
136 public : const Tspr_t ob32s : 1;
137 public : const Tspr_t cgf : 1;
138 public : const Tspr_t nsdf : 1;
139
140 public : CPUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
141 _res (0),
142 ov64s (0),
143 of64s (0),
144 of32s (0),
145 ob64s (0),
146 ob32s (0),
147 cgf (0),
148 nsdf (0)
149 {};
150
151 public : void reset (void ) {};
152 public : Tspr_t read (void )
153 {
154 return ((ov64s << 9) |
155 (of64s << 8) |
156 (of32s << 7) |
157 (ob64s << 6) |
158 (ob32s << 5) |
159 (cgf << 4) |
160 (nsdf << 0) );
161 }
162 public : void write (Tspr_t x) {}; // All bit field is Read Only
163 };
164
165 //----------------------------------------------------------
166 // [0][3] DMMUCFGR
167 //----------------------------------------------------------
168 class DMMUCFGR : public morpheo::behavioural::SPR
169 {
170 public : const Tspr_t _res : 20;
171 public : const Tspr_t htr : 1;
172 public : const Tspr_t teiri : 1;
173 public : const Tspr_t pri : 1;
174 public : const Tspr_t cri : 1;
175 public : const Tspr_t nae : 3;
176 public : const Tspr_t nts : 3;
177 public : const Tspr_t ntw : 2;
178
179 public : DMMUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
180 _res (0),
181 htr (0),
182 teiri (0),
183 pri (0),
184 cri (0),
185 nae (0),
186 nts (0),
187 ntw (0)
188 {};
189 public : void reset (void ) {};
190 public : Tspr_t read (void )
191 {
192 return ((htr << 11) |
193 (teiri << 10) |
194 (pri << 9) |
195 (cri << 8) |
196 (nae << 5) |
197 (nts << 2) |
198 (ntw << 0) );
199 };
200 public : void write (Tspr_t x) {}; // All bit field is Read Only
201 };
202
203 //----------------------------------------------------------
204 // [0][4] IMMUCFGR
205 //----------------------------------------------------------
206 class IMMUCFGR : public morpheo::behavioural::SPR
207 {
208 public : const Tspr_t _res : 20;
209 public : const Tspr_t htr : 1;
210 public : const Tspr_t teiri : 1;
211 public : const Tspr_t pri : 1;
212 public : const Tspr_t cri : 1;
213 public : const Tspr_t nae : 3;
214 public : const Tspr_t nts : 3;
215 public : const Tspr_t ntw : 2;
216
217 public : IMMUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
218 _res (0),
219 htr (0),
220 teiri (0),
221 pri (0),
222 cri (0),
223 nae (0),
224 nts (0),
225 ntw (0)
226 {};
227 public : void reset (void ) {};
228 public : Tspr_t read (void )
229 {
230 return ((htr << 11) |
231 (teiri << 10) |
232 (pri << 9) |
233 (cri << 8) |
234 (nae << 5) |
235 (nts << 2) |
236 (ntw << 0) );
237 };
238 public : void write (Tspr_t x) {}; // All bit field is Read Only
239 };
240
241 //----------------------------------------------------------
242 // [0][5] DCCFGR
243 //----------------------------------------------------------
244 class DCCFGR : public morpheo::behavioural::SPR
245 {
246 public : const Tspr_t _res : 17;
247 public : const Tspr_t cbwbri : 1;
248 public : const Tspr_t cbfri : 1;
249 public : const Tspr_t cblri : 1;
250 public : const Tspr_t cbpri : 1;
251 public : const Tspr_t cbiri : 1;
252 public : const Tspr_t ccri : 1;
253 public : const Tspr_t cws : 1;
254 public : const Tspr_t cbs : 1;
255 public : const Tspr_t ncs : 4;
256 public : const Tspr_t ncw : 3;
257
258 public : DCCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
259 _res (0),
260 cbwbri (0),
261 cbfri (0),
262 cblri (0),
263 cbpri (0),
264 cbiri (0),
265 ccri (0),
266 cws (0),
267 cbs (0),
268 ncs (0),
269 ncw (0)
270 {};
271 public : void reset (void ) {};
272 public : Tspr_t read (void )
273 {
274 return ((cbwbri << 14) |
275 (cbfri << 13) |
276 (cblri << 12) |
277 (cbpri << 11) |
278 (cbiri << 10) |
279 (ccri << 9) |
280 (cws << 8) |
281 (cbs << 7) |
282 (ncs << 3) |
283 (ncw << 0) );
284 };
285 public : void write (Tspr_t x) {}; // All bit field is Read Only
286 };
287
288 //----------------------------------------------------------
289 // [0][6] ICCFGR
290 //----------------------------------------------------------
291 class ICCFGR : public morpheo::behavioural::SPR
292 {
293 public : const Tspr_t _res1 : 19;
294 public : const Tspr_t cblri : 1;
295 public : const Tspr_t cbpri : 1;
296 public : const Tspr_t cbiri : 1;
297 public : const Tspr_t ccri : 1;
298 public : const Tspr_t _res2 : 1;
299 public : const Tspr_t cbs : 1;
300 public : const Tspr_t ncs : 4;
301 public : const Tspr_t ncw : 3;
302
303 public : ICCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
304 _res1 (0),
305 cblri (0),
306 cbpri (0),
307 cbiri (0),
308 ccri (0),
309 _res2 (0),
310 cbs (0),
311 ncs (0),
312 ncw (0)
313 {};
314 public : void reset (void ) {};
315 public : Tspr_t read (void )
316 {
317 return ((cblri << 12) |
318 (cbpri << 11) |
319 (cbiri << 10) |
320 (ccri << 9) |
321 (cbs << 7) |
322 (ncs << 3) |
323 (ncw << 0) );
324 };
325 public : void write (Tspr_t x) {}; // All bit field is Read Only
326 };
327
328 //----------------------------------------------------------
329 // [0][7] DCFGR
330 //----------------------------------------------------------
331 class DCFGR : public morpheo::behavioural::SPR
332 {
333 public : const Tspr_t _res : 28;
334 public : const Tspr_t wpci : 1;
335 public : const Tspr_t ndp : 3;
336
337 public : DCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
338 _res (0),
339 wpci (0),
340 ndp (0)
341 {};
342 public : void reset (void ) {};
343 public : Tspr_t read (void )
344 {
345 return ((wpci << 3) |
346 (ndp << 0) );
347 };
348 public : void write (Tspr_t x) {}; // All bit field is Read Only
349 };
350
351 //----------------------------------------------------------
352 // [0][8] PCCFGR
353 //----------------------------------------------------------
354 class PCCFGR : public morpheo::behavioural::SPR
355 {
356 public : const Tspr_t _res : 29;
357 public : const Tspr_t npc : 3;
358
359 public : PCCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
360 _res (0),
361 npc (0)
362 {};
363 public : void reset (void ) {};
364 public : Tspr_t read (void )
365 {
366 return ((npc << 0));
367 };
368 public : void write (Tspr_t x) {}; // All bit field is Read Only
369 };
370
371 //----------------------------------------------------------
372 // [0][16] NPC
373 //----------------------------------------------------------
374 class NPC : public GENERIC
375 {
376 public : NPC (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
377 };
378
379 //----------------------------------------------------------
380 // [0][17] SR
381 //----------------------------------------------------------
382 class SR : public morpheo::behavioural::SPR
383 {
384 public : Tspr_t cid : 4;
385 public : const Tspr_t _res : 11;
386 public : Tspr_t sumra : 1;
387 public : const Tspr_t fo : 1;
388 public : Tspr_t eph : 1;
389 public : Tspr_t dsx : 1;
390 public : Tspr_t ove : 1;
391 public : Tspr_t ov : 1;
392 public : Tspr_t cy : 1;
393 public : Tspr_t f : 1;
394 public : Tspr_t ce : 1;
395 public : Tspr_t lee : 1;
396 public : Tspr_t ime : 1;
397 public : Tspr_t dme : 1;
398 public : Tspr_t ice : 1;
399 public : Tspr_t dce : 1;
400 public : Tspr_t iee : 1;
401 public : Tspr_t tee : 1;
402 public : Tspr_t sm : 1;
403
404 public : SR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
405 _res (0),
406 fo (1)
407 {};
408 public : void reset (void )
409 {
410 cid = 0;
411 sumra = 0;
412 eph = 0;
413 dsx = 0;
414 ove = 0;
415 ov = 0;
416 cy = 0;
417 f = 0;
418 ce = 0;
419 lee = 0;
420 ime = 0;
421 dme = 0;
422 ice = 0;
423 dce = 0;
424 iee = 0;
425 tee = 0;
426 sm = 1;
427 };
428 public : Tspr_t read (void )
429 {
430 return ((cid << 28) |
431 (sumra << 16) |
432 (fo << 15) |
433 (eph << 14) |
434 (dsx << 13) |
435 (ove << 12) |
436 (ov << 11) |
437 (cy << 10) |
438 (f << 9) |
439 (ce << 8) |
440 (lee << 7) |
441 (ime << 6) |
442 (dme << 5) |
443 (ice << 4) |
444 (dce << 3) |
445 (iee << 2) |
446 (tee << 1) |
447 (sm << 0) );
448 };
449 public : void write (Tspr_t x)
450 {
451 cid = x >> 28;
452 sumra = x >> 16;
453 eph = x >> 14;
454 dsx = x >> 13;
455 ove = x >> 12;
456 ov = x >> 11;
457 cy = x >> 10;
458 f = x >> 9;
459 ce = x >> 8;
460 lee = x >> 7;
461 ime = x >> 6;
462 dme = x >> 5;
463 ice = x >> 4;
464 dce = x >> 3;
465 iee = x >> 2;
466 tee = x >> 1;
467 sm = x >> 0;
468 };
469 };
470
471 //----------------------------------------------------------
472 // [0][18] PPC
473 //----------------------------------------------------------
474 class PPC : public GENERIC
475 {
476 public : PPC (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
477 };
478
479 //----------------------------------------------------------
480 // [0][20] FPCSR
481 //----------------------------------------------------------
482 class FPCSR : public morpheo::behavioural::SPR
483 {
484 public : const Tspr_t _res : 20;
485 public : Tspr_t dzf : 1;
486 public : Tspr_t inf : 1;
487 public : Tspr_t ivf : 1;
488 public : Tspr_t ixf : 1;
489 public : Tspr_t zf : 1;
490 public : Tspr_t qnf : 1;
491 public : Tspr_t snf : 1;
492 public : Tspr_t unf : 1;
493 public : Tspr_t ovf : 1;
494 public : Tspr_t rm : 2;
495 public : Tspr_t fpee : 1;
496
497 public : FPCSR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
498 _res (0)
499 {};
500 public : void reset (void )
501 {
502 dzf = 0;
503 inf = 0;
504 ivf = 0;
505 ixf = 0;
506 zf = 0;
507 qnf = 0;
508 snf = 0;
509 unf = 0;
510 ovf = 0;
511 rm = 0;
512 fpee = 0;
513 };
514 public : Tspr_t read (void )
515 {
516 return ((dzf << 11) |
517 (inf << 10) |
518 (ivf << 9) |
519 (ixf << 8) |
520 (zf << 7) |
521 (qnf << 6) |
522 (snf << 5) |
523 (unf << 4) |
524 (ovf << 3) |
525 (rm << 1) |
526 (fpee << 0) );
527 };
528 public : void write (Tspr_t x)
529 {
530 dzf = x >> 11;
531 inf = x >> 10;
532 ivf = x >> 9;
533 ixf = x >> 8;
534 zf = x >> 7;
535 qnf = x >> 6;
536 snf = x >> 5;
537 unf = x >> 4;
538 ovf = x >> 3;
539 rm = x >> 1;
540 fpee = x >> 0;
541 };
542 };
543
544 //----------------------------------------------------------
545 // [0][21] CID
546 //----------------------------------------------------------
547 class CID : public morpheo::behavioural::SPR
548 {
549 private: const Tspr_t _cpu_id : 32; // cpu_id reset value
550 public : Tspr_t cpu_id : 32;
551
552 public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
553 _cpu_id ((param==NULL)?0:param->_translate_num_context_to_num_thread[num_front_end][num_context])
554 {};
555 public : void reset (void )
556 {
557 cpu_id = _cpu_id;
558 };
559 public : Tspr_t read (void )
560 {
561 return ((cpu_id << 0));
562 };
563 public : void write (Tspr_t x)
564 {
565 cpu_id = x >> 0;
566 };
567 };
568
569 //----------------------------------------------------------
570 // [0][22] TID - Thread Id
571 //----------------------------------------------------------
572 class TID : public morpheo::behavioural::SPR
573 {
574 public : Tspr_t thread_id : 32;
575
576 public : TID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL)
577 {};
578 public : void reset (void )
579 {
580 };
581 public : Tspr_t read (void )
582 {
583 return ((thread_id << 0));
584 };
585 public : void write (Tspr_t x)
586 {
587 thread_id = x >> 0;
588 };
589 };
590
591 //----------------------------------------------------------
592 // [0][23] TSR - Thread Status Register
593 //----------------------------------------------------------
594 class TSR : public GENERIC
595 {
596 public : TSR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
597 };
598
599 //----------------------------------------------------------
600 // [0][32] EPCR
601 //----------------------------------------------------------
602 class EPCR : public GENERIC
603 {
604 public : EPCR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
605 };
606
607 //----------------------------------------------------------
608 // [0][48] EEAR
609 //----------------------------------------------------------
610 class EEAR : public GENERIC
611 {
612 public : EEAR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
613 };
614
615 //----------------------------------------------------------
616 // [0][64] ESR
617 //----------------------------------------------------------
618 class ESR : public GENERIC
619 {
620 public : ESR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
621 };
622
623 //----------------------------------------------------------
624 // [0][1024] GPR
625 //----------------------------------------------------------
626 class GPR : public GENERIC
627 {
628 public : GPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
629 };
630
631 //----------------------------------------------------------
632 // [3][0] DCCR
633 //----------------------------------------------------------
634 class DCCR : public morpheo::behavioural::SPR
635 {
636 public : const Tspr_t _res : 24;
637 public : Tspr_t ew : 8;
638
639 public : DCCR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL):
640 _res (0),
641 ew (0)
642 {};
643 public : void reset (void ) {};
644 public : Tspr_t read (void )
645 {
646 return ((ew << 0));
647 };
648 public : void write (Tspr_t x)
649 {
650 ew = (x >> 0);
651 };
652 };
653
654 //----------------------------------------------------------
655 // [3][1] DCBPR
656 //----------------------------------------------------------
657 class DCBPR : public GENERIC
658 {
659 public : DCBPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
660 };
661
662 //----------------------------------------------------------
663 // [3][2] DCBFR
664 //----------------------------------------------------------
665 class DCBFR : public GENERIC
666 {
667 public : DCBFR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
668 };
669
670 //----------------------------------------------------------
671 // [3][3] DCBIR
672 //----------------------------------------------------------
673 class DCBIR : public GENERIC
674 {
675 public : DCBIR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
676 };
677
678 //----------------------------------------------------------
679 // [3][4] DCBWR
680 //----------------------------------------------------------
681 class DCBWR : public GENERIC
682 {
683 public : DCBWR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
684 };
685
686 //----------------------------------------------------------
687 // [3][5] DCBLR
688 //----------------------------------------------------------
689 class DCBLR : public GENERIC
690 {
691 public : DCBLR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {};
692 };
693
694// //----------------------------------------------------------
695// // [0][1] UPR
696// //----------------------------------------------------------
697// class UPR : public morpheo::behavioural::SPR
698// {
699// public : UPR (void): {};
700// public : void reset (void ) {};
701// public : Tspr_t read (void )
702// {
703// return ();
704// };
705// public : void write (Tspr_t x) {};
706// };
707
708
709}; // end namespace special_register_unit
710}; // end namespace ooo_engine
711}; // end namespace multi_ooo_engine
712}; // end namespace core
713
714}; // end namespace behavioural
715}; // end namespace morpheo
716
717#endif
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