1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h" |
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10 | |
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11 | #ifdef VHDL_TESTBENCH |
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12 | # define VHDL_SET_PORT(name,direction,size) vhdl.set_port (name,direction,size); _vhdl_testbench->set_port (name,direction,size); |
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13 | #else |
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14 | # define VHDL_SET_PORT(name,direction,size) vhdl.set_port (name,direction,size); |
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15 | #endif |
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16 | |
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17 | namespace morpheo { |
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18 | namespace behavioural { |
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19 | namespace generic { |
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20 | namespace registerfile{ |
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21 | namespace registerfile_multi_banked { |
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22 | namespace registerfile_multi_banked_glue { |
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23 | |
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24 | |
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25 | void RegisterFile_Multi_Banked_Glue::vhdl_port (Vhdl & vhdl) |
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26 | { |
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27 | log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_port","Begin"); |
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28 | |
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29 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_IN"); |
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30 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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31 | { |
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32 | VHDL_SET_PORT(" in_READ_IN_VAL_"+toString(i)+" ", IN, 1); |
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33 | VHDL_SET_PORT("out_READ_IN_ACK_"+toString(i)+" ",OUT, 1); |
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34 | VHDL_SET_PORT(" in_READ_IN_ADDRESS_"+toString(i)+" ", IN, _param._size_address); |
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35 | VHDL_SET_PORT("out_READ_IN_DATA_"+toString(i)+" ",OUT, _param._size_word ); |
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36 | } |
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37 | |
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38 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_SELECT"); |
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39 | |
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40 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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41 | { |
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42 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d]",i); |
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43 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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44 | { |
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45 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d][%d]",i,j); |
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46 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++) |
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47 | { |
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48 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d][%d][%d]",i,j,k); |
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49 | VHDL_SET_PORT("out_READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ",OUT, 1); |
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50 | VHDL_SET_PORT(" in_READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ", IN, 1); |
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51 | } |
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52 | } |
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53 | } |
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54 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_OUT"); |
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55 | |
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56 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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57 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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58 | { |
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59 | VHDL_SET_PORT("out_READ_OUT_VAL_"+toString(i)+"_"+toString(j)+" ",OUT, 1); |
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60 | VHDL_SET_PORT(" in_READ_OUT_ACK_"+toString(i)+"_"+toString(j)+" ", IN, 1); |
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61 | VHDL_SET_PORT("out_READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ",OUT, _param._size_address); |
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62 | VHDL_SET_PORT(" in_READ_OUT_DATA_"+toString(i)+"_"+toString(j)+" ", IN, _param._size_word ); |
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63 | } |
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64 | |
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65 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_IN"); |
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66 | |
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67 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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68 | { |
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69 | VHDL_SET_PORT(" in_WRITE_IN_VAL_"+toString(i)+" ", IN, 1); |
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70 | VHDL_SET_PORT("out_WRITE_IN_ACK_"+toString(i)+" ",OUT, 1); |
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71 | VHDL_SET_PORT(" in_WRITE_IN_ADDRESS_"+toString(i)+" ", IN, _param._size_address); |
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72 | VHDL_SET_PORT(" in_WRITE_IN_DATA_"+toString(i)+" ", IN, _param._size_word ); |
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73 | } |
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74 | |
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75 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_SELECT"); |
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76 | |
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77 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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78 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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79 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++) |
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80 | { |
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81 | VHDL_SET_PORT("out_WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ",OUT, 1); |
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82 | VHDL_SET_PORT(" in_WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ", IN, 1); |
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83 | } |
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84 | |
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85 | log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_OUT"); |
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86 | |
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87 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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88 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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89 | { |
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90 | VHDL_SET_PORT("out_WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+" ",OUT, 1); |
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91 | VHDL_SET_PORT(" in_WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+" ", IN, 1); |
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92 | VHDL_SET_PORT("out_WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ",OUT, _param._size_address); |
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93 | VHDL_SET_PORT("out_WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+" ",OUT, _param._size_word ); |
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94 | } |
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95 | |
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96 | log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_port","End"); |
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97 | }; |
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98 | |
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99 | }; // end namespace registerfile_multi_banked_glue |
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100 | }; // end namespace registerfile_multi_banked |
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101 | }; // end namespace registerfile |
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102 | }; // end namespace generic |
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103 | |
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104 | }; // end namespace behavioural |
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105 | }; // end namespace morpheo |
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106 | #endif |
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