Changeset 15 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/RegisterFile_Multi_Banked_Glue_vhdl_port.cpp

Timestamp:

Apr 5, 2007, 4:17:30 PM (17 years ago)

Author:

rosiere

Message:

Interface normalisé
Début du banc de registres multi niveaux

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/RegisterFile_Multi_Banked_Glue_vhdl_port.cpp (modified) (6 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/src/RegisterFile_Multi_Banked_Glue_vhdl_port.cpp

@@ -7 +7 @@
  */
 
-#include "Behavioural/Generic/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h"
+#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h"
 
 #ifdef VHDL_TESTBENCH
@@ -18 +18 @@
 namespace behavioural {
 namespace generic {
+namespace registerfile{
 namespace registerfile_multi_banked {
 namespace registerfile_multi_banked_glue {
@@ -26 +27 @@
     log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_port","Begin");
 
+    log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_IN");
    for (uint32_t i=0; i<_param._nb_port_read; i++)
      {
@@ -32 +34 @@
        VHDL_SET_PORT(" in_READ_IN_ADDRESS_"+toString(i)+"  ", IN, _param._size_address);
        VHDL_SET_PORT("out_READ_IN_DATA_"+toString(i)+"     ",OUT, _param._size_word   );
-       VHDL_SET_PORT(" in_READ_SELECT_VAL_"+toString(i)+"  ", IN, 1);
-       VHDL_SET_PORT("out_READ_SELECT_ACK_"+toString(i)+"  ",OUT, 1);
      }
-                                                      
+
+   log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_SELECT");
+        
+   for (uint32_t i=0; i<_param._nb_bank; i++)
+     {
+       log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d]",i);
+       for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
+         {
+           log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d][%d]",i,j);
+           for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++)
+             {
+               log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","READ_SELECT[%d][%d][%d]",i,j,k);
+               VHDL_SET_PORT("out_READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ",OUT, 1);
+               VHDL_SET_PORT(" in_READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ", IN, 1);
+             }
+         }
+     }
+   log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface READ_OUT");
+    
     for (uint32_t i=0; i<_param._nb_bank; i++)
-      {
-        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
-          {
-            VHDL_SET_PORT("out_READ_OUT_VAL_"+toString(i)+"_"+toString(j)+"      ",OUT, 1);
-            VHDL_SET_PORT(" in_READ_OUT_ACK_"+toString(i)+"_"+toString(j)+"      ", IN, 1);
-            VHDL_SET_PORT("out_READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+"  ",OUT, _param._size_address);
-            VHDL_SET_PORT(" in_READ_OUT_DATA_"+toString(i)+"_"+toString(j)+"     ", IN, _param._size_word   );
-          }
-      }
+      for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
+        {
+          VHDL_SET_PORT("out_READ_OUT_VAL_"+toString(i)+"_"+toString(j)+"      ",OUT, 1);
+          VHDL_SET_PORT(" in_READ_OUT_ACK_"+toString(i)+"_"+toString(j)+"      ", IN, 1);
+          VHDL_SET_PORT("out_READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+"  ",OUT, _param._size_address);
+          VHDL_SET_PORT(" in_READ_OUT_DATA_"+toString(i)+"_"+toString(j)+"     ", IN, _param._size_word   );
+        }
 
+    log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_IN");
+    
    for (uint32_t i=0; i<_param._nb_port_write; i++)
      {
@@ -53 +71 @@
        VHDL_SET_PORT(" in_WRITE_IN_ADDRESS_"+toString(i)+" ", IN, _param._size_address);
        VHDL_SET_PORT(" in_WRITE_IN_DATA_"+toString(i)+"    ", IN, _param._size_word   );
-       VHDL_SET_PORT(" in_WRITE_SELECT_VAL_"+toString(i)+" ", IN, 1);
-       VHDL_SET_PORT("out_WRITE_SELECT_ACK_"+toString(i)+" ",OUT, 1);
      }
    
-    for (uint32_t i=0; i<_param._nb_bank; i++)
-      {
-        for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
-          {
-            VHDL_SET_PORT("out_WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+"     ",OUT, 1);
-            VHDL_SET_PORT(" in_WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+"     ", IN, 1);
-            VHDL_SET_PORT("out_WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ",OUT, _param._size_address);
-            VHDL_SET_PORT("out_WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+"    ",OUT, _param._size_word   );
-          }
-      }
+   log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_SELECT");
+
+   for (uint32_t i=0; i<_param._nb_bank; i++)
+     for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
+       for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++)
+         {
+           VHDL_SET_PORT("out_WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ",OUT, 1);
+           VHDL_SET_PORT(" in_WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ", IN, 1);
+         }
+   
+   log_printf(TRACE,RegisterFile_Multi_Banked_Glue,"vhdl_port","Interface WRITE_OUT");
+    
+   for (uint32_t i=0; i<_param._nb_bank; i++)
+     for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
+       {
+         VHDL_SET_PORT("out_WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+"     ",OUT, 1);
+         VHDL_SET_PORT(" in_WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+"     ", IN, 1);
+         VHDL_SET_PORT("out_WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ",OUT, _param._size_address);
+         VHDL_SET_PORT("out_WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+"    ",OUT, _param._size_word   );
+       }
 
     log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_port","End");
@@ -73 +99 @@
 }; // end namespace registerfile_multi_banked_glue
 }; // end namespace registerfile_multi_banked
+}; // end namespace registerfile
 }; // end namespace generic