1 | #ifdef VHDL_TESTBENCH |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/include/RegisterFile_Multi_Banked_Glue.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace generic { |
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14 | namespace registerfile{ |
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15 | namespace registerfile_multi_banked { |
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16 | namespace registerfile_multi_banked_glue { |
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17 | |
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18 | |
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19 | void RegisterFile_Multi_Banked_Glue::vhdl_testbench_transition () |
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20 | { |
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21 | log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_testbench_transition","Begin"); |
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22 | |
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23 | // Evaluation before read the ouput signal |
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24 | sc_start(0); |
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25 | |
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26 | // In order with file RegisterFile_Multi_Banked_Glue_vhdl_testbench_port.cpp |
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27 | // Warning : if a output depend of a subcomponent, take directly the port of subcomponent |
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28 | // (because we have no control on the ordonnancer's policy) |
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29 | |
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30 | //_vhdl_testbench->add_input (PORT_READ( in_NRESET)); |
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31 | |
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32 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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33 | { |
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34 | _vhdl_testbench->add_input (PORT_READ( in_READ_IN_VAL [i])); |
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35 | _vhdl_testbench->add_output(PORT_READ(out_READ_IN_ACK [i])); |
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36 | _vhdl_testbench->add_input (PORT_READ( in_READ_IN_ADDRESS [i])); |
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37 | _vhdl_testbench->add_input (PORT_READ(out_READ_IN_DATA [i])); |
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38 | } |
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39 | |
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40 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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41 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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42 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++) |
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43 | { |
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44 | _vhdl_testbench->add_output(PORT_READ(out_READ_SELECT_VAL [i][j][k])); |
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45 | _vhdl_testbench->add_input (PORT_READ( in_READ_SELECT_ACK [i][j][k])); |
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46 | } |
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47 | |
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48 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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49 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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50 | { |
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51 | _vhdl_testbench->add_output(PORT_READ(out_READ_OUT_VAL [i][j])); |
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52 | _vhdl_testbench->add_input (PORT_READ( in_READ_OUT_ACK [i][j])); |
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53 | _vhdl_testbench->add_output(PORT_READ(out_READ_OUT_ADDRESS [i][j])); |
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54 | _vhdl_testbench->add_input (PORT_READ( in_READ_OUT_DATA [i][j])); |
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55 | } |
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56 | |
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57 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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58 | { |
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59 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_IN_VAL [i])); |
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60 | _vhdl_testbench->add_output(PORT_READ(out_WRITE_IN_ACK [i])); |
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61 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_IN_ADDRESS [i])); |
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62 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_IN_DATA [i])); |
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63 | } |
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64 | |
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65 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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66 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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67 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++) |
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68 | { |
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69 | _vhdl_testbench->add_output(PORT_READ(out_WRITE_SELECT_VAL [i][j][k])); |
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70 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_SELECT_ACK [i][j][k])); |
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71 | } |
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72 | |
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73 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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74 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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75 | { |
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76 | _vhdl_testbench->add_output(PORT_READ(out_WRITE_OUT_VAL [i][j])); |
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77 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_OUT_ACK [i][j])); |
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78 | _vhdl_testbench->add_output(PORT_READ(out_WRITE_OUT_ADDRESS [i][j])); |
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79 | _vhdl_testbench->add_output(PORT_READ(out_WRITE_OUT_DATA [i][j])); |
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80 | } |
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81 | |
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82 | |
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83 | // add_test : |
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84 | // - True : the cycle must be compare with the output of systemC |
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85 | // - False : no test |
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86 | _vhdl_testbench->add_test(true); |
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87 | |
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88 | _vhdl_testbench->new_cycle (); // always at the end |
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89 | |
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90 | log_printf(FUNC,RegisterFile_Multi_Banked_Glue,"vhdl_testbench_transition","End"); |
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91 | }; |
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92 | |
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93 | }; // end namespace registerfile_multi_banked_glue |
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94 | }; // end namespace registerfile_multi_banked |
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95 | }; // end namespace registerfile |
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96 | }; // end namespace generic |
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97 | |
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98 | }; // end namespace behavioural |
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99 | }; // end namespace morpheo |
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100 | #endif |
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