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Last change
on this file since 39 was
38,
checked in by rosiere, 17 years ago
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Interface et vhdl_testbench : l'appel aux fonction add_input et add_ouput est maintenant réalisé par la classe Interface (et autre).
2 remarques :
- tester avec des sous composants (en particulier les sorties d'un est directement relié au sortie d'un autre)
- Signal_testbench.cpp -> l'optimisé (par exemple pointeur de fonction afin d'éviter le test et le switch)
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File size:
1.1 KB
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| Line | |
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| 1 | # |
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| 2 | # $Id$ |
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| 3 | # |
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| 4 | # [ Description ] |
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| 5 | # |
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| 6 | |
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| 7 | #-----[ Simulator ]---------------------------------------- |
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| 8 | SIMULATOR = systemcass_deps |
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| 9 | |
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| 10 | # 3 simulators : |
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| 11 | # systemc - SystemC |
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| 12 | # systemcass - SystemCASS |
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| 13 | # systemcass_deps - SystemCASS, and use port dependency information instead of sensitivity list |
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| 14 | |
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| 15 | #-----[ Flags ]-------------------------------------------- |
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| 16 | FLAGS = -DSYSTEMC \ |
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| 17 | -DVHDL \ |
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| 18 | -DVHDL_TESTBENCH \ |
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| 19 | -DSTATISTICS \ |
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| 20 | -DPOSITION \ |
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| 21 | -DCONFIGURATION \ |
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| 22 | -DDEBUG=DEBUG_ALL |
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| 23 | |
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| 24 | |
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| 25 | # Flags : |
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| 26 | # DEBUG={level} - Print Debug Message |
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| 27 | # SYSTEMC - To generate a systemc's model |
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| 28 | # VHDL - To generate a vhdl's models |
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| 29 | # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model |
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| 30 | # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file |
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| 31 | # POSITION - To generate a position's files (it's input of viewer) |
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| 32 | # CONFIGURATION - To generate a configuration's file (it's input of viewer and generator) |
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