1 | #ifndef morpheo_behavioural_Constants_h |
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2 | #define morpheo_behavioural_Constants_h |
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3 | |
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4 | /* |
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5 | WARNING : |
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6 | |
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7 | I Use reserved exception : |
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8 | |
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9 | 0x10 - EXCEPTION_MEMORY_MISS_SPECULATION - Load miss speculation |
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10 | 0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE - The load is speculative : write in register file, but don't commit |
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11 | 0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID - SPR present in ALU but not compatible privilege |
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12 | 0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ - SPR not present in ALU |
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13 | 0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU |
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14 | |
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15 | I Use reserved SPR : |
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16 | [0][19] - SPR_CID |
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17 | */ |
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18 | |
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19 | namespace morpheo { |
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20 | namespace behavioural { |
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21 | |
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22 | # define SET_FLAG( x,pos) {(x) |= (1<<(pos));} while (0) |
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23 | # define UNSET_FLAG( x,pos) {(x) &= ~(1<<(pos));} while (0) |
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24 | # define IS_SET_FLAG( x,pos) (((x) & (1<<(pos))) != 0) |
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25 | # define IS_UNSET_FLAG(x,pos) (((x) & (1<<(pos))) == 0) |
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26 | # define CHANGE_FLAG( x,pos,f) \ |
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27 | { \ |
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28 | if (f) \ |
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29 | {SET_FLAG(x,pos);} \ |
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30 | else \ |
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31 | {UNSET_FLAG(x,pos);} \ |
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32 | } while (0) |
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33 | |
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34 | //=========================================================[ Type ]===== |
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35 | # define TYPE_ALU 0x0 // 00000 - unit multiple |
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36 | # define TYPE_SHIFT 0x1 // 00000 - unit multiple |
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37 | # define TYPE_MOVE 0x2 // 00000 - unit multiple |
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38 | # define TYPE_TEST 0x3 // 00000 - unit multiple |
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39 | # define TYPE_MUL 0x4 // 00000 - unit multiple |
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40 | # define TYPE_DIV 0x5 // 00000 - unit multiple, type optionnal |
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41 | # define TYPE_EXTEND 0x6 // 00000 - unit multiple, type optionnal |
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42 | # define TYPE_FIND 0x7 // 00000 - unit multiple, type optionnal |
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43 | # define TYPE_SPECIAL 0x8 // 00000 - unit uniq |
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44 | # define TYPE_CUSTOM 0x9 // 00000 - unit uniq , type optionnal |
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45 | # define TYPE_BRANCH 0xa // 00000 - unit multiple |
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46 | # define TYPE_MEMORY 0xb // 00000 - unit uniq |
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47 | |
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48 | //#define NB_TYPE 11 |
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49 | # define SIZE_TYPE 5 |
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50 | # define MAX_TYPE (1<<SIZE_TYPE) |
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51 | |
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52 | # define is_type_valid(x) \ |
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53 | (( x == TYPE_ALU ) or \ |
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54 | ( x == TYPE_SHIFT ) or \ |
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55 | ( x == TYPE_MOVE ) or \ |
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56 | ( x == TYPE_TEST ) or \ |
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57 | ( x == TYPE_MUL ) or \ |
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58 | ( x == TYPE_DIV ) or \ |
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59 | ( x == TYPE_EXTEND ) or \ |
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60 | ( x == TYPE_FIND ) or \ |
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61 | ( x == TYPE_SPECIAL) or \ |
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62 | ( x == TYPE_CUSTOM ) or \ |
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63 | ( x == TYPE_BRANCH ) or \ |
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64 | ( x == TYPE_MEMORY )) |
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65 | |
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66 | //====================================================[ Operation ]===== |
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67 | |
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68 | //-------------------------------------------------------[ Memory ]----- |
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69 | # define OPERATION_MEMORY_LOAD_8_Z 0x08 // 0_1000 |
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70 | # define OPERATION_MEMORY_LOAD_16_Z 0x09 // 0_1001 |
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71 | # define OPERATION_MEMORY_LOAD_32_Z 0x0a // 0_1010 |
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72 | # define OPERATION_MEMORY_LOAD_64_Z 0x0b // 0_1011 |
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73 | # define OPERATION_MEMORY_LOAD_8_S 0x18 // 1_1000 |
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74 | # define OPERATION_MEMORY_LOAD_16_S 0x19 // 1_1001 |
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75 | # define OPERATION_MEMORY_LOAD_32_S 0x1a // 1_1010 |
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76 | # define OPERATION_MEMORY_LOAD_64_S 0x1b // 1_1011 |
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77 | |
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78 | # define OPERATION_MEMORY_STORE_8 0x0c // 0_1100 |
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79 | # define OPERATION_MEMORY_STORE_16 0x0d // 0_1101 |
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80 | # define OPERATION_MEMORY_STORE_32 0x0e // 0_1110 |
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81 | # define OPERATION_MEMORY_STORE_64 0x0f // 0_1111 |
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82 | # define OPERATION_MEMORY_STORE_HEAD_OK 0x1c // 1_1100 |
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83 | # define OPERATION_MEMORY_STORE_HEAD_KO 0x1d // 1_1101 |
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84 | |
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85 | # define OPERATION_MEMORY_LOCK 0x01 // 0_0001 |
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86 | # define OPERATION_MEMORY_INVALIDATE 0x02 // 0_0010 |
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87 | # define OPERATION_MEMORY_PREFETCH 0x03 // 0_0011 |
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88 | # define OPERATION_MEMORY_FLUSH 0x06 // 0_0110 |
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89 | # define OPERATION_MEMORY_SYNCHRONIZATION 0x07 // 0_0111 |
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90 | |
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91 | #define is_operation_memory_load(x) \ |
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92 | ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ |
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93 | (x == OPERATION_MEMORY_LOAD_16_Z) or \ |
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94 | (x == OPERATION_MEMORY_LOAD_32_Z) or \ |
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95 | (x == OPERATION_MEMORY_LOAD_64_Z) or \ |
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96 | (x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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97 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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98 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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99 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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100 | |
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101 | #define is_operation_memory_store(x) \ |
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102 | ((x == OPERATION_MEMORY_STORE_8 ) or \ |
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103 | (x == OPERATION_MEMORY_STORE_16 ) or \ |
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104 | (x == OPERATION_MEMORY_STORE_32 ) or \ |
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105 | (x == OPERATION_MEMORY_STORE_64 ) or \ |
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106 | (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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107 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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108 | |
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109 | #define is_operation_memory_store_head(x) \ |
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110 | ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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111 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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112 | |
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113 | #define is_operation_memory_load_signed(x) \ |
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114 | ((x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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115 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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116 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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117 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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118 | |
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119 | # define MEMORY_ACCESS_8 0x0 |
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120 | # define MEMORY_ACCESS_16 0x1 |
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121 | # define MEMORY_ACCESS_32 0x2 |
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122 | # define MEMORY_ACCESS_64 0x3 |
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123 | |
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124 | # define MEMORY_SIZE_8 8 |
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125 | # define MEMORY_SIZE_16 16 |
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126 | # define MEMORY_SIZE_32 32 |
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127 | # define MEMORY_SIZE_64 64 |
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128 | |
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129 | # define MASK_MEMORY_ACCESS_8 0x0 |
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130 | # define MASK_MEMORY_ACCESS_16 0x1 |
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131 | # define MASK_MEMORY_ACCESS_32 0x3 |
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132 | # define MASK_MEMORY_ACCESS_64 0x7 |
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133 | |
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134 | #define memory_size(x) \ |
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135 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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136 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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137 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \ |
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138 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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139 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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140 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \ |
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141 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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142 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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143 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8))) |
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144 | |
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145 | #define memory_access(x) \ |
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146 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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147 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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148 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ |
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149 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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150 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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151 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ |
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152 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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153 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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154 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) |
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155 | |
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156 | #define mask_memory_access(x) \ |
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157 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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158 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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159 | (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ |
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160 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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161 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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162 | (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ |
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163 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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164 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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165 | (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) |
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166 | |
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167 | //---------------------------------------------[ Functionnal Unit ]----- |
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168 | # define OPERATION_ALU_L_ADD 0x1 // 000_0000 l.add , l.addi |
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169 | # define OPERATION_ALU_L_ADDC 0x2 // 000_0000 l.addc , l.addic |
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170 | # define OPERATION_ALU_L_SUB 0x4 // 000_0000 l.sub |
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171 | # define OPERATION_ALU_L_AND 0x8 // 000_0000 l.and , l.andi |
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172 | # define OPERATION_ALU_L_OR 0x10 // 000_0000 l.or , l.ori |
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173 | # define OPERATION_ALU_L_XOR 0x20 // 000_0000 l.xor , l.xori |
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174 | |
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175 | # define OPERATION_SHIFT_L_SLL 0x1 // 000_0000 l.sll , l.slli |
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176 | # define OPERATION_SHIFT_L_SRA 0x2 // 000_0000 l.sra , l.srai |
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177 | # define OPERATION_SHIFT_L_SRL 0x4 // 000_0000 l.srl , l.srli |
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178 | # define OPERATION_SHIFT_L_ROR 0x8 // 000_0000 l.ror , l.rori |
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179 | |
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180 | # define OPERATION_MOVE_L_MOVHI 0x1 // 000_0000 l.movhi |
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181 | # define OPERATION_MOVE_L_CMOV 0x2 // 000_0000 l.cmov |
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182 | |
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183 | # define OPERATION_TEST_L_SFGES 0x41 // 000_0000 l.sfges , l.sfges |
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184 | # define OPERATION_TEST_L_SFGEU 0x1 // 000_0000 l.sfgeu , l.sfgeu |
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185 | # define OPERATION_TEST_L_SFGTS 0x42 // 000_0000 L.sfgts , l.sfgts |
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186 | # define OPERATION_TEST_L_SFGTU 0x2 // 000_0000 l.sfgtu , l.sfgtu |
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187 | # define OPERATION_TEST_L_SFLES 0x44 // 000_0000 l.sfles , l.sfles |
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188 | # define OPERATION_TEST_L_SFLEU 0x4 // 000_0000 l.sfleu , l.sfleu |
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189 | # define OPERATION_TEST_L_SFLTS 0x48 // 000_0000 l.sflts , l.sflts |
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190 | # define OPERATION_TEST_L_SFLTU 0x8 // 000_0000 l.sfltu , l.sfltu |
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191 | # define OPERATION_TEST_L_SFEQ 0x10 // 000_0000 l.sfeq , l.sfeqi |
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192 | # define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei |
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193 | |
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194 | # define OPERATION_MUL_L_MUL 0x1 // 000_0000 l.mul , l.muli |
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195 | # define OPERATION_MUL_L_MULU 0x2 // 000_0000 l.mulu |
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196 | |
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197 | # define OPERATION_DIV_L_DIV 0x1 // 000_0000 l.div |
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198 | # define OPERATION_DIV_L_DIVU 0x2 // 000_0000 l.divu |
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199 | |
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200 | # define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz |
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201 | # define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0000 l.extbs , l.exths, l.extws |
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202 | |
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203 | # define OPERATION_FIND_L_FF1 0x1 // 000_0000 l.ff1 |
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204 | # define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1 |
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205 | |
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206 | # define OPERATION_SPECIAL_L_NOP 0xff // 000_0000 l.nop |
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207 | # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr |
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208 | # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr |
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209 | # define OPERATION_SPECIAL_L_RFE 0x4 // 000_0100 l.rfe |
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210 | # define OPERATION_SPECIAL_L_MAC 0x11 // 001_0001 l.mac , l.maci |
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211 | # define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc |
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212 | # define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb |
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213 | # define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync |
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214 | # define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync |
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215 | # define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync |
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216 | # define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys |
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217 | # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap |
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218 | |
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219 | |
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220 | # define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j |
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221 | # define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0000 l.bnf |
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222 | # define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0000 l.bf |
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223 | # define OPERATION_BRANCH_L_JALR 0x8 // 000_0000 l.jal , l.jalr , l.jr |
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224 | |
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225 | //-------------------------------------------------------[ Custom ]----- |
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226 | |
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227 | # define OPERATION_CUSTOM_L_1 0x40 // 100_0000 |
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228 | # define OPERATION_CUSTOM_L_2 0x41 // 100_0001 |
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229 | # define OPERATION_CUSTOM_L_3 0x42 // 100_0010 |
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230 | # define OPERATION_CUSTOM_L_4 0x43 // 100_0011 |
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231 | # define OPERATION_CUSTOM_L_5 0x44 // 100_0100 |
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232 | # define OPERATION_CUSTOM_L_6 0x45 // 100_0101 |
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233 | # define OPERATION_CUSTOM_L_7 0x46 // 100_0110 |
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234 | # define OPERATION_CUSTOM_L_8 0x47 // 100_0111 |
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235 | # define OPERATION_CUSTOM_LF_1_D 0x48 // 100_1000 |
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236 | # define OPERATION_CUSTOM_LF_1_S 0x49 // 100_1001 |
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237 | # define OPERATION_CUSTOM_LV_1 0x4c // 100_1100 |
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238 | # define OPERATION_CUSTOM_LV_2 0x4d // 100_1101 |
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239 | # define OPERATION_CUSTOM_LV_3 0x4e // 100_1110 |
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240 | # define OPERATION_CUSTOM_LV_4 0x4f // 100_1111 |
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241 | |
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242 | # define SIZE_OPERATION 7 |
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243 | # define MAX_OPERATION (1<<SIZE_OPERATION) |
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244 | |
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245 | //====================================================[ Exception ]===== |
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246 | // Exception - OpenRISC |
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247 | |
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248 | # define SIZE_EXCEPTION 5 |
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249 | # define SIZE_EXCEPTION_USE 4 |
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250 | # define SIZE_EXCEPTION_MEMORY 5 |
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251 | # define SIZE_EXCEPTION_CUSTOM 5 |
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252 | # define SIZE_EXCEPTION_ALU 5 |
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253 | # define SIZE_EXCEPTION_DECOD 5 |
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254 | # define SIZE_EXCEPTION_IFETCH 5 |
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255 | |
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256 | # define EXCEPTION_NONE 0x00 // none exception |
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257 | # define EXCEPTION_RESET 0x01 // software or hardware reset |
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258 | # define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress |
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259 | # define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
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260 | # define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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261 | # define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption |
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262 | # define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned |
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263 | # define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) |
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264 | # define EXCEPTION_INTERRUPT 0x08 // External interruption |
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265 | # define EXCEPTION_DATA_TLB 0x09 // DTLB miss |
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266 | # define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss |
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267 | # define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context |
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268 | # define EXCEPTION_SYSCALL 0x0c // System Call |
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269 | # define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction |
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270 | # define EXCEPTION_TRAP 0x0e // L.trap or debug unit |
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271 | # define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage |
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272 | # define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage |
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273 | # define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage |
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274 | # define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage |
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275 | # define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage |
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276 | # define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage |
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277 | # define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions |
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278 | # define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions |
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279 | # define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions |
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280 | # define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions |
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281 | # define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions |
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282 | # define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions |
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283 | # define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions |
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284 | # define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions |
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285 | # define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions |
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286 | # define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions |
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287 | # define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions |
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288 | |
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289 | //SR[14].EPH : Exception Prefix High |
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290 | // EPH = 0 Exceptions vectors are located in memory area starting at 0x0 |
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291 | // EPH = 1 Exception vectors are located in memory area starting at 0xF0000000 |
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292 | |
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293 | #define exception_to_address(eph,x) (((eph==0)?0x0:0xF0000000)+(x<<8)) |
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294 | |
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295 | // Exception Execution |
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296 | # define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception |
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297 | # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss |
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298 | # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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299 | # define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address |
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300 | |
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301 | # define EXCEPTION_DECOD_NONE 0x00 // none exception |
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302 | # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) |
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303 | # define EXCEPTION_DECOD_SYSCALL 0x02 // System Call |
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304 | //#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) |
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305 | # define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss |
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306 | # define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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307 | # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address |
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308 | |
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309 | # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception |
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310 | # define EXCEPTION_ALU_RANGE 0x0b // |
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311 | # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // SPR present in ALU but not compatible privilege |
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312 | # define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // SPR not present in ALU |
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313 | # define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // SPR not present in ALU |
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314 | |
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315 | # define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception |
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316 | # define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned |
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317 | # define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss |
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318 | # define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
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319 | # define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address |
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320 | # define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // Load miss speculation |
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321 | # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // The load is speculative : write in register file, but don't commit |
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322 | |
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323 | # define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception |
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324 | # define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions |
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325 | # define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions |
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326 | # define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions |
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327 | # define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions |
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328 | # define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions |
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329 | # define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions |
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330 | # define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions |
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331 | |
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332 | # define EXCEPTION_USE_NONE 0x00 // |
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333 | # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction |
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334 | # define EXCEPTION_USE_RANGE 0x02 // range |
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335 | # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment |
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336 | # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error |
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337 | # define EXCEPTION_USE_SYSCALL 0x05 // syscall |
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338 | # define EXCEPTION_USE_TRAP 0x06 // trap |
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339 | # define EXCEPTION_USE_CUSTOM_0 0x07 // |
---|
340 | # define EXCEPTION_USE_CUSTOM_1 0x08 // |
---|
341 | # define EXCEPTION_USE_CUSTOM_2 0x09 // |
---|
342 | # define EXCEPTION_USE_CUSTOM_3 0x0a // |
---|
343 | # define EXCEPTION_USE_CUSTOM_4 0x0b // |
---|
344 | # define EXCEPTION_USE_CUSTOM_5 0x0c // |
---|
345 | # define EXCEPTION_USE_CUSTOM_6 0x0d // |
---|
346 | |
---|
347 | # define exception_ifetch_to_exception_decod(x) x |
---|
348 | # define exception_decod_to_exception(x) x |
---|
349 | # define exception_alu_to_exception(x) x |
---|
350 | # define exception_memory_to_exception(x) x |
---|
351 | # define exception_custom_to_exception(x) x |
---|
352 | |
---|
353 | //=======================================================[ icache ]===== |
---|
354 | |
---|
355 | //--------------------------------------------------[ icache_type ]----- |
---|
356 | |
---|
357 | # define SIZE_ICACHE_TYPE 2 |
---|
358 | |
---|
359 | # define ICACHE_TYPE_LOAD 0x0 // 0000 |
---|
360 | # define ICACHE_TYPE_LOCK 0x1 // 0001 |
---|
361 | # define ICACHE_TYPE_INVALIDATE 0x2 // 0010 |
---|
362 | # define ICACHE_TYPE_PREFETCH 0x3 // 0011 |
---|
363 | |
---|
364 | // just take the 2 less significative bits. |
---|
365 | #define operation_to_icache_type(x) (x&0x3) |
---|
366 | |
---|
367 | //-------------------------------------------------[ icache_error ]----- |
---|
368 | |
---|
369 | # define SIZE_ICACHE_ERROR 1 |
---|
370 | |
---|
371 | # define ICACHE_ERROR_NONE 0x0 |
---|
372 | # define ICACHE_ERROR_BUS_ERROR 0x1 |
---|
373 | |
---|
374 | //=======================================================[ dcache ]===== |
---|
375 | |
---|
376 | //--------------------------------------------------[ dcache_type ]----- |
---|
377 | |
---|
378 | # define SIZE_DCACHE_TYPE 4 |
---|
379 | |
---|
380 | //#define DCACHE_TYPE_ 0x0 // 0000 |
---|
381 | # define DCACHE_TYPE_LOCK 0x1 // 0001 |
---|
382 | # define DCACHE_TYPE_INVALIDATE 0x2 // 0010 |
---|
383 | # define DCACHE_TYPE_PREFETCH 0x3 // 0011 |
---|
384 | //#define DCACHE_TYPE_ 0x4 // 0100 |
---|
385 | //#define DCACHE_TYPE_ 0x5 // 0101 |
---|
386 | # define DCACHE_TYPE_FLUSH 0x6 // 0110 |
---|
387 | # define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111 |
---|
388 | # define DCACHE_TYPE_LOAD_8 0x8 // 1000 |
---|
389 | # define DCACHE_TYPE_LOAD_16 0x9 // 1001 |
---|
390 | # define DCACHE_TYPE_LOAD_32 0xa // 1010 |
---|
391 | # define DCACHE_TYPE_LOAD_64 0xb // 1011 |
---|
392 | # define DCACHE_TYPE_STORE_8 0xc // 1100 |
---|
393 | # define DCACHE_TYPE_STORE_16 0xd // 1101 |
---|
394 | # define DCACHE_TYPE_STORE_32 0xe // 1110 |
---|
395 | # define DCACHE_TYPE_STORE_64 0xf // 1111 |
---|
396 | |
---|
397 | // just take the 4 less significative bits. |
---|
398 | #define operation_to_dcache_type(x) (x&0xf) |
---|
399 | |
---|
400 | //-------------------------------------------------[ dcache_error ]----- |
---|
401 | |
---|
402 | # define SIZE_DCACHE_ERROR 1 |
---|
403 | |
---|
404 | # define DCACHE_ERROR_NONE 0x0 |
---|
405 | # define DCACHE_ERROR_BUS_ERROR 0x1 |
---|
406 | |
---|
407 | //=================================================[ special_data ]===== |
---|
408 | |
---|
409 | # define SIZE_SPECIAL_DATA 2 |
---|
410 | |
---|
411 | // Position of flag in "rename register SR" (NOT IN "SR") |
---|
412 | # define FLAG_POSITION_F 0x0 // Conditionnal branch flag |
---|
413 | # define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation |
---|
414 | # define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation |
---|
415 | |
---|
416 | # define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag |
---|
417 | # define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation |
---|
418 | # define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation |
---|
419 | |
---|
420 | //==========================================================[ spr ]===== |
---|
421 | |
---|
422 | enum |
---|
423 | { |
---|
424 | GROUP_SYSTEM_AND_CONTROL, // 0 |
---|
425 | GROUP_DMMU, // 1 |
---|
426 | GROUP_IMMU, // 2 |
---|
427 | GROUP_DCACHE, // 3 |
---|
428 | GROUP_ICACHE, // 4 |
---|
429 | GROUP_MAC, // 5 |
---|
430 | GROUP_DEBUG, // 6 |
---|
431 | GROUP_PERFORMANCE_COUNTER, // 7 |
---|
432 | GROUP_POWER_MANAGEMENT, // 8 |
---|
433 | GROUP_PIC, // 9 |
---|
434 | GROUP_TICK_TIMER, // 10 |
---|
435 | GROUP_FLOATING_POINT, // 11 |
---|
436 | GROUP_RESERVED_1, // 12 |
---|
437 | GROUP_RESERVED_2, // 13 |
---|
438 | GROUP_RESERVED_3, // 14 |
---|
439 | GROUP_RESERVED_4, // 15 |
---|
440 | GROUP_RESERVED_5, // 16 |
---|
441 | GROUP_RESERVED_6, // 17 |
---|
442 | GROUP_RESERVED_7, // 18 |
---|
443 | GROUP_RESERVED_8, // 19 |
---|
444 | GROUP_RESERVED_9, // 20 |
---|
445 | GROUP_RESERVED_10, // 21 |
---|
446 | GROUP_RESERVED_11, // 22 |
---|
447 | GROUP_RESERVED_12, // 23 |
---|
448 | GROUP_CUSTOM_1, // 24 |
---|
449 | GROUP_CUSTOM_2, // 25 |
---|
450 | GROUP_CUSTOM_3, // 26 |
---|
451 | GROUP_CUSTOM_4, // 27 |
---|
452 | GROUP_CUSTOM_5, // 28 |
---|
453 | GROUP_CUSTOM_6, // 29 |
---|
454 | GROUP_CUSTOM_7, // 30 |
---|
455 | GROUP_CUSTOM_8, // 31 |
---|
456 | NB_GROUP |
---|
457 | }; |
---|
458 | |
---|
459 | # define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536 |
---|
460 | # define NB_REG_GROUP_DMMU 1536 |
---|
461 | # define NB_REG_GROUP_IMMU 1536 |
---|
462 | # define NB_REG_GROUP_DCACHE 6 |
---|
463 | # define NB_REG_GROUP_ICACHE 4 |
---|
464 | # define NB_REG_GROUP_MAC 3 |
---|
465 | # define NB_REG_GROUP_DEBUG 22 |
---|
466 | # define NB_REG_GROUP_PERFORMANCE_COUNTER 16 |
---|
467 | # define NB_REG_GROUP_POWER_MANAGEMENT 1 |
---|
468 | # define NB_REG_GROUP_PIC 3 |
---|
469 | # define NB_REG_GROUP_TICK_TIMER 2 |
---|
470 | # define NB_REG_GROUP_FLOATING_POINT 0 |
---|
471 | # define NB_REG_GROUP_RESERVED_1 0 |
---|
472 | # define NB_REG_GROUP_RESERVED_2 0 |
---|
473 | # define NB_REG_GROUP_RESERVED_3 0 |
---|
474 | # define NB_REG_GROUP_RESERVED_4 0 |
---|
475 | # define NB_REG_GROUP_RESERVED_5 0 |
---|
476 | # define NB_REG_GROUP_RESERVED_6 0 |
---|
477 | # define NB_REG_GROUP_RESERVED_7 0 |
---|
478 | # define NB_REG_GROUP_RESERVED_8 0 |
---|
479 | # define NB_REG_GROUP_RESERVED_9 0 |
---|
480 | # define NB_REG_GROUP_RESERVED_10 0 |
---|
481 | # define NB_REG_GROUP_RESERVED_11 0 |
---|
482 | # define NB_REG_GROUP_RESERVED_12 0 |
---|
483 | # define NB_REG_GROUP_CUSTOM_1 0 |
---|
484 | # define NB_REG_GROUP_CUSTOM_2 0 |
---|
485 | # define NB_REG_GROUP_CUSTOM_3 0 |
---|
486 | # define NB_REG_GROUP_CUSTOM_4 0 |
---|
487 | # define NB_REG_GROUP_CUSTOM_5 0 |
---|
488 | # define NB_REG_GROUP_CUSTOM_6 0 |
---|
489 | # define NB_REG_GROUP_CUSTOM_7 0 |
---|
490 | # define NB_REG_GROUP_CUSTOM_8 0 |
---|
491 | |
---|
492 | static const uint32_t NB_REG_GROUP [] = |
---|
493 | {NB_REG_GROUP_SYSTEM_AND_CONTROL , |
---|
494 | NB_REG_GROUP_DMMU , |
---|
495 | NB_REG_GROUP_IMMU , |
---|
496 | NB_REG_GROUP_DCACHE , |
---|
497 | NB_REG_GROUP_ICACHE , |
---|
498 | NB_REG_GROUP_MAC , |
---|
499 | NB_REG_GROUP_DEBUG , |
---|
500 | NB_REG_GROUP_PERFORMANCE_COUNTER , |
---|
501 | NB_REG_GROUP_POWER_MANAGEMENT , |
---|
502 | NB_REG_GROUP_PIC , |
---|
503 | NB_REG_GROUP_TICK_TIMER , |
---|
504 | NB_REG_GROUP_FLOATING_POINT , |
---|
505 | NB_REG_GROUP_RESERVED_1 , |
---|
506 | NB_REG_GROUP_RESERVED_2 , |
---|
507 | NB_REG_GROUP_RESERVED_3 , |
---|
508 | NB_REG_GROUP_RESERVED_4 , |
---|
509 | NB_REG_GROUP_RESERVED_5 , |
---|
510 | NB_REG_GROUP_RESERVED_6 , |
---|
511 | NB_REG_GROUP_RESERVED_7 , |
---|
512 | NB_REG_GROUP_RESERVED_8 , |
---|
513 | NB_REG_GROUP_RESERVED_9 , |
---|
514 | NB_REG_GROUP_RESERVED_10 , |
---|
515 | NB_REG_GROUP_RESERVED_11 , |
---|
516 | NB_REG_GROUP_RESERVED_12 , |
---|
517 | NB_REG_GROUP_CUSTOM_1 , |
---|
518 | NB_REG_GROUP_CUSTOM_2 , |
---|
519 | NB_REG_GROUP_CUSTOM_3 , |
---|
520 | NB_REG_GROUP_CUSTOM_4 , |
---|
521 | NB_REG_GROUP_CUSTOM_5 , |
---|
522 | NB_REG_GROUP_CUSTOM_6 , |
---|
523 | NB_REG_GROUP_CUSTOM_7 , |
---|
524 | NB_REG_GROUP_CUSTOM_8 }; |
---|
525 | |
---|
526 | // GROUP_SYSTEM_AND_CONTROL |
---|
527 | # define SPR_VR 0 // Version register |
---|
528 | # define SPR_UPR 1 // Unit Present register |
---|
529 | # define SPR_CPUCFGR 2 // CPU Configuration register |
---|
530 | # define SPR_DMMUCFGR 3 // Data MMU Configuration register |
---|
531 | # define SPR_IMMUCFGR 4 // Instruction MMU Configuration register |
---|
532 | # define SPR_DCCFGR 5 // Data Cache Configuration register |
---|
533 | # define SPR_ICCFGR 6 // Instruction Cache Configuration register |
---|
534 | # define SPR_DCFGR 7 // Debug Configuration register |
---|
535 | # define SPR_PCCFGR 8 // Performance Counters Configuration register |
---|
536 | # define SPR_NPC 16 // PC mapped to SPR space (next PC) |
---|
537 | # define SPR_SR 17 // Supervision register |
---|
538 | # define SPR_PPC 18 // PC mapped to SPR space (previous PC) |
---|
539 | # define SPR_CID 19 // Context Id |
---|
540 | # define SPR_FPCSR 20 // FP Control Status register |
---|
541 | # define SPR_EPCR 32 // Exception PC register |
---|
542 | # define SPR_EEAR 48 // Exception EA register |
---|
543 | # define SPR_ESR 64 // Exception SR register |
---|
544 | # define SPR_GPR 1024 // GPRs mappted to SPR space |
---|
545 | |
---|
546 | // GROUP_DCACHE |
---|
547 | # define SPR_DCCR 0 // DC Control register |
---|
548 | # define SPR_DCBPR 1 // DC Block Prefetch register |
---|
549 | # define SPR_DCBFR 2 // DC Block Flush register |
---|
550 | # define SPR_DCBIR 3 // DC Block Invalidate register |
---|
551 | # define SPR_DCBWR 4 // DC Block Write-back register |
---|
552 | # define SPR_DCBLR 5 // DC Block Lock register |
---|
553 | |
---|
554 | // GROUP_ICACHE |
---|
555 | # define SPR_ICCR 0 // IC Control register |
---|
556 | # define SPR_ICBPR 1 // IC Block Prefetch register |
---|
557 | # define SPR_ICBIR 2 // IC Block Invalidate register |
---|
558 | # define SPR_ICBLR 3 // IC Block Lock register |
---|
559 | |
---|
560 | // GROUP_MAC |
---|
561 | # define SPR_MACLO 1 // MAC Low |
---|
562 | # define SPR_MACHI 2 // MAC High |
---|
563 | |
---|
564 | |
---|
565 | |
---|
566 | // SR RENAME |
---|
567 | # define NB_SPR_LOGIC 2 |
---|
568 | # define LOG2_NB_SPR_LOGIC 1 |
---|
569 | // SPR_LOGIC[0] = F |
---|
570 | // SPR_LOGIC[1] = Carry, Overflow |
---|
571 | # define SPR_LOGIC_SR_F 0x0 // Status register bit F (size = 1) |
---|
572 | # define SPR_LOGIC_SR_CY_OV 0x1 // Status register bit overflow and carry (size = 2) |
---|
573 | |
---|
574 | //----------------------------------------------[ spr_mode_access ]----- |
---|
575 | |
---|
576 | # define SPR_ACCESS_MODE_NONE 0x0 // 000 |
---|
577 | # define SPR_ACCESS_MODE_READ_ONLY 0x1 // 001 |
---|
578 | # define SPR_ACCESS_MODE_WRITE_ONLY 0x2 // 010 |
---|
579 | # define SPR_ACCESS_MODE_READ_WRITE 0x3 // 011 |
---|
580 | # define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read |
---|
581 | |
---|
582 | //--------------------------------------------------------[ event ]----- |
---|
583 | # define SIZE_EVENT_STATE 2 |
---|
584 | |
---|
585 | # define EVENT_STATE_NO_EVENT 0 // no event : current case |
---|
586 | # define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event |
---|
587 | # define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) |
---|
588 | # define EVENT_STATE_END 3 // CPU can continue |
---|
589 | |
---|
590 | # define SIZE_EVENT_TYPE 3 |
---|
591 | |
---|
592 | # define EVENT_TYPE_NONE 0 // no event |
---|
593 | # define EVENT_TYPE_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) |
---|
594 | # define EVENT_TYPE_EXCEPTION 2 // exception or interruption occure |
---|
595 | # define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss) |
---|
596 | # define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction |
---|
597 | # define EVENT_TYPE_MSYNC 5 // decod a memory synchronization |
---|
598 | # define EVENT_TYPE_PSYNC 6 // decod a pipeline synchronization |
---|
599 | # define EVENT_TYPE_CSYNC 7 // decod a context synchronization |
---|
600 | |
---|
601 | //-------------------------------------------------[ branch_state ]----- |
---|
602 | # define SIZE_BRANCH_STATE 2 |
---|
603 | |
---|
604 | # define BRANCH_STATE_NONE 0x0 // 0 0 |
---|
605 | # define BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal |
---|
606 | # define BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 |
---|
607 | # define BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 |
---|
608 | |
---|
609 | //---------------------------------------------[ branch_condition ]----- |
---|
610 | |
---|
611 | # define SIZE_BRANCH_CONDITION 4 |
---|
612 | |
---|
613 | # define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK 0x0 // None condition (jump) |
---|
614 | # define BRANCH_CONDITION_NONE_WITH_WRITE_STACK 0x8 // None condition (jump) |
---|
615 | # define BRANCH_CONDITION_FLAG_UNSET 0x2 // Branch if Flag is clear |
---|
616 | # define BRANCH_CONDITION_FLAG_SET 0x3 // Branch if Flag is set |
---|
617 | # define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4 // Branch if a register is read |
---|
618 | # define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK 0xc // Branch if a register is read |
---|
619 | # define BRANCH_CONDITION_READ_STACK 0xf // Branch with pop in stack pointer |
---|
620 | |
---|
621 | //--------------------------------------------------[ instruction ]----- |
---|
622 | # define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format) |
---|
623 | |
---|
624 | enum |
---|
625 | { |
---|
626 | // ORBIS |
---|
627 | INSTRUCTION_L_ADD, |
---|
628 | INSTRUCTION_L_ADDC, |
---|
629 | INSTRUCTION_L_ADDI, |
---|
630 | INSTRUCTION_L_ADDIC, |
---|
631 | INSTRUCTION_L_AND, |
---|
632 | INSTRUCTION_L_ANDI, |
---|
633 | INSTRUCTION_L_BF, |
---|
634 | INSTRUCTION_L_BNF, |
---|
635 | INSTRUCTION_L_CMOV, |
---|
636 | INSTRUCTION_L_CSYNC, |
---|
637 | INSTRUCTION_L_CUST1, |
---|
638 | INSTRUCTION_L_CUST2, |
---|
639 | INSTRUCTION_L_CUST3, |
---|
640 | INSTRUCTION_L_CUST4, |
---|
641 | INSTRUCTION_L_CUST5, |
---|
642 | INSTRUCTION_L_CUST6, |
---|
643 | INSTRUCTION_L_CUST7, |
---|
644 | INSTRUCTION_L_CUST8, |
---|
645 | INSTRUCTION_L_DIV, |
---|
646 | INSTRUCTION_L_DIVU, |
---|
647 | INSTRUCTION_L_EXTBS, |
---|
648 | INSTRUCTION_L_EXTBZ, |
---|
649 | INSTRUCTION_L_EXTHS, |
---|
650 | INSTRUCTION_L_EXTHZ, |
---|
651 | INSTRUCTION_L_EXTWS, |
---|
652 | INSTRUCTION_L_EXTWZ, |
---|
653 | INSTRUCTION_L_FF1, |
---|
654 | INSTRUCTION_L_FL1, |
---|
655 | INSTRUCTION_L_J, |
---|
656 | INSTRUCTION_L_JAL, |
---|
657 | INSTRUCTION_L_JALR, |
---|
658 | INSTRUCTION_L_JR, |
---|
659 | INSTRUCTION_L_LBS, |
---|
660 | INSTRUCTION_L_LBZ, |
---|
661 | INSTRUCTION_L_LD, |
---|
662 | INSTRUCTION_L_LHS, |
---|
663 | INSTRUCTION_L_LHZ, |
---|
664 | INSTRUCTION_L_LWS, |
---|
665 | INSTRUCTION_L_LWZ, |
---|
666 | INSTRUCTION_L_MAC, |
---|
667 | INSTRUCTION_L_MACI, |
---|
668 | INSTRUCTION_L_MACRC, |
---|
669 | INSTRUCTION_L_MFSPR, |
---|
670 | INSTRUCTION_L_MOVHI, |
---|
671 | INSTRUCTION_L_MSB, |
---|
672 | INSTRUCTION_L_MSYNC, |
---|
673 | INSTRUCTION_L_MTSPR, |
---|
674 | INSTRUCTION_L_MUL, |
---|
675 | INSTRUCTION_L_MULI, |
---|
676 | INSTRUCTION_L_MULU, |
---|
677 | INSTRUCTION_L_NOP, |
---|
678 | INSTRUCTION_L_OR, |
---|
679 | INSTRUCTION_L_ORI, |
---|
680 | INSTRUCTION_L_PSYNC, |
---|
681 | INSTRUCTION_L_RFE, |
---|
682 | INSTRUCTION_L_ROR, |
---|
683 | INSTRUCTION_L_RORI, |
---|
684 | INSTRUCTION_L_SB, |
---|
685 | INSTRUCTION_L_SD, |
---|
686 | INSTRUCTION_L_SFEQ, |
---|
687 | INSTRUCTION_L_SFEQI, |
---|
688 | INSTRUCTION_L_SFGES, |
---|
689 | INSTRUCTION_L_SFGESI, |
---|
690 | INSTRUCTION_L_SFGEU, |
---|
691 | INSTRUCTION_L_SFGEUI, |
---|
692 | INSTRUCTION_L_SFGTS, |
---|
693 | INSTRUCTION_L_SFGTSI, |
---|
694 | INSTRUCTION_L_SFGTU, |
---|
695 | INSTRUCTION_L_SFGTUI, |
---|
696 | INSTRUCTION_L_SFLES, |
---|
697 | INSTRUCTION_L_SFLESI, |
---|
698 | INSTRUCTION_L_SFLEU, |
---|
699 | INSTRUCTION_L_SFLEUI, |
---|
700 | INSTRUCTION_L_SFLTS, |
---|
701 | INSTRUCTION_L_SFLTSI, |
---|
702 | INSTRUCTION_L_SFLTU, |
---|
703 | INSTRUCTION_L_SFLTUI, |
---|
704 | INSTRUCTION_L_SFNE, |
---|
705 | INSTRUCTION_L_SFNEI, |
---|
706 | INSTRUCTION_L_SH, |
---|
707 | INSTRUCTION_L_SLL, |
---|
708 | INSTRUCTION_L_SLLI, |
---|
709 | INSTRUCTION_L_SRA, |
---|
710 | INSTRUCTION_L_SRAI, |
---|
711 | INSTRUCTION_L_SRL, |
---|
712 | INSTRUCTION_L_SRLI, |
---|
713 | INSTRUCTION_L_SUB, |
---|
714 | INSTRUCTION_L_SW, |
---|
715 | INSTRUCTION_L_SYS, |
---|
716 | INSTRUCTION_L_TRAP, |
---|
717 | INSTRUCTION_L_XOR, |
---|
718 | INSTRUCTION_L_XORI, |
---|
719 | // ORFPX |
---|
720 | INSTRUCTION_LF_ADD_D, |
---|
721 | INSTRUCTION_LF_ADD_S, |
---|
722 | INSTRUCTION_LF_CUST1_D, |
---|
723 | INSTRUCTION_LF_CUST1_S, |
---|
724 | INSTRUCTION_LF_DIV_D, |
---|
725 | INSTRUCTION_LF_DIV_S, |
---|
726 | INSTRUCTION_LF_FTOI_D, |
---|
727 | INSTRUCTION_LF_FTOI_S, |
---|
728 | INSTRUCTION_LF_ITOF_D, |
---|
729 | INSTRUCTION_LF_ITOF_S, |
---|
730 | INSTRUCTION_LF_MADD_D, |
---|
731 | INSTRUCTION_LF_MADD_S, |
---|
732 | INSTRUCTION_LF_MUL_D, |
---|
733 | INSTRUCTION_LF_MUL_S, |
---|
734 | INSTRUCTION_LF_REM_D, |
---|
735 | INSTRUCTION_LF_REM_S, |
---|
736 | INSTRUCTION_LF_SFEQ_D, |
---|
737 | INSTRUCTION_LF_SFEQ_S, |
---|
738 | INSTRUCTION_LF_SFGE_D, |
---|
739 | INSTRUCTION_LF_SFGE_S, |
---|
740 | INSTRUCTION_LF_SFGT_D, |
---|
741 | INSTRUCTION_LF_SFGT_S, |
---|
742 | INSTRUCTION_LF_SFLE_D, |
---|
743 | INSTRUCTION_LF_SFLE_S, |
---|
744 | INSTRUCTION_LF_SFLT_D, |
---|
745 | INSTRUCTION_LF_SFLT_S, |
---|
746 | INSTRUCTION_LF_SFNE_D, |
---|
747 | INSTRUCTION_LF_SFNE_S, |
---|
748 | INSTRUCTION_LF_SUB_D, |
---|
749 | INSTRUCTION_LF_SUB_S, |
---|
750 | // ORVDX |
---|
751 | INSTRUCTION_LV_ADD_B, |
---|
752 | INSTRUCTION_LV_ADD_H, |
---|
753 | INSTRUCTION_LV_ADDS_B, |
---|
754 | INSTRUCTION_LV_ADDS_H, |
---|
755 | INSTRUCTION_LV_ADDU_B, |
---|
756 | INSTRUCTION_LV_ADDU_H, |
---|
757 | INSTRUCTION_LV_ADDUS_B, |
---|
758 | INSTRUCTION_LV_ADDUS_H, |
---|
759 | INSTRUCTION_LV_ALL_EQ_B, |
---|
760 | INSTRUCTION_LV_ALL_EQ_H, |
---|
761 | INSTRUCTION_LV_ALL_GE_B, |
---|
762 | INSTRUCTION_LV_ALL_GE_H, |
---|
763 | INSTRUCTION_LV_ALL_GT_B, |
---|
764 | INSTRUCTION_LV_ALL_GT_H, |
---|
765 | INSTRUCTION_LV_ALL_LE_B, |
---|
766 | INSTRUCTION_LV_ALL_LE_H, |
---|
767 | INSTRUCTION_LV_ALL_LT_B, |
---|
768 | INSTRUCTION_LV_ALL_LT_H, |
---|
769 | INSTRUCTION_LV_ALL_NE_B, |
---|
770 | INSTRUCTION_LV_ALL_NE_H, |
---|
771 | INSTRUCTION_LV_AND, |
---|
772 | INSTRUCTION_LV_ANY_EQ_B, |
---|
773 | INSTRUCTION_LV_ANY_EQ_H, |
---|
774 | INSTRUCTION_LV_ANY_GE_B, |
---|
775 | INSTRUCTION_LV_ANY_GE_H, |
---|
776 | INSTRUCTION_LV_ANY_GT_B, |
---|
777 | INSTRUCTION_LV_ANY_GT_H, |
---|
778 | INSTRUCTION_LV_ANY_LE_B, |
---|
779 | INSTRUCTION_LV_ANY_LE_H, |
---|
780 | INSTRUCTION_LV_ANY_LT_B, |
---|
781 | INSTRUCTION_LV_ANY_LT_H, |
---|
782 | INSTRUCTION_LV_ANY_NE_B, |
---|
783 | INSTRUCTION_LV_ANY_NE_H, |
---|
784 | INSTRUCTION_LV_AVG_B, |
---|
785 | INSTRUCTION_LV_AVG_H, |
---|
786 | INSTRUCTION_LV_CMP_EQ_B, |
---|
787 | INSTRUCTION_LV_CMP_EQ_H, |
---|
788 | INSTRUCTION_LV_CMP_GE_B, |
---|
789 | INSTRUCTION_LV_CMP_GE_H, |
---|
790 | INSTRUCTION_LV_CMP_GT_B, |
---|
791 | INSTRUCTION_LV_CMP_GT_H, |
---|
792 | INSTRUCTION_LV_CMP_LE_B, |
---|
793 | INSTRUCTION_LV_CMP_LE_H, |
---|
794 | INSTRUCTION_LV_CMP_LT_B, |
---|
795 | INSTRUCTION_LV_CMP_LT_H, |
---|
796 | INSTRUCTION_LV_CMP_NE_B, |
---|
797 | INSTRUCTION_LV_CMP_NE_H, |
---|
798 | INSTRUCTION_LV_CUST1, |
---|
799 | INSTRUCTION_LV_CUST2, |
---|
800 | INSTRUCTION_LV_CUST3, |
---|
801 | INSTRUCTION_LV_CUST4, |
---|
802 | INSTRUCTION_LV_MADDS_H, |
---|
803 | INSTRUCTION_LV_MAX_B, |
---|
804 | INSTRUCTION_LV_MAX_H, |
---|
805 | INSTRUCTION_LV_MERGE_B, |
---|
806 | INSTRUCTION_LV_MERGE_H, |
---|
807 | INSTRUCTION_LV_MIN_B, |
---|
808 | INSTRUCTION_LV_MIN_H, |
---|
809 | INSTRUCTION_LV_MSUBS_H, |
---|
810 | INSTRUCTION_LV_MULS_H, |
---|
811 | INSTRUCTION_LV_NAND, |
---|
812 | INSTRUCTION_LV_NOR, |
---|
813 | INSTRUCTION_LV_OR, |
---|
814 | INSTRUCTION_LV_PACK_B, |
---|
815 | INSTRUCTION_LV_PACK_H, |
---|
816 | INSTRUCTION_LV_PACKS_B, |
---|
817 | INSTRUCTION_LV_PACKS_H, |
---|
818 | INSTRUCTION_LV_PACKUS_B, |
---|
819 | INSTRUCTION_LV_PACKUS_H, |
---|
820 | INSTRUCTION_LV_PERM_N, |
---|
821 | INSTRUCTION_LV_RL_B, |
---|
822 | INSTRUCTION_LV_RL_H, |
---|
823 | INSTRUCTION_LV_SLL, |
---|
824 | INSTRUCTION_LV_SLL_B, |
---|
825 | INSTRUCTION_LV_SLL_H, |
---|
826 | INSTRUCTION_LV_SRA_B, |
---|
827 | INSTRUCTION_LV_SRA_H, |
---|
828 | INSTRUCTION_LV_SRL, |
---|
829 | INSTRUCTION_LV_SRL_B, |
---|
830 | INSTRUCTION_LV_SRL_H, |
---|
831 | INSTRUCTION_LV_SUB_B, |
---|
832 | INSTRUCTION_LV_SUB_H, |
---|
833 | INSTRUCTION_LV_SUBS_B, |
---|
834 | INSTRUCTION_LV_SUBS_H, |
---|
835 | INSTRUCTION_LV_SUBU_B, |
---|
836 | INSTRUCTION_LV_SUBU_H, |
---|
837 | INSTRUCTION_LV_SUBUS_B, |
---|
838 | INSTRUCTION_LV_SUBUS_H, |
---|
839 | INSTRUCTION_LV_UNPACK_B, |
---|
840 | INSTRUCTION_LV_UNPACK_H, |
---|
841 | INSTRUCTION_LV_XOR |
---|
842 | }; |
---|
843 | |
---|
844 | //-----------------------------------------------[ Code Operation ]----- |
---|
845 | |
---|
846 | # define MAX_OPCOD_0 64 // Instructions with immediat |
---|
847 | # define MAX_OPCOD_1 64 // Instruction ORFPX32/64 |
---|
848 | # define MAX_OPCOD_2 256 // Instruction ORVDX64 |
---|
849 | # define MAX_OPCOD_3 256 // Instructions Register-Register |
---|
850 | # define MAX_OPCOD_4 32 // Instructions "set flag" with register |
---|
851 | # define MAX_OPCOD_5 32 // Instructions "set flag" with immediat |
---|
852 | # define MAX_OPCOD_6 4 // Instruction Shift/Rotate with immediat |
---|
853 | # define MAX_OPCOD_7 16 // Instructions multiply with HI-LO |
---|
854 | # define MAX_OPCOD_8 2 // Instructions acces at HI-LO |
---|
855 | # define MAX_OPCOD_9 8 // Instructions special |
---|
856 | # define MAX_OPCOD_10 4 // Instructions no operation |
---|
857 | # define MAX_OPCOD_11 4 // Instruction Shift/Rotate with register |
---|
858 | # define MAX_OPCOD_12 4 // Instructions extend |
---|
859 | # define MAX_OPCOD_13 4 // Instructions extend (64b) |
---|
860 | |
---|
861 | // OPCOD_0 - [31:26] Instructions with immediat |
---|
862 | # define OPCOD_L_J 0x00 // 000_000 |
---|
863 | # define OPCOD_L_JAL 0x01 // 000_001 |
---|
864 | # define OPCOD_L_BNF 0x03 // 000_011 |
---|
865 | # define OPCOD_L_BF 0x04 // 000_100 |
---|
866 | # define OPCOD_L_RFE 0x09 // 001_001 |
---|
867 | # define OPCOD_L_JR 0x11 // 010_001 |
---|
868 | # define OPCOD_L_JALR 0x12 // 010_010 |
---|
869 | # define OPCOD_L_MACI 0x13 // 010_011 |
---|
870 | # define OPCOD_L_CUST1 0x1c // 011_100 |
---|
871 | # define OPCOD_L_CUST2 0x1d // 011_101 |
---|
872 | # define OPCOD_L_CUST3 0x1e // 011_110 |
---|
873 | # define OPCOD_L_CUST4 0x1f // 011_111 |
---|
874 | # define OPCOD_L_CUST5 0x3c // 111_100 |
---|
875 | # define OPCOD_L_CUST6 0x3d // 111_101 |
---|
876 | # define OPCOD_L_CUST7 0x3e // 111_110 |
---|
877 | # define OPCOD_L_CUST8 0x3f // 111_111 |
---|
878 | # define OPCOD_L_LD 0x20 // 100_000 |
---|
879 | # define OPCOD_L_LWZ 0x21 // 100_001 |
---|
880 | # define OPCOD_L_LWS 0x22 // 100_010 |
---|
881 | # define OPCOD_L_LBZ 0x23 // 100_011 |
---|
882 | # define OPCOD_L_LBS 0x24 // 100_100 |
---|
883 | # define OPCOD_L_LHZ 0x25 // 100_101 |
---|
884 | # define OPCOD_L_LHS 0x26 // 100_110 |
---|
885 | # define OPCOD_L_ADDI 0x27 // 100_111 |
---|
886 | # define OPCOD_L_ADDIC 0x28 // 101_000 |
---|
887 | # define OPCOD_L_ANDI 0x29 // 101_001 |
---|
888 | # define OPCOD_L_ORI 0x2a // 101_010 |
---|
889 | # define OPCOD_L_XORI 0x2b // 101_011 |
---|
890 | # define OPCOD_L_MULI 0x2c // 101_100 |
---|
891 | # define OPCOD_L_MFSPR 0x2d // 101_101 |
---|
892 | # define OPCOD_L_MTSPR 0x30 // 110_000 |
---|
893 | # define OPCOD_L_SD 0x34 // 110_100 |
---|
894 | # define OPCOD_L_SW 0x35 // 110_101 |
---|
895 | # define OPCOD_L_SB 0x36 // 110_110 |
---|
896 | # define OPCOD_L_SH 0x37 // 110_111 |
---|
897 | |
---|
898 | # define OPCOD_1 0x33 // 110_011 // Instruction ORFPX32/64 |
---|
899 | # define OPCOD_2 0x0a // 001_010 // Instruction ORVDX64 |
---|
900 | # define OPCOD_3 0x38 // 111_000 // Instructions Register-Register |
---|
901 | # define OPCOD_4 0x39 // 111_001 // Instructions "set flag" with register |
---|
902 | # define OPCOD_5 0x2f // 101_111 // Instructions "set flag" with immediat |
---|
903 | # define OPCOD_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat |
---|
904 | # define OPCOD_7 0x31 // 110_001 // Instructions multiply with HI-LO |
---|
905 | # define OPCOD_8 0x06 // 000_110 // Instructions acces at HI-LO |
---|
906 | # define OPCOD_9 0x08 // 001_000 // Instructions special |
---|
907 | # define OPCOD_10 0x05 // 000_101 // Instructions no operation |
---|
908 | |
---|
909 | // OPCOD_3 instructions - [9:8] [3:0] Instructions Register-Register |
---|
910 | # define OPCOD_L_ADD 0x00 // 00_0000 |
---|
911 | # define OPCOD_L_ADDC 0x01 // 00_0001 |
---|
912 | # define OPCOD_L_SUB 0x02 // 00_0010 |
---|
913 | # define OPCOD_L_AND 0x03 // 00_0011 |
---|
914 | # define OPCOD_L_OR 0x04 // 00_0100 |
---|
915 | # define OPCOD_L_XOR 0x05 // 00_0101 |
---|
916 | # define OPCOD_L_CMOV 0x0e // 00_1110 |
---|
917 | # define OPCOD_L_FF1 0x0f // 00_1111 |
---|
918 | # define OPCOD_L_FL1 0x1f // 01_1111 |
---|
919 | # define OPCOD_L_MUL 0x36 // 11_0110 |
---|
920 | # define OPCOD_L_DIV 0x39 // 11_1001 |
---|
921 | # define OPCOD_L_DIVU 0x3a // 11_1010 |
---|
922 | # define OPCOD_L_MULU 0x3b // 11_1011 |
---|
923 | |
---|
924 | # define OPCOD_11 0x8 // 1000 // Instruction Shift/Rotate with register |
---|
925 | # define OPCOD_12 0xc // 1100 // Instructions extend |
---|
926 | # define OPCOD_13 0xd // 1101 // Instructions extend (64b) |
---|
927 | |
---|
928 | // OPCOD_4 instructions - [25:21] Instructions "set flag" with register |
---|
929 | # define OPCOD_L_SFEQ 0x00 // 00000 |
---|
930 | # define OPCOD_L_SFNE 0x01 // 00001 |
---|
931 | # define OPCOD_L_SFGTU 0x02 // 00010 |
---|
932 | # define OPCOD_L_SFGEU 0x03 // 00011 |
---|
933 | # define OPCOD_L_SFLTU 0x04 // 00100 |
---|
934 | # define OPCOD_L_SFLEU 0x05 // 00101 |
---|
935 | # define OPCOD_L_SFGTS 0x0a // 01010 |
---|
936 | # define OPCOD_L_SFGES 0x0b // 01011 |
---|
937 | # define OPCOD_L_SFLTS 0x0c // 01100 |
---|
938 | # define OPCOD_L_SFLES 0x0d // 01101 |
---|
939 | |
---|
940 | // OPCOD_5 instructions - [25:21] Instructions "set flag" with immediat |
---|
941 | # define OPCOD_L_SFEQI 0x00 // 00000 |
---|
942 | # define OPCOD_L_SFNEI 0x01 // 00001 |
---|
943 | # define OPCOD_L_SFGTUI 0x02 // 00010 |
---|
944 | # define OPCOD_L_SFGEUI 0x03 // 00011 |
---|
945 | # define OPCOD_L_SFLTUI 0x04 // 00100 |
---|
946 | # define OPCOD_L_SFLEUI 0x05 // 00101 |
---|
947 | # define OPCOD_L_SFGTSI 0x0a // 01010 |
---|
948 | # define OPCOD_L_SFGESI 0x0b // 01011 |
---|
949 | # define OPCOD_L_SFLTSI 0x0c // 01100 |
---|
950 | # define OPCOD_L_SFLESI 0x0d // 01101 |
---|
951 | |
---|
952 | // OPCOD_6 instructions - [7:6] Instruction Shift/Rotate with immediat |
---|
953 | # define OPCOD_L_SLLI 0x0 // 00 |
---|
954 | # define OPCOD_L_SRLI 0x1 // 01 |
---|
955 | # define OPCOD_L_SRAI 0x2 // 10 |
---|
956 | # define OPCOD_L_RORI 0x3 // 11 |
---|
957 | |
---|
958 | // OPCOD_7 instructions - [3:0] Instructions multiply with HI-LO |
---|
959 | # define OPCOD_L_MAC 0x1 // 0001 |
---|
960 | # define OPCOD_L_MSB 0x2 // 0010 |
---|
961 | |
---|
962 | // OPCOD_8 instructions - [17] Instructions acces at HI-LO |
---|
963 | # define OPCOD_L_MOVHI 0x0 // 0 |
---|
964 | # define OPCOD_L_MACRC 0x1 // 1 |
---|
965 | |
---|
966 | // OPCOD_9 instructions - [25:23] Instruction special |
---|
967 | # define OPCOD_L_SYS 0x0 // 000 |
---|
968 | # define OPCOD_L_TRAP 0x2 // 010 |
---|
969 | # define OPCOD_L_MSYNC 0x4 // 100 |
---|
970 | # define OPCOD_L_PSYNC 0x5 // 101 |
---|
971 | # define OPCOD_L_CSYNC 0x6 // 110 |
---|
972 | |
---|
973 | // OPCOD_10 instructions - [25:24] Instruction no operation |
---|
974 | # define OPCOD_L_NOP 0x1 // 01 |
---|
975 | |
---|
976 | // OPCOD_11 instructions - [7:6] Instruction Shift/Rotate with register |
---|
977 | # define OPCOD_L_SLL 0x0 // 00 |
---|
978 | # define OPCOD_L_SRL 0x1 // 01 |
---|
979 | # define OPCOD_L_SRA 0x2 // 10 |
---|
980 | # define OPCOD_L_ROR 0x3 // 11 |
---|
981 | |
---|
982 | // OPCOD_12 instructions - [9:6] Instructions extend |
---|
983 | # define OPCOD_L_EXTHS 0x0 // 0000 |
---|
984 | # define OPCOD_L_EXTHZ 0x2 // 0010 |
---|
985 | # define OPCOD_L_EXTBS 0x1 // 0001 |
---|
986 | # define OPCOD_L_EXTBZ 0x3 // 0011 |
---|
987 | |
---|
988 | // OPCOD_13 instructions - [9:6] Instructions extend (64b) |
---|
989 | # define OPCOD_L_EXTWS 0x0 // 0000 |
---|
990 | # define OPCOD_L_EXTWZ 0x1 // 0001 |
---|
991 | |
---|
992 | }; // end namespace behavioural |
---|
993 | }; // end namespace morpheo |
---|
994 | |
---|
995 | #endif |
---|