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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h @ 81

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1	#ifndef morpheo_behavioural_Constants_h
2	#define morpheo_behavioural_Constants_h
3
4	namespace morpheo {
5	namespace behavioural {
6
7	//=========================================================[ Type ]=====
8	# define TYPE_ALU 0x0 // 00000 - unit multiple
9	# define TYPE_SHIFT 0x1 // 00000 - unit multiple
10	# define TYPE_MOVE 0x2 // 00000 - unit multiple
11	# define TYPE_TEST 0x3 // 00000 - unit multiple
12	# define TYPE_MUL_DIV 0x4 // 00000 - unit multiple
13	# define TYPE_EXTEND 0x5 // 00000 - unit multiple, type optionnal
14	# define TYPE_FIND 0x6 // 00000 - unit multiple, type optionnal
15	# define TYPE_SPECIAL 0x7 // 00000 - unit uniq
16	# define TYPE_CUSTOM 0x8 // 00000 - unit uniq , type optionnal
17	# define TYPE_BRANCH 0x9 // 00000 - unit multiple
18	# define TYPE_MEMORY 0xa // 00000 - unit uniq
19
20	# define SIZE_TYPE 5
21	# define MAX_TYPE (1<<SIZE_TYPE)
22
23	//====================================================[ Operation ]=====
24
25	//-------------------------------------------------------[ Memory ]-----
26	# define OPERATION_MEMORY_LOAD_8_Z 0x08 // 0_1000
27	# define OPERATION_MEMORY_LOAD_16_Z 0x09 // 0_1001
28	# define OPERATION_MEMORY_LOAD_32_Z 0x0a // 0_1010
29	# define OPERATION_MEMORY_LOAD_64_Z 0x0b // 0_1011
30	# define OPERATION_MEMORY_LOAD_8_S 0x18 // 1_1000
31	# define OPERATION_MEMORY_LOAD_16_S 0x19 // 1_1001
32	# define OPERATION_MEMORY_LOAD_32_S 0x1a // 1_1010
33	# define OPERATION_MEMORY_LOAD_64_S 0x1b // 1_1011
34
35	# define OPERATION_MEMORY_STORE_8 0x0c // 0_1100
36	# define OPERATION_MEMORY_STORE_16 0x0d // 0_1101
37	# define OPERATION_MEMORY_STORE_32 0x0e // 0_1110
38	# define OPERATION_MEMORY_STORE_64 0x0f // 0_1111
39	# define OPERATION_MEMORY_STORE_HEAD_OK 0x1c // 1_1100
40	# define OPERATION_MEMORY_STORE_HEAD_KO 0x1d // 1_1101
41
42	# define OPERATION_MEMORY_LOCK 0x01 // 0_0001
43	# define OPERATION_MEMORY_INVALIDATE 0x02 // 0_0010
44	# define OPERATION_MEMORY_PREFETCH 0x03 // 0_0011
45	# define OPERATION_MEMORY_FLUSH 0x06 // 0_0110
46	# define OPERATION_MEMORY_SYNCHRONIZATION 0x07 // 0_0111
47
48	#define is_operation_memory_load(x) \
49	((x == OPERATION_MEMORY_LOAD_8_Z ) or \
50	(x == OPERATION_MEMORY_LOAD_16_Z) or \
51	(x == OPERATION_MEMORY_LOAD_32_Z) or \
52	(x == OPERATION_MEMORY_LOAD_64_Z) or \
53	(x == OPERATION_MEMORY_LOAD_8_S ) or \
54	(x == OPERATION_MEMORY_LOAD_16_S) or \
55	(x == OPERATION_MEMORY_LOAD_32_S) or \
56	(x == OPERATION_MEMORY_LOAD_64_S) )
57
58	#define is_operation_memory_store(x) \
59	((x == OPERATION_MEMORY_STORE_8 ) or \
60	(x == OPERATION_MEMORY_STORE_16 ) or \
61	(x == OPERATION_MEMORY_STORE_32 ) or \
62	(x == OPERATION_MEMORY_STORE_64 ) or \
63	(x == OPERATION_MEMORY_STORE_HEAD_OK) or \
64	(x == OPERATION_MEMORY_STORE_HEAD_KO))
65
66	#define is_operation_memory_store_head(x) \
67	((x == OPERATION_MEMORY_STORE_HEAD_OK) or \
68	(x == OPERATION_MEMORY_STORE_HEAD_KO))
69
70	#define is_operation_memory_load_signed(x) \
71	((x == OPERATION_MEMORY_LOAD_8_S ) or \
72	(x == OPERATION_MEMORY_LOAD_16_S) or \
73	(x == OPERATION_MEMORY_LOAD_32_S) or \
74	(x == OPERATION_MEMORY_LOAD_64_S) )
75
76	# define MEMORY_ACCESS_8 0x0
77	# define MEMORY_ACCESS_16 0x1
78	# define MEMORY_ACCESS_32 0x2
79	# define MEMORY_ACCESS_64 0x3
80
81	# define MEMORY_SIZE_8 8
82	# define MEMORY_SIZE_16 16
83	# define MEMORY_SIZE_32 32
84	# define MEMORY_SIZE_64 64
85
86	# define MASK_MEMORY_ACCESS_8 0x0
87	# define MASK_MEMORY_ACCESS_16 0x1
88	# define MASK_MEMORY_ACCESS_32 0x3
89	# define MASK_MEMORY_ACCESS_64 0x7
90
91	#define memory_size(x) \
92	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
93	(x==OPERATION_MEMORY_LOAD_16_S)or \
94	(x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \
95	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
96	(x==OPERATION_MEMORY_LOAD_32_S)or \
97	(x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \
98	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
99	(x==OPERATION_MEMORY_LOAD_64_S)or \
100	(x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8)))
101
102	#define memory_access(x) \
103	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
104	(x==OPERATION_MEMORY_LOAD_16_S)or \
105	(x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \
106	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
107	(x==OPERATION_MEMORY_LOAD_32_S)or \
108	(x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \
109	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
110	(x==OPERATION_MEMORY_LOAD_64_S)or \
111	(x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8)))
112
113	#define mask_memory_access(x) \
114	(((x==OPERATION_MEMORY_LOAD_16_Z)or \
115	(x==OPERATION_MEMORY_LOAD_16_S)or \
116	(x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \
117	(((x==OPERATION_MEMORY_LOAD_32_Z)or \
118	(x==OPERATION_MEMORY_LOAD_32_S)or \
119	(x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \
120	(((x==OPERATION_MEMORY_LOAD_64_Z)or \
121	(x==OPERATION_MEMORY_LOAD_64_S)or \
122	(x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8)))
123
124	//---------------------------------------------[ Functionnal Unit ]-----
125	# define OPERATION_ALU_L_ADD 0x1 // 000_0000 l.add , l.addi
126	# define OPERATION_ALU_L_ADDC 0x2 // 000_0000 l.addc , l.addic
127	# define OPERATION_ALU_L_SUB 0x4 // 000_0000 l.sub
128	# define OPERATION_ALU_L_AND 0x8 // 000_0000 l.and , l.andi
129	# define OPERATION_ALU_L_OR 0x10 // 000_0000 l.or , l.ori
130	# define OPERATION_ALU_L_XOR 0x20 // 000_0000 l.xor , l.xori
131
132	# define OPERATION_SHIFT_L_SLL 0x1 // 000_0000 l.sll , l.slli
133	# define OPERATION_SHIFT_L_SRA 0x2 // 000_0000 l.sra , l.srai
134	# define OPERATION_SHIFT_L_SRL 0x4 // 000_0000 l.srl , l.srli
135	# define OPERATION_SHIFT_L_ROR 0x8 // 000_0000 l.ror , l.rori
136
137	# define OPERATION_MOVE_L_MOVHI 0x1 // 000_0000 l.movhi
138	# define OPERATION_MOVE_L_CMOV 0x2 // 000_0000 l.cmov
139
140	# define OPERATION_TEST_L_SFGES 0x41 // 000_0000 l.sfges , l.sfges
141	# define OPERATION_TEST_L_SFGEU 0x1 // 000_0000 l.sfgeu , l.sfgeu
142	# define OPERATION_TEST_L_SFGTS 0x42 // 000_0000 L.sfgts , l.sfgts
143	# define OPERATION_TEST_L_SFGTU 0x2 // 000_0000 l.sfgtu , l.sfgtu
144	# define OPERATION_TEST_L_SFLES 0x44 // 000_0000 l.sfles , l.sfles
145	# define OPERATION_TEST_L_SFLEU 0x4 // 000_0000 l.sfleu , l.sfleu
146	# define OPERATION_TEST_L_SFLTS 0x48 // 000_0000 l.sflts , l.sflts
147	# define OPERATION_TEST_L_SFLTU 0x8 // 000_0000 l.sfltu , l.sfltu
148	# define OPERATION_TEST_L_SFEQ 0x10 // 000_0000 l.sfeq , l.sfeqi
149	# define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei
150
151	# define OPERATION_MUL_DIV_L_MUL 0x1 // 000_0000 l.mul , l.muli
152	# define OPERATION_MUL_DIV_L_MULU 0x2 // 000_0000 l.mulu
153	# define OPERATION_MUL_DIV_L_DIV 0x4 // 000_0000 l.div
154	# define OPERATION_MUL_DIV_L_DIVU 0x8 // 000_0000 l.divu
155
156	# define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz
157	# define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0000 l.extbs , l.exths, l.extws
158
159	# define OPERATION_FIND_L_FF1 0x1 // 000_0000 l.ff1
160	# define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1
161
162	# define OPERATION_SPECIAL_L_NOP 0xff // 000_0000 l.nop
163	# define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr
164	# define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr
165	# define OPERATION_SPECIAL_L_RFE 0x4 // 000_0100 l.rfe
166	# define OPERATION_SPECIAL_L_MAC 0x11 // 001_0001 l.mac , l.maci
167	# define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc
168	# define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb
169	# define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync
170	# define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync
171	# define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync
172	# define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys
173	# define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap
174
175
176	# define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j
177	# define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0000 l.bnf
178	# define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0000 l.bf
179	# define OPERATION_BRANCH_L_JALR 0x8 // 000_0000 l.jal , l.jalr , l.jr
180
181	//-------------------------------------------------------[ Custom ]-----
182
183	# define OPERATION_CUSTOM_L_1 0x40 // 100_0000
184	# define OPERATION_CUSTOM_L_2 0x41 // 100_0001
185	# define OPERATION_CUSTOM_L_3 0x42 // 100_0010
186	# define OPERATION_CUSTOM_L_4 0x43 // 100_0011
187	# define OPERATION_CUSTOM_L_5 0x44 // 100_0100
188	# define OPERATION_CUSTOM_L_6 0x45 // 100_0101
189	# define OPERATION_CUSTOM_L_7 0x46 // 100_0110
190	# define OPERATION_CUSTOM_L_8 0x47 // 100_0111
191	# define OPERATION_CUSTOM_LF_1_D 0x48 // 100_1000
192	# define OPERATION_CUSTOM_LF_1_S 0x49 // 100_1001
193	# define OPERATION_CUSTOM_LV_1 0x4c // 100_1100
194	# define OPERATION_CUSTOM_LV_2 0x4d // 100_1101
195	# define OPERATION_CUSTOM_LV_3 0x4e // 100_1110
196	# define OPERATION_CUSTOM_LV_4 0x4f // 100_1111
197
198	# define SIZE_OPERATION 7
199	# define MAX_OPERATION (1<<SIZE_OPERATION)
200
201	//====================================================[ Exception ]=====
202	// Exception - OpenRISC
203
204	# define SIZE_EXCEPTION 5
205	# define SIZE_EXCEPTION_USE 4
206	# define SIZE_EXCEPTION_MEMORY 3
207	# define SIZE_EXCEPTION_CUSTOM 3
208	# define SIZE_EXCEPTION_ALU 2
209	# define SIZE_EXCEPTION_DECOD 2
210	# define SIZE_EXCEPTION_IFETCH 2
211
212	# define EXCEPTION_NONE 0x00 // none exception
213	# define EXCEPTION_RESET 0x01 // software or hardware reset
214	# define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress
215	# define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables
216	# define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables
217	# define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption
218	# define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned
219	# define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented)
220	# define EXCEPTION_INTERRUPT 0x08 // External interruption
221	# define EXCEPTION_DATA_TLB 0x09 // DTLB miss
222	# define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss
223	# define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context
224	# define EXCEPTION_SYSCALL 0x0c // System Call
225	# define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction
226	# define EXCEPTION_TRAP 0x0e // L.trap or debug unit
227	# define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage
228	# define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage
229	# define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage
230	# define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage
231	# define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage
232	# define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage
233	# define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions
234	# define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions
235	# define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions
236	# define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions
237	# define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions
238	# define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions
239	# define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions
240	# define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions
241	# define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions
242	# define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions
243	# define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions
244
245
246	#define exception_to_address(x) (x<<8)
247
248	// Exception Execution
249	# define EXCEPTION_MEMORY_NONE 0x0 // Load/Store generate none exception
250	# define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned
251	# define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss
252	# define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables
253	# define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address
254	# define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation
255	# define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x6 // The load is speculative : write in register file, but don't commit
256
257	# define EXCEPTION_CUSTOM_NONE 0x1 // Custom unit generate none exception
258	# define EXCEPTION_CUSTOM_CUST_0 0x1 // Reserved for custom exceptions
259	# define EXCEPTION_CUSTOM_CUST_1 0x2 // Reserved for custom exceptions
260	# define EXCEPTION_CUSTOM_CUST_2 0x3 // Reserved for custom exceptions
261	# define EXCEPTION_CUSTOM_CUST_3 0x4 // Reserved for custom exceptions
262	# define EXCEPTION_CUSTOM_CUST_4 0x5 // Reserved for custom exceptions
263	# define EXCEPTION_CUSTOM_CUST_5 0x6 // Reserved for custom exceptions
264	# define EXCEPTION_CUSTOM_CUST_6 0x7 // Reserved for custom exceptions
265
266	# define EXCEPTION_ALU_NONE 0x0 // Functionnal unit generate none exception
267	# define EXCEPTION_ALU_RANGE 0x1 //
268	# define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x2 // SPR present in ALU but not compatible privilege
269	# define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE 0x3 // SPR not present in ALU
270
271	# define EXCEPTION_DECOD_NONE 0x0 // none exception
272	# define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x1 // Instruction is illegal (no implemented)
273	# define EXCEPTION_DECOD_SYSCALL 0x2 // System Call
274	//#define EXCEPTION_DECOD_TRAP 0x4 // L.trap or debug unit (note : must read SR !)
275
276	# define EXCEPTION_IFETCH_NONE 0x0 // Fetch Unit generate none exception
277	# define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x1 // ITLB miss
278	# define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x2 // No matching or page violation protection in pages tables
279	# define EXCEPTION_IFETCH_BUS_ERROR 0x3 // Access at a invalid physical address
280
281	# define EXCEPTION_USE_NONE 0x0 //
282	# define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x1 // illegal_instruction
283	# define EXCEPTION_USE_RANGE 0x2 // range
284	# define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x3 // TLB miss, page fault, bus error, alignment
285	# define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x4 // TLB miss, page fault, bus error
286	# define EXCEPTION_USE_SYSCALL 0x5 // syscall
287	# define EXCEPTION_USE_TRAP 0x6 // trap
288	# define EXCEPTION_USE_CUSTOM_0 0x7 //
289	# define EXCEPTION_USE_CUSTOM_1 0x8 //
290	# define EXCEPTION_USE_CUSTOM_2 0x9 //
291	# define EXCEPTION_USE_CUSTOM_3 0xa //
292	# define EXCEPTION_USE_CUSTOM_4 0xb //
293	# define EXCEPTION_USE_CUSTOM_5 0xc //
294	# define EXCEPTION_USE_CUSTOM_6 0xd //
295
296	//=======================================================[ icache ]=====
297
298	//--------------------------------------------------[ icache_type ]-----
299
300	# define SIZE_ICACHE_TYPE 2
301
302	# define ICACHE_TYPE_LOAD 0x0 // 0000
303	# define ICACHE_TYPE_LOCK 0x1 // 0001
304	# define ICACHE_TYPE_INVALIDATE 0x2 // 0010
305	# define ICACHE_TYPE_PREFETCH 0x3 // 0011
306
307	// just take the 2 less significative bits.
308	#define operation_to_icache_type(x) (x&0x3)
309
310	//-------------------------------------------------[ icache_error ]-----
311
312	# define SIZE_ICACHE_ERROR 1
313
314	# define ICACHE_ERROR_NONE 0x0
315	# define ICACHE_ERROR_BUS_ERROR 0x1
316
317	//=======================================================[ dcache ]=====
318
319	//--------------------------------------------------[ dcache_type ]-----
320
321	# define SIZE_DCACHE_TYPE 4
322
323	//#define DCACHE_TYPE_ 0x0 // 0000
324	# define DCACHE_TYPE_LOCK 0x1 // 0001
325	# define DCACHE_TYPE_INVALIDATE 0x2 // 0010
326	# define DCACHE_TYPE_PREFETCH 0x3 // 0011
327	//#define DCACHE_TYPE_ 0x4 // 0100
328	//#define DCACHE_TYPE_ 0x5 // 0101
329	# define DCACHE_TYPE_FLUSH 0x6 // 0110
330	# define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111
331	# define DCACHE_TYPE_LOAD_8 0x8 // 1000
332	# define DCACHE_TYPE_LOAD_16 0x9 // 1001
333	# define DCACHE_TYPE_LOAD_32 0xa // 1010
334	# define DCACHE_TYPE_LOAD_64 0xb // 1011
335	# define DCACHE_TYPE_STORE_8 0xc // 1100
336	# define DCACHE_TYPE_STORE_16 0xd // 1101
337	# define DCACHE_TYPE_STORE_32 0xe // 1110
338	# define DCACHE_TYPE_STORE_64 0xf // 1111
339
340	// just take the 4 less significative bits.
341	#define operation_to_dcache_type(x) (x&0xf)
342
343	//-------------------------------------------------[ dcache_error ]-----
344
345	# define SIZE_DCACHE_ERROR 1
346
347	# define DCACHE_ERROR_NONE 0x0
348	# define DCACHE_ERROR_BUS_ERROR 0x1
349
350	//=================================================[ special_data ]=====
351
352	# define SIZE_SPECIAL_DATA 2
353
354	// Position of flag in "rename register SR" (NOT IN "SR")
355	# define FLAG_POSITION_F 0x0 // Conditionnal branch flag
356	# define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation
357	# define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation
358
359	# define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag
360	# define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation
361	# define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation
362
363	//==========================================================[ spr ]=====
364
365	enum
366	{
367	GROUP_SYSTEM_AND_CONTROL, // 0
368	GROUP_DMMU, // 1
369	GROUP_IMMU, // 2
370	GROUP_DCACHE, // 3
371	GROUP_ICACHE, // 4
372	GROUP_MAC, // 5
373	GROUP_DEBUG, // 6
374	GROUP_PERFORMANCE_COUNTER, // 7
375	GROUP_POWER_MANAGEMENT, // 8
376	GROUP_PIC, // 9
377	GROUP_TICK_TIMER, // 10
378	GROUP_FLOATING_POINT, // 11
379	GROUP_RESERVED_1, // 12
380	GROUP_RESERVED_2, // 13
381	GROUP_RESERVED_3, // 14
382	GROUP_RESERVED_4, // 15
383	GROUP_RESERVED_5, // 16
384	GROUP_RESERVED_6, // 17
385	GROUP_RESERVED_7, // 18
386	GROUP_RESERVED_8, // 19
387	GROUP_RESERVED_9, // 20
388	GROUP_RESERVED_10, // 21
389	GROUP_RESERVED_11, // 22
390	GROUP_RESERVED_12, // 23
391	GROUP_CUSTOM_1, // 24
392	GROUP_CUSTOM_2, // 25
393	GROUP_CUSTOM_3, // 26
394	GROUP_CUSTOM_4, // 27
395	GROUP_CUSTOM_5, // 28
396	GROUP_CUSTOM_6, // 29
397	GROUP_CUSTOM_7, // 30
398	GROUP_CUSTOM_8 // 31
399	};
400
401	# define NB_GROUP 32
402	# define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536
403	# define NB_REG_GROUP_DMMU 1536
404	# define NB_REG_GROUP_IMMU 1536
405	# define NB_REG_GROUP_DCACHE 6
406	# define NB_REG_GROUP_ICACHE 4
407	# define NB_REG_GROUP_MAC 3
408	# define NB_REG_GROUP_DEBUG 22
409	# define NB_REG_GROUP_PERFORMANCE_COUNTER 16
410	# define NB_REG_GROUP_POWER_MANAGEMENT 1
411	# define NB_REG_GROUP_PIC 3
412	# define NB_REG_GROUP_TICK_TIMER 2
413	# define NB_REG_GROUP_FLOATING_POINT 0
414	# define NB_REG_GROUP_RESERVED_1 0
415	# define NB_REG_GROUP_RESERVED_2 0
416	# define NB_REG_GROUP_RESERVED_3 0
417	# define NB_REG_GROUP_RESERVED_4 0
418	# define NB_REG_GROUP_RESERVED_5 0
419	# define NB_REG_GROUP_RESERVED_6 0
420	# define NB_REG_GROUP_RESERVED_7 0
421	# define NB_REG_GROUP_RESERVED_8 0
422	# define NB_REG_GROUP_RESERVED_9 0
423	# define NB_REG_GROUP_RESERVED_10 0
424	# define NB_REG_GROUP_RESERVED_11 0
425	# define NB_REG_GROUP_RESERVED_12 0
426	# define NB_REG_GROUP_CUSTOM_1 0
427	# define NB_REG_GROUP_CUSTOM_2 0
428	# define NB_REG_GROUP_CUSTOM_3 0
429	# define NB_REG_GROUP_CUSTOM_4 0
430	# define NB_REG_GROUP_CUSTOM_5 0
431	# define NB_REG_GROUP_CUSTOM_6 0
432	# define NB_REG_GROUP_CUSTOM_7 0
433	# define NB_REG_GROUP_CUSTOM_8 0
434
435
436	// GROUP_MAC
437	# define SPR_MACLO 1 // MAC Low
438	# define SPR_MACHI 2 // MAC High
439
440	# define NB_SPR_LOGIC 2
441	# define LOG2_NB_SPR_LOGIC 1
442	// SPR_LOGIC[0] = F
443	// SPR_LOGIC[1] = Carry, Overflow
444	# define SPR_LOGIC_SR_F 0x0 // Status register bit F (size = 1)
445	# define SPR_LOGIC_SR_CY_OV 0x1 // Status register bit overflow and carry (size = 2)
446
447	//----------------------------------------------[ spr_mode_access ]-----
448
449	# define SPR_ACCESS_MODE_NONE 0x0 // 000
450	# define SPR_ACCESS_MODE_READ_ONLY 0x1 // 001
451	# define SPR_ACCESS_MODE_WRITE_ONLY 0x2 // 010
452	# define SPR_ACCESS_MODE_READ_WRITE 0x3 // 011
453	# define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read
454
455	//--------------------------------------------------------[ event ]-----
456	# define SIZE_EVENT_STATE 2
457
458	# define EVENT_STATE_NO_EVENT 0 // no event : current case
459	# define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event
460	# define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context)
461	# define EVENT_STATE_END 3 // CPU can continue
462
463	# define SIZE_EVENT_TYPE 3
464
465	# define EVENT_TYPE_NONE 0 // no event
466	# define EVENT_TYPE_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation)
467	# define EVENT_TYPE_EXCEPTION 2 // exception or interruption occure
468	# define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss)
469	# define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction
470	# define EVENT_TYPE_MSYNC 5 // decod a memory synchronization
471	# define EVENT_TYPE_PSYNC 6 // decod a pipeline synchronization
472	# define EVENT_TYPE_CSYNC 7 // decod a context synchronization
473
474	//-------------------------------------------------[ branch_state ]-----
475	# define SIZE_BRANCH_STATE 2
476
477	# define BRANCH_STATE_NONE 0x0 // 0 0
478	# define BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal
479	# define BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0
480	# define BRANCH_STATE_SPEC_TAKE 0x3 // 1 1
481
482	//---------------------------------------------[ branch_condition ]-----
483
484	# define SIZE_BRANCH_CONDITION 4
485
486	# define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK 0x0 // None condition (jump)
487	# define BRANCH_CONDITION_NONE_WITH_WRITE_STACK 0x8 // None condition (jump)
488	# define BRANCH_CONDITION_FLAG_UNSET 0x2 // Branch if Flag is clear
489	# define BRANCH_CONDITION_FLAG_SET 0x3 // Branch if Flag is set
490	# define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4 // Branch if a register is read
491	# define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK 0xc // Branch if a register is read
492	# define BRANCH_CONDITION_READ_STACK 0xf // Branch with pop in stack pointer
493
494	//--------------------------------------------------[ instruction ]-----
495	# define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format)
496
497	enum
498	{
499	// ORBIS
500	INSTRUCTION_L_ADD,
501	INSTRUCTION_L_ADDC,
502	INSTRUCTION_L_ADDI,
503	INSTRUCTION_L_ADDIC,
504	INSTRUCTION_L_AND,
505	INSTRUCTION_L_ANDI,
506	INSTRUCTION_L_BF,
507	INSTRUCTION_L_BNF,
508	INSTRUCTION_L_CMOV,
509	INSTRUCTION_L_CSYNC,
510	INSTRUCTION_L_CUST1,
511	INSTRUCTION_L_CUST2,
512	INSTRUCTION_L_CUST3,
513	INSTRUCTION_L_CUST4,
514	INSTRUCTION_L_CUST5,
515	INSTRUCTION_L_CUST6,
516	INSTRUCTION_L_CUST7,
517	INSTRUCTION_L_CUST8,
518	INSTRUCTION_L_DIV,
519	INSTRUCTION_L_DIVU,
520	INSTRUCTION_L_EXTBS,
521	INSTRUCTION_L_EXTBZ,
522	INSTRUCTION_L_EXTHS,
523	INSTRUCTION_L_EXTHZ,
524	INSTRUCTION_L_EXTWS,
525	INSTRUCTION_L_EXTWZ,
526	INSTRUCTION_L_FF1,
527	INSTRUCTION_L_FL1,
528	INSTRUCTION_L_J,
529	INSTRUCTION_L_JAL,
530	INSTRUCTION_L_JALR,
531	INSTRUCTION_L_JR,
532	INSTRUCTION_L_LBS,
533	INSTRUCTION_L_LBZ,
534	INSTRUCTION_L_LD,
535	INSTRUCTION_L_LHS,
536	INSTRUCTION_L_LHZ,
537	INSTRUCTION_L_LWS,
538	INSTRUCTION_L_LWZ,
539	INSTRUCTION_L_MAC,
540	INSTRUCTION_L_MACI,
541	INSTRUCTION_L_MACRC,
542	INSTRUCTION_L_MFSPR,
543	INSTRUCTION_L_MOVHI,
544	INSTRUCTION_L_MSB,
545	INSTRUCTION_L_MSYNC,
546	INSTRUCTION_L_MTSPR,
547	INSTRUCTION_L_MUL,
548	INSTRUCTION_L_MULI,
549	INSTRUCTION_L_MULU,
550	INSTRUCTION_L_NOP,
551	INSTRUCTION_L_OR,
552	INSTRUCTION_L_ORI,
553	INSTRUCTION_L_PSYNC,
554	INSTRUCTION_L_RFE,
555	INSTRUCTION_L_ROR,
556	INSTRUCTION_L_RORI,
557	INSTRUCTION_L_SB,
558	INSTRUCTION_L_SD,
559	INSTRUCTION_L_SFEQ,
560	INSTRUCTION_L_SFEQI,
561	INSTRUCTION_L_SFGES,
562	INSTRUCTION_L_SFGESI,
563	INSTRUCTION_L_SFGEU,
564	INSTRUCTION_L_SFGEUI,
565	INSTRUCTION_L_SFGTS,
566	INSTRUCTION_L_SFGTSI,
567	INSTRUCTION_L_SFGTU,
568	INSTRUCTION_L_SFGTUI,
569	INSTRUCTION_L_SFLES,
570	INSTRUCTION_L_SFLESI,
571	INSTRUCTION_L_SFLEU,
572	INSTRUCTION_L_SFLEUI,
573	INSTRUCTION_L_SFLTS,
574	INSTRUCTION_L_SFLTSI,
575	INSTRUCTION_L_SFLTU,
576	INSTRUCTION_L_SFLTUI,
577	INSTRUCTION_L_SFNE,
578	INSTRUCTION_L_SFNEI,
579	INSTRUCTION_L_SH,
580	INSTRUCTION_L_SLL,
581	INSTRUCTION_L_SLLI,
582	INSTRUCTION_L_SRA,
583	INSTRUCTION_L_SRAI,
584	INSTRUCTION_L_SRL,
585	INSTRUCTION_L_SRLI,
586	INSTRUCTION_L_SUB,
587	INSTRUCTION_L_SW,
588	INSTRUCTION_L_SYS,
589	INSTRUCTION_L_TRAP,
590	INSTRUCTION_L_XOR,
591	INSTRUCTION_L_XORI,
592	// ORFPX
593	INSTRUCTION_LF_ADD_D,
594	INSTRUCTION_LF_ADD_S,
595	INSTRUCTION_LF_CUST1_D,
596	INSTRUCTION_LF_CUST1_S,
597	INSTRUCTION_LF_DIV_D,
598	INSTRUCTION_LF_DIV_S,
599	INSTRUCTION_LF_FTOI_D,
600	INSTRUCTION_LF_FTOI_S,
601	INSTRUCTION_LF_ITOF_D,
602	INSTRUCTION_LF_ITOF_S,
603	INSTRUCTION_LF_MADD_D,
604	INSTRUCTION_LF_MADD_S,
605	INSTRUCTION_LF_MUL_D,
606	INSTRUCTION_LF_MUL_S,
607	INSTRUCTION_LF_REM_D,
608	INSTRUCTION_LF_REM_S,
609	INSTRUCTION_LF_SFEQ_D,
610	INSTRUCTION_LF_SFEQ_S,
611	INSTRUCTION_LF_SFGE_D,
612	INSTRUCTION_LF_SFGE_S,
613	INSTRUCTION_LF_SFGT_D,
614	INSTRUCTION_LF_SFGT_S,
615	INSTRUCTION_LF_SFLE_D,
616	INSTRUCTION_LF_SFLE_S,
617	INSTRUCTION_LF_SFLT_D,
618	INSTRUCTION_LF_SFLT_S,
619	INSTRUCTION_LF_SFNE_D,
620	INSTRUCTION_LF_SFNE_S,
621	INSTRUCTION_LF_SUB_D,
622	INSTRUCTION_LF_SUB_S,
623	// ORVDX
624	INSTRUCTION_LV_ADD_B,
625	INSTRUCTION_LV_ADD_H,
626	INSTRUCTION_LV_ADDS_B,
627	INSTRUCTION_LV_ADDS_H,
628	INSTRUCTION_LV_ADDU_B,
629	INSTRUCTION_LV_ADDU_H,
630	INSTRUCTION_LV_ADDUS_B,
631	INSTRUCTION_LV_ADDUS_H,
632	INSTRUCTION_LV_ALL_EQ_B,
633	INSTRUCTION_LV_ALL_EQ_H,
634	INSTRUCTION_LV_ALL_GE_B,
635	INSTRUCTION_LV_ALL_GE_H,
636	INSTRUCTION_LV_ALL_GT_B,
637	INSTRUCTION_LV_ALL_GT_H,
638	INSTRUCTION_LV_ALL_LE_B,
639	INSTRUCTION_LV_ALL_LE_H,
640	INSTRUCTION_LV_ALL_LT_B,
641	INSTRUCTION_LV_ALL_LT_H,
642	INSTRUCTION_LV_ALL_NE_B,
643	INSTRUCTION_LV_ALL_NE_H,
644	INSTRUCTION_LV_AND,
645	INSTRUCTION_LV_ANY_EQ_B,
646	INSTRUCTION_LV_ANY_EQ_H,
647	INSTRUCTION_LV_ANY_GE_B,
648	INSTRUCTION_LV_ANY_GE_H,
649	INSTRUCTION_LV_ANY_GT_B,
650	INSTRUCTION_LV_ANY_GT_H,
651	INSTRUCTION_LV_ANY_LE_B,
652	INSTRUCTION_LV_ANY_LE_H,
653	INSTRUCTION_LV_ANY_LT_B,
654	INSTRUCTION_LV_ANY_LT_H,
655	INSTRUCTION_LV_ANY_NE_B,
656	INSTRUCTION_LV_ANY_NE_H,
657	INSTRUCTION_LV_AVG_B,
658	INSTRUCTION_LV_AVG_H,
659	INSTRUCTION_LV_CMP_EQ_B,
660	INSTRUCTION_LV_CMP_EQ_H,
661	INSTRUCTION_LV_CMP_GE_B,
662	INSTRUCTION_LV_CMP_GE_H,
663	INSTRUCTION_LV_CMP_GT_B,
664	INSTRUCTION_LV_CMP_GT_H,
665	INSTRUCTION_LV_CMP_LE_B,
666	INSTRUCTION_LV_CMP_LE_H,
667	INSTRUCTION_LV_CMP_LT_B,
668	INSTRUCTION_LV_CMP_LT_H,
669	INSTRUCTION_LV_CMP_NE_B,
670	INSTRUCTION_LV_CMP_NE_H,
671	INSTRUCTION_LV_CUST1,
672	INSTRUCTION_LV_CUST2,
673	INSTRUCTION_LV_CUST3,
674	INSTRUCTION_LV_CUST4,
675	INSTRUCTION_LV_MADDS_H,
676	INSTRUCTION_LV_MAX_B,
677	INSTRUCTION_LV_MAX_H,
678	INSTRUCTION_LV_MERGE_B,
679	INSTRUCTION_LV_MERGE_H,
680	INSTRUCTION_LV_MIN_B,
681	INSTRUCTION_LV_MIN_H,
682	INSTRUCTION_LV_MSUBS_H,
683	INSTRUCTION_LV_MULS_H,
684	INSTRUCTION_LV_NAND,
685	INSTRUCTION_LV_NOR,
686	INSTRUCTION_LV_OR,
687	INSTRUCTION_LV_PACK_B,
688	INSTRUCTION_LV_PACK_H,
689	INSTRUCTION_LV_PACKS_B,
690	INSTRUCTION_LV_PACKS_H,
691	INSTRUCTION_LV_PACKUS_B,
692	INSTRUCTION_LV_PACKUS_H,
693	INSTRUCTION_LV_PERM_N,
694	INSTRUCTION_LV_RL_B,
695	INSTRUCTION_LV_RL_H,
696	INSTRUCTION_LV_SLL,
697	INSTRUCTION_LV_SLL_B,
698	INSTRUCTION_LV_SLL_H,
699	INSTRUCTION_LV_SRA_B,
700	INSTRUCTION_LV_SRA_H,
701	INSTRUCTION_LV_SRL,
702	INSTRUCTION_LV_SRL_B,
703	INSTRUCTION_LV_SRL_H,
704	INSTRUCTION_LV_SUB_B,
705	INSTRUCTION_LV_SUB_H,
706	INSTRUCTION_LV_SUBS_B,
707	INSTRUCTION_LV_SUBS_H,
708	INSTRUCTION_LV_SUBU_B,
709	INSTRUCTION_LV_SUBU_H,
710	INSTRUCTION_LV_SUBUS_B,
711	INSTRUCTION_LV_SUBUS_H,
712	INSTRUCTION_LV_UNPACK_B,
713	INSTRUCTION_LV_UNPACK_H,
714	INSTRUCTION_LV_XOR
715	};
716
717	//-----------------------------------------------[ Code Operation ]-----
718
719	# define MAX_OPCOD_0 64 // Instructions with immediat
720	# define MAX_OPCOD_1 64 // Instruction ORFPX32/64
721	# define MAX_OPCOD_2 256 // Instruction ORVDX64
722	# define MAX_OPCOD_3 256 // Instructions Register-Register
723	# define MAX_OPCOD_4 32 // Instructions "set flag" with register
724	# define MAX_OPCOD_5 32 // Instructions "set flag" with immediat
725	# define MAX_OPCOD_6 4 // Instruction Shift/Rotate with immediat
726	# define MAX_OPCOD_7 16 // Instructions multiply with HI-LO
727	# define MAX_OPCOD_8 2 // Instructions acces at HI-LO
728	# define MAX_OPCOD_9 8 // Instructions special
729	# define MAX_OPCOD_10 4 // Instructions no operation
730	# define MAX_OPCOD_11 4 // Instruction Shift/Rotate with register
731	# define MAX_OPCOD_12 4 // Instructions extend
732	# define MAX_OPCOD_13 4 // Instructions extend (64b)
733
734	// OPCOD_0 - [31:26] Instructions with immediat
735	# define OPCOD_L_J 0x00 // 000_000
736	# define OPCOD_L_JAL 0x01 // 000_001
737	# define OPCOD_L_BNF 0x03 // 000_011
738	# define OPCOD_L_BF 0x04 // 000_100
739	# define OPCOD_L_RFE 0x09 // 001_001
740	# define OPCOD_L_JR 0x11 // 010_001
741	# define OPCOD_L_JALR 0x12 // 010_010
742	# define OPCOD_L_MACI 0x13 // 010_011
743	# define OPCOD_L_CUST1 0x1c // 011_100
744	# define OPCOD_L_CUST2 0x1d // 011_101
745	# define OPCOD_L_CUST3 0x1e // 011_110
746	# define OPCOD_L_CUST4 0x1f // 011_111
747	# define OPCOD_L_CUST5 0x3c // 111_100
748	# define OPCOD_L_CUST6 0x3d // 111_101
749	# define OPCOD_L_CUST7 0x3e // 111_110
750	# define OPCOD_L_CUST8 0x3f // 111_111
751	# define OPCOD_L_LD 0x20 // 100_000
752	# define OPCOD_L_LWZ 0x21 // 100_001
753	# define OPCOD_L_LWS 0x22 // 100_010
754	# define OPCOD_L_LBZ 0x23 // 100_011
755	# define OPCOD_L_LBS 0x24 // 100_100
756	# define OPCOD_L_LHZ 0x25 // 100_101
757	# define OPCOD_L_LHS 0x26 // 100_110
758	# define OPCOD_L_ADDI 0x27 // 100_111
759	# define OPCOD_L_ADDIC 0x28 // 101_000
760	# define OPCOD_L_ANDI 0x29 // 101_001
761	# define OPCOD_L_ORI 0x2a // 101_010
762	# define OPCOD_L_XORI 0x2b // 101_011
763	# define OPCOD_L_MULI 0x2c // 101_100
764	# define OPCOD_L_MFSPR 0x2d // 101_101
765	# define OPCOD_L_MTSPR 0x30 // 110_000
766	# define OPCOD_L_SD 0x34 // 110_100
767	# define OPCOD_L_SW 0x35 // 110_101
768	# define OPCOD_L_SB 0x36 // 110_110
769	# define OPCOD_L_SH 0x37 // 110_111
770
771	# define OPCOD_1 0x33 // 110_011 // Instruction ORFPX32/64
772	# define OPCOD_2 0x0a // 001_010 // Instruction ORVDX64
773	# define OPCOD_3 0x38 // 111_000 // Instructions Register-Register
774	# define OPCOD_4 0x39 // 111_001 // Instructions "set flag" with register
775	# define OPCOD_5 0x2f // 101_111 // Instructions "set flag" with immediat
776	# define OPCOD_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat
777	# define OPCOD_7 0x31 // 110_001 // Instructions multiply with HI-LO
778	# define OPCOD_8 0x06 // 000_110 // Instructions acces at HI-LO
779	# define OPCOD_9 0x08 // 001_000 // Instructions special
780	# define OPCOD_10 0x05 // 000_101 // Instructions no operation
781
782	// OPCOD_3 instructions - [9:8] [3:0] Instructions Register-Register
783	# define OPCOD_L_ADD 0x00 // 00_0000
784	# define OPCOD_L_ADDC 0x01 // 00_0001
785	# define OPCOD_L_SUB 0x02 // 00_0010
786	# define OPCOD_L_AND 0x03 // 00_0011
787	# define OPCOD_L_OR 0x04 // 00_0100
788	# define OPCOD_L_XOR 0x05 // 00_0101
789	# define OPCOD_L_CMOV 0x0e // 00_1110
790	# define OPCOD_L_FF1 0x0f // 00_1111
791	# define OPCOD_L_FL1 0x1f // 01_1111
792	# define OPCOD_L_MUL 0x36 // 11_0110
793	# define OPCOD_L_DIV 0x39 // 11_1001
794	# define OPCOD_L_DIVU 0x3a // 11_1010
795	# define OPCOD_L_MULU 0x3b // 11_1011
796
797	# define OPCOD_11 0x8 // 1000 // Instruction Shift/Rotate with register
798	# define OPCOD_12 0xc // 1100 // Instructions extend
799	# define OPCOD_13 0xd // 1101 // Instructions extend (64b)
800
801	// OPCOD_4 instructions - [25:21] Instructions "set flag" with register
802	# define OPCOD_L_SFEQ 0x00 // 00000
803	# define OPCOD_L_SFNE 0x01 // 00001
804	# define OPCOD_L_SFGTU 0x02 // 00010
805	# define OPCOD_L_SFGEU 0x03 // 00011
806	# define OPCOD_L_SFLTU 0x04 // 00100
807	# define OPCOD_L_SFLEU 0x05 // 00101
808	# define OPCOD_L_SFGTS 0x0a // 01010
809	# define OPCOD_L_SFGES 0x0b // 01011
810	# define OPCOD_L_SFLTS 0x0c // 01100
811	# define OPCOD_L_SFLES 0x0d // 01101
812
813	// OPCOD_5 instructions - [25:21] Instructions "set flag" with immediat
814	# define OPCOD_L_SFEQI 0x00 // 00000
815	# define OPCOD_L_SFNEI 0x01 // 00001
816	# define OPCOD_L_SFGTUI 0x02 // 00010
817	# define OPCOD_L_SFGEUI 0x03 // 00011
818	# define OPCOD_L_SFLTUI 0x04 // 00100
819	# define OPCOD_L_SFLEUI 0x05 // 00101
820	# define OPCOD_L_SFGTSI 0x0a // 01010
821	# define OPCOD_L_SFGESI 0x0b // 01011
822	# define OPCOD_L_SFLTSI 0x0c // 01100
823	# define OPCOD_L_SFLESI 0x0d // 01101
824
825	// OPCOD_6 instructions - [7:6] Instruction Shift/Rotate with immediat
826	# define OPCOD_L_SLLI 0x0 // 00
827	# define OPCOD_L_SRLI 0x1 // 01
828	# define OPCOD_L_SRAI 0x2 // 10
829	# define OPCOD_L_RORI 0x3 // 11
830
831	// OPCOD_7 instructions - [3:0] Instructions multiply with HI-LO
832	# define OPCOD_L_MAC 0x1 // 0001
833	# define OPCOD_L_MSB 0x2 // 0010
834
835	// OPCOD_8 instructions - [17] Instructions acces at HI-LO
836	# define OPCOD_L_MOVHI 0x0 // 0
837	# define OPCOD_L_MACRC 0x1 // 1
838
839	// OPCOD_9 instructions - [25:23] Instruction special
840	# define OPCOD_L_SYS 0x0 // 000
841	# define OPCOD_L_TRAP 0x2 // 010
842	# define OPCOD_L_MSYNC 0x4 // 100
843	# define OPCOD_L_PSYNC 0x5 // 101
844	# define OPCOD_L_CSYNC 0x6 // 110
845
846	// OPCOD_10 instructions - [25:24] Instruction no operation
847	# define OPCOD_L_NOP 0x1 // 01
848
849	// OPCOD_11 instructions - [7:6] Instruction Shift/Rotate with register
850	# define OPCOD_L_SLL 0x0 // 00
851	# define OPCOD_L_SRL 0x1 // 01
852	# define OPCOD_L_SRA 0x2 // 10
853	# define OPCOD_L_ROR 0x3 // 11
854
855	// OPCOD_12 instructions - [9:6] Instructions extend
856	# define OPCOD_L_EXTHS 0x0 // 0000
857	# define OPCOD_L_EXTHZ 0x2 // 0010
858	# define OPCOD_L_EXTBS 0x1 // 0001
859	# define OPCOD_L_EXTBZ 0x3 // 0011
860
861	// OPCOD_13 instructions - [9:6] Instructions extend (64b)
862	# define OPCOD_L_EXTWS 0x0 // 0000
863	# define OPCOD_L_EXTWZ 0x1 // 0001
864
865	/*
866
867	//--------------------------------------------------[ destination ]-----
868	#define _size_destination1 4
869
870	#define cst_DESTINATION1_NONE 0x0
871	#define mask_DESTINATION1_GPR 0x1
872	#define mask_DESTINATION1_MEMORY 0x2
873	#define mask_DESTINATION1_SPR 0x4
874	#define mask_DESTINATION1_MAC_UNIT 0x8
875
876	#define _size_destination2 3
877
878	#define cst_DESTINATION2_NONE 0x0
879	#define mask_DESTINATION2_COMMIT 0x1
880	#define mask_DESTINATION2_MEMORY 0x2
881	#define mask_DESTINATION2_SPR 0x4
882
883	//----------------------------------------------------[ exec_flag ]-----
884	#define _size_exec_flag 2
885
886	#define mask_EXEC_FLAG_NONE 0x1
887	#define mask_EXEC_FLAG_CARRY 0x1
888	#define mask_EXEC_FLAG_FLAG 0x1
889	#define mask_EXEC_FLAG_OVERFLOW 0x2
890
891	//---------------------------------------------------[ exec_excep ]-----
892	#define _size_exec_excep 1
893
894	#define mask_EXEC_EXCEP_NONE 0x0
895	#define mask_EXEC_EXCEP_RANGE 0x1
896
897	//----------------------------------------------------[ Condition ]-----
898	#define _size_condition 3
899
900	#define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump)
901	#define mask_CONDITION_CONDITIONAL 0x2
902	#define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear
903	#define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set
904	#define mask_CONDITION_REG 0x4 // Branch if a register is read
905	#define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer
906
907	*/
908
909	/*
910	#define M_CPU_SIZE_INST 32
911
912	//----------------------------------------------------
913	// Exception type
914	//----------------------------------------------------
915
916	#define M_CPU_LOG2_NB_EXCP 5
917	#define M_CPU_NB_EXCP 32
918
919	#define EXCP_NO 0x00 // none exception
920	#define EXCP_RESET 0x01 // software or hardware reset
921	#define EXCP_BERR 0x02 // Access at a invalid physical adress
922	#define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables
923	#define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables
924	#define EXCP_TICK_TIMER 0x05 // Tick timer interruption
925	#define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned
926	#define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented)
927	#define EXCP_IRQ 0x08 // External interruption
928	#define EXCP_D_TLB 0x09 // DTLB miss
929	#define EXCP_I_TLB 0x0a // ITLB miss
930	#define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context
931	#define EXCP_SYSCALL 0x0c // System Call
932	#define EXCP_FP 0x0d // Caused by a floating instruction
933	#define EXCP_TRAP 0x0e // L.trap or debug unit
934	#define EXCP_RES0 0x0f // Reserved for a futur usage
935	#define EXCP_RES1 0x10 // Reserved for a futur usage
936	#define EXCP_RES2 0x11 // Reserved for a futur usage
937	#define EXCP_RES3 0x12 // Reserved for a futur usage
938	#define EXCP_RES4 0x13 // Reserved for a futur usage
939	#define EXCP_RES5 0x14 // Reserved for a futur usage
940	#define EXCP_RES6 0x15 // Reserved for implemented specific exceptions
941	#define EXCP_RES7 0x16 // Reserved for implemented specific exceptions
942	#define EXCP_RES8 0x17 // Reserved for implemented specific exceptions
943	#define EXCP_RES9 0x18 // Reserved for implemented specific exceptions
944	#define EXCP_CUST0 0x19 // Reserved for custom exceptions
945	#define EXCP_CUST1 0x1a // Reserved for custom exceptions
946	#define EXCP_CUST2 0x1b // Reserved for custom exceptions
947	#define EXCP_CUST3 0x1c // Reserved for custom exceptions
948	#define EXCP_CUST4 0x1d // Reserved for custom exceptions
949	#define EXCP_CUST5 0x1e // Reserved for custom exceptions
950	#define EXCP_CUST6 0x1f // Reserved for custom exceptions
951
952	//----------------------------------------------------
953	// Flags
954	//----------------------------------------------------
955
956	#define M_CPU_NB_FLAG 3
957
958	// Integer flags
959	#define FLAG_F 0x1 // Conditionnal branch flag
960	#define FLAG_CY 0x2 // Carry was produced by last arithmétic operation
961	#define FLAG_OV 0x4 // Overflow occured during last arithmetic operation
962
963	// Floating flags
964	#define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation
965	#define FLAG_UNF 0x008 // Underflow flags
966	#define FLAG_SNF 0x010 // Result SNAN
967	#define FLAG_QNF 0x020 // Result QNAN
968	#define FLAG_ZF 0x040 // Result is nul
969	#define FLAG_IXF 0x080 // Result is inexact
970	#define FLAG_IVF 0x100 // Result is invalid
971	#define FLAG_INF 0x200 // Result is infinite
972	#define FLAG_DZF 0x400 // Division by zero
973
974	// Position of flag in "rename register SR" (NOT IN "SR")
975	#define FLAG_POS_F 0x0 // Conditionnal branch flag
976	#define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation
977	#define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation
978
979	//----------------------------------------------------
980	// Instruction type
981	//----------------------------------------------------
982
983	#define M_CPU_LOG2_NB_TYPE 4
984
985	#define TYPE_NOP 0x0
986	#define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...)
987	#define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...)
988	#define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO
989	#define TYPE_J 0x4 // Branch instruction
990	#define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr
991	#define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr
992	#define TYPE_SPECIAL 0x7 // Instruction execute in decode stage
993	#define TYPE_CUSTOM 0x8 // Instruction Custom
994
995	#define TYPE_LOAD_Z 0x9 // Load access (extended by zero)
996	#define TYPE_LOAD_S 0xa // Load access (sign extended)
997	#define TYPE_STORE 0xc // Store access
998
999	//----------------------------------------------------
1000	// Condition to branch
1001	//----------------------------------------------------
1002
1003	#define M_CPU_LOG2_NB_COND 4
1004
1005	#define COND_NONE 0x0 // None condition (jump)
1006	#define COND_F 0x2 // Branch if Flag is set
1007	#define COND_NF 0x3 // Branch if Flag is clear
1008	#define COND_REG 0x4 // Branch if a register is read
1009	#define COND_STACK 0x8 // Branch with pop in stack pointer
1010
1011	//----------------------------------------------------
1012	// Event : State and Type
1013	//----------------------------------------------------
1014
1015	#define EVENT_STATE_NO_EVENT 0 // no event : current case
1016	#define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event
1017	#define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context)
1018	#define EVENT_STATE_END 3 // CPU can continue
1019
1020	#define EVENT_TYPE_MISS 0 // miss of speculation
1021	#define EVENT_TYPE_EXCP 1 // exception or interruption occure
1022
1023	// SPEC? TAKE?
1024	#define BRANCH_STATE_NONE 0 // 0 0
1025	#define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal
1026	#define BRANCH_STATE_SPEC_NTAKE 2 // 1 0
1027	#define BRANCH_STATE_SPEC_TAKE 3 // 1 1
1028
1029	//----------------------------------------------------
1030	// Name to particular register
1031	//----------------------------------------------------
1032
1033	//~~~~~~~~~~~~~~~~~~~~~~~~~~
1034	// GENERAL PURPOSE REGISTER
1035	//~~~~~~~~~~~~~~~~~~~~~~~~~~
1036	#define M_CPU_LOG2_NB_GPR_LOG 5
1037	#define M_CPU_NB_GPR_LOG (1<<M_CPU_LOG2_NB_GPR_LOG)
1038
1039	#define GPR_LOG_LR 0x09 // Link register
1040	#define REG_PHY_SR 0x00 // Status register
1041
1042	//~~~~~~~~~~~~~~~~~~~~~~~~~~
1043	// SPECIAL PURPOSE REGISTER
1044	//~~~~~~~~~~~~~~~~~~~~~~~~~~
1045	#define M_CPU_LOG2_NB_SPR_LOG 1
1046	#define M_CPU_NB_SPR_LOG (1<<M_CPU_LOG2_NB_SPR_LOG)
1047	#define M_CPU_SPR_SIZE_DATA 2 // Size of the most great register
1048
1049	#define SPR_LOG_SR_F 0x00 // Status register bit F (size = 1)
1050	#define SPR_LOG_SR_CY_OV 0x01 // Status register bit overflow and carry (size = 2)
1051	//#define SPR_LOG_SR_LO 0x02 // MAC LSB (size = 32)
1052	//#define SPR_LOG_SR_HI 0x03 // MAC MSB (size = 32)
1053	*/
1054
1055	/*
1056	*/
1057
1058	}; // end namespace behavioural
1059	}; // end namespace morpheo
1060
1061	#endif

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