1 | #include "Behavioural/include/SPR_access_mode.h" |
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2 | |
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3 | namespace morpheo { |
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4 | namespace behavioural { |
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5 | |
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6 | void SPR_access_mode::implement_group (uint32_t num_group, uint32_t nb_reg ) |
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7 | { |
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8 | if (_spr_generic[num_group] != NULL) |
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9 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group."); |
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10 | |
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11 | _max_register_by_group[num_group] = nb_reg; |
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12 | _spr_generic [num_group] = new spr_access_mode_t [nb_reg]; |
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13 | } |
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14 | |
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15 | uint32_t SPR_access_mode::implement_group (uint32_t num_group) |
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16 | { |
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17 | if (_spr_generic[num_group] != NULL) |
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18 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "implement more once a group."); |
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19 | |
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20 | switch (num_group) |
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21 | { |
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22 | case GROUP_SYSTEM_AND_CONTROL : |
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23 | { |
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24 | implement_group(GROUP_SYSTEM_AND_CONTROL ,NB_REG_GROUP_SYSTEM_AND_CONTROL ); |
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25 | |
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26 | for (uint32_t i=0 ; i<=8 ; i++) |
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27 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_ONLY; |
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28 | for (uint32_t i=16; i<=18; i++) |
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29 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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30 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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31 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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32 | |
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33 | const uint32_t nb_shadow = 1; |
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34 | |
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35 | for (uint32_t i=32; i<=32+nb_shadow; i++) |
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36 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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37 | for (uint32_t i=48; i<=48+nb_shadow; i++) |
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38 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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39 | for (uint32_t i=64; i<=64+nb_shadow; i++) |
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40 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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41 | for (uint32_t i=1024; i<=1024+32*nb_shadow; i++) |
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42 | _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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43 | |
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44 | break; |
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45 | } |
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46 | case GROUP_DMMU : |
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47 | { |
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48 | implement_group(GROUP_DMMU ,NB_REG_GROUP_DMMU ); |
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49 | |
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50 | for (uint32_t i=0; i<=2; i++) |
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51 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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52 | _spr_generic [GROUP_DMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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53 | for (uint32_t i=4; i<=11; i++) |
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54 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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55 | for (uint32_t i=512; i<=1535; i++) |
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56 | _spr_generic [GROUP_DMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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57 | |
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58 | break; |
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59 | } |
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60 | case GROUP_IMMU : |
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61 | { |
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62 | implement_group(GROUP_IMMU ,NB_REG_GROUP_IMMU ); |
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63 | |
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64 | for (uint32_t i=0; i<=2; i++) |
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65 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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66 | _spr_generic [GROUP_IMMU ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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67 | for (uint32_t i=4; i<=11; i++) |
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68 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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69 | for (uint32_t i=512; i<=1536; i++) |
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70 | _spr_generic [GROUP_IMMU ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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71 | |
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72 | break; |
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73 | } |
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74 | case GROUP_DCACHE : |
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75 | { |
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76 | implement_group(GROUP_DCACHE ,NB_REG_GROUP_DCACHE ); |
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77 | |
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78 | _spr_generic [GROUP_DCACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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79 | for (uint32_t i=0; i<=5; i++) |
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80 | { |
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81 | _spr_generic [GROUP_DCACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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82 | _spr_generic [GROUP_DCACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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83 | } |
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84 | _spr_generic [GROUP_DCACHE ][ 3]._user_access_mode = SPR_ACCESS_MODE_NONE; |
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85 | |
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86 | break; |
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87 | } |
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88 | case GROUP_ICACHE : |
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89 | { |
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90 | implement_group(GROUP_ICACHE ,NB_REG_GROUP_ICACHE ); |
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91 | |
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92 | _spr_generic [GROUP_ICACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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93 | for (uint32_t i=0; i<=3; i++) |
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94 | { |
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95 | _spr_generic [GROUP_ICACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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96 | _spr_generic [GROUP_ICACHE ][ i]._user_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; |
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97 | } |
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98 | _spr_generic [GROUP_ICACHE ][ 2]._user_access_mode = SPR_ACCESS_MODE_NONE; |
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99 | |
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100 | break; |
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101 | } |
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102 | case GROUP_MAC : |
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103 | { |
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104 | implement_group(GROUP_MAC ,NB_REG_GROUP_MAC ); |
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105 | |
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106 | for (uint32_t i=1; i<=2; i++) |
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107 | { |
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108 | _spr_generic [GROUP_MAC ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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109 | _spr_generic [GROUP_MAC ][ i]._user_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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110 | } |
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111 | |
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112 | break; |
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113 | } |
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114 | case GROUP_DEBUG : |
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115 | { |
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116 | implement_group(GROUP_DEBUG ,NB_REG_GROUP_DEBUG ); |
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117 | |
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118 | for (uint32_t i=0; i<=21; i++) |
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119 | _spr_generic [GROUP_DEBUG ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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120 | |
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121 | break; |
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122 | } |
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123 | case GROUP_PERFORMANCE_COUNTER : |
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124 | { |
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125 | implement_group(GROUP_PERFORMANCE_COUNTER ,NB_REG_GROUP_PERFORMANCE_COUNTER ); |
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126 | |
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127 | for (uint32_t i=0; i<=7; i++) |
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128 | { |
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129 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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130 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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131 | } |
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132 | for (uint32_t i=8; i<=15; i++) |
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133 | _spr_generic [GROUP_PERFORMANCE_COUNTER][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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134 | |
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135 | break; |
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136 | } |
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137 | case GROUP_POWER_MANAGEMENT : |
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138 | { |
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139 | implement_group(GROUP_POWER_MANAGEMENT ,NB_REG_GROUP_POWER_MANAGEMENT ); |
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140 | |
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141 | _spr_generic [GROUP_POWER_MANAGEMENT ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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142 | |
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143 | break; |
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144 | } |
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145 | case GROUP_PIC : |
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146 | { |
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147 | implement_group(GROUP_PIC ,NB_REG_GROUP_PIC ); |
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148 | |
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149 | _spr_generic [GROUP_PIC ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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150 | _spr_generic [GROUP_PIC ][ 2]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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151 | |
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152 | break; |
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153 | } |
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154 | case GROUP_TICK_TIMER : |
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155 | { |
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156 | implement_group(GROUP_TICK_TIMER ,NB_REG_GROUP_TICK_TIMER ); |
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157 | |
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158 | _spr_generic [GROUP_TICK_TIMER ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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159 | _spr_generic [GROUP_TICK_TIMER ][ 1]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; |
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160 | _spr_generic [GROUP_TICK_TIMER ][ 1]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; |
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161 | |
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162 | break; |
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163 | } |
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164 | case GROUP_FLOATING_POINT : |
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165 | { |
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166 | implement_group(GROUP_FLOATING_POINT ,NB_REG_GROUP_FLOATING_POINT ); |
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167 | break; |
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168 | } |
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169 | case GROUP_RESERVED_1 : |
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170 | case GROUP_RESERVED_2 : |
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171 | case GROUP_RESERVED_3 : |
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172 | case GROUP_RESERVED_4 : |
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173 | case GROUP_RESERVED_5 : |
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174 | case GROUP_RESERVED_6 : |
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175 | case GROUP_RESERVED_7 : |
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176 | case GROUP_RESERVED_8 : |
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177 | case GROUP_RESERVED_9 : |
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178 | case GROUP_RESERVED_10 : |
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179 | case GROUP_RESERVED_11 : |
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180 | case GROUP_RESERVED_12 : |
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181 | { |
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182 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a reserved group."); |
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183 | break; |
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184 | } |
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185 | case GROUP_CUSTOM_1 : |
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186 | case GROUP_CUSTOM_2 : |
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187 | case GROUP_CUSTOM_3 : |
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188 | case GROUP_CUSTOM_4 : |
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189 | case GROUP_CUSTOM_5 : |
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190 | case GROUP_CUSTOM_6 : |
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191 | case GROUP_CUSTOM_7 : |
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192 | case GROUP_CUSTOM_8 : |
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193 | { |
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194 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a custom group."); |
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195 | break; |
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196 | } |
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197 | default : |
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198 | { |
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199 | throw ERRORMORPHEO("SPR_access_mode::implement_group", "group number is invalid : it's a unknow group."); |
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200 | break; |
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201 | } |
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202 | } |
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203 | |
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204 | return _max_register_by_group[num_group]; |
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205 | } |
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206 | |
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207 | }; // end namespace behavioural |
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208 | }; // end namespace morpheo |
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209 | |
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