source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/CACHE_pipeline.fig @ 63

#FIG 3.2
Landscape
Center
Inches
Letter  
100.00
Single
-2
1200 2
6 4500 5400 5700 5850
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5100 5400 5100 5850 4500 5850 4500 5400 5100 5400
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5700 5400 5700 5850 5100 5850 5100 5400 5700 5400
4 1 0 50 -1 0 8 0.0000 0 75 345 4800 5550 dcache\001
4 1 0 50 -1 0 8 0.0000 0 105 375 4800 5775 request\001
4 1 0 50 -1 0 8 0.0000 0 75 345 5400 5550 dcache\001
4 1 0 50 -1 0 8 0.0000 0 90 375 5400 5775 respons\001
-6
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5100 4200 5100 4650 4500 4650 4500 4200 5100 4200
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5100 4800 5100 5250 4500 5250 4500 4800 5100 4800
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5700 4800 5700 5250 5100 5250 5100 4800 5700 4800
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5100 3600 5100 4050 4500 4050 4500 3600 5100 3600
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5700 4200 5700 4650 5100 4650 5100 4200 5700 4200
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         6900 4200 6900 4650 5700 4650 5700 4200 6900 4200
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         7500 4200 7500 4650 6900 4650 6900 4200 7500 4200
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5700 3600 5700 4050 5100 4050 5100 3600 5700 3600
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         6900 3600 6900 4050 5700 4050 5700 3600 6900 3600
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         8100 3600 8100 4050 6900 4050 6900 3600 8100 3600
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         8700 3600 8700 4050 8100 4050 8100 3600 8700 3600
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5100 3000 5100 3450 4500 3450 4500 3000 5100 3000
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         5700 3000 5700 3450 5100 3450 5100 3000 5700 3000
2 4 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 5
         8100 4200 8100 4650 7500 4650 7500 4200 8100 4200
4 2 0 50 -1 0 8 0.0000 0 90 525 4200 3300 Read - Hit\001
4 2 0 50 -1 0 8 0.0000 0 90 600 4200 3900 Read - Miss\001
4 1 0 50 -1 0 8 0.0000 0 75 345 4800 4350 dcache\001
4 1 0 50 -1 0 8 0.0000 0 105 375 4800 4575 request\001
4 2 0 50 -1 0 8 0.0000 0 90 570 4200 4350 Write - Hit\001
4 2 0 50 -1 0 8 0.0000 0 90 645 4200 4575 Write - Miss\001
4 2 0 50 -1 0 8 0.0000 0 90 495 4200 4950 Invalidate\001
4 2 0 50 -1 0 8 0.0000 0 75 285 4200 5175 Flush\001
4 1 0 50 -1 0 8 0.0000 0 75 345 4800 4950 dcache\001
4 1 0 50 -1 0 8 0.0000 0 105 375 4800 5175 request\001
4 2 0 50 -1 0 8 0.0000 0 75 255 4200 5550 Lock\001
4 2 0 50 -1 0 8 0.0000 0 75 450 4200 5775 Prefetch\001
4 1 0 50 -1 0 8 0.0000 0 75 345 5400 4950 dcache\001
4 1 0 50 -1 0 8 0.0000 0 90 375 5400 5175 respons\001
4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3750 dcache\001
4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3975 request\001
4 1 0 50 -1 0 8 0.0000 0 75 225 5400 4350 VCI\001
4 1 0 50 -1 0 8 0.0000 0 105 375 5400 4575 request\001
4 1 0 50 -1 0 8 0.0000 0 90 750 6300 4425 memory access\001
4 1 0 50 -1 0 8 0.0000 0 75 225 7200 4350 VCI\001
4 1 0 50 -1 0 8 0.0000 0 90 375 7200 4575 respons\001
4 1 0 50 -1 0 8 0.0000 0 75 225 5400 3750 VCI\001
4 1 0 50 -1 0 8 0.0000 0 105 375 5400 3975 request\001
4 1 0 50 -1 0 8 0.0000 0 90 750 6300 3825 memory access\001
4 1 0 50 -1 0 8 0.0000 0 75 225 7500 3750 VCI\001
4 1 0 50 -1 0 8 0.0000 0 90 375 7500 3975 respons\001
4 1 0 50 -1 0 8 0.0000 0 75 345 8400 3750 dcache\001
4 1 0 50 -1 0 8 0.0000 0 90 375 8400 3975 respons\001
4 1 0 50 -1 0 8 0.0000 0 75 345 4800 3150 dcache\001
4 1 0 50 -1 0 8 0.0000 0 105 375 4800 3375 request\001
4 1 0 50 -1 0 8 0.0000 0 75 345 5400 3150 dcache\001
4 1 0 50 -1 0 8 0.0000 0 90 375 5400 3375 respons\001
4 1 0 50 -1 0 8 0.0000 0 75 345 7800 4350 dcache\001
4 1 0 50 -1 0 8 0.0000 0 90 375 7800 4575 respons\001