source: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig @ 88

#FIG 3.2
Landscape
Center
Inches
Letter  
100.00
Single
-2
1200 2
6 900 -1500 2100 -750
6 900 -1500 2100 -1200
2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5
         2100 -1200 900 -1200 900 -1500 2100 -1500 2100 -1200
4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -1350 D\351but\001
-6
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         1500 -1200 1500 -750
-6
1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525
1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850
1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 375 600 225 1500 375 2100 150
1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950
2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         1500 825 2250 1050
2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         750 1500 1350 1950
2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         2250 1500 1650 1950
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
        3 0 1.00 60.00 120.00
         900 2175 0 2175 0 900 450 900 450 1050
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         1500 2400 1500 2850
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         1500 3300 1500 3750
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
        3 0 1.00 60.00 120.00
         -150 750 750 750 750 1050
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
        3 0 1.00 60.00 120.00
         -750 525 -750 -975 1200 -975 1200 -750
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
        3 0 1.00 60.00 120.00
         900 3075 -750 3075 -750 975
2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5
         2100 4050 900 4050 900 3750 2100 3750 2100 4050
2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
         1350 1500 150 1500 150 1050 1350 1050 1350 1500
2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
         2850 1500 1650 1500 1650 1050 2850 1050 2850 1500
2 1 0 1 0 7 50 -1 20 0.000 0 0 7 1 0 2
        3 0 1.00 60.00 120.00
         1500 825 1050 1050
2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 2
         1500 600 1500 825
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
        3 0 1.00 60.00 120.00
         2100 375 2250 375 2250 -900 1800 -900 1800 -750
2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
        3 0 1.00 60.00 120.00
         1500 -300 1500 150
2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5
         2100 -300 900 -300 900 -750 2100 -750 2100 -300
4 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001
4 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001
4 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001
4 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001
4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001
4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001
4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001
4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001
4 0 0 51 -1 0 8 0.0000 0 75 120 1575 750 ok\001
4 1 0 50 -1 2 8 0.0000 0 75 240 1500 375 Test\001
4 0 0 51 -1 0 8 0.0000 0 75 120 2025 225 ko\001
4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001
4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001
4 2 0 51 -1 0 8 0.0000 0 75 120 825 2025 ko\001
4 1 0 50 -1 2 8 0.0000 0 75 375 750 1425 VHDL\001
4 1 0 50 -1 2 8 0.0000 0 75 375 2250 1425 VHDL\001
4 1 0 50 -1 2 8 0.0000 0 90 615 2250 1200 TestBench \001
4 1 0 50 -1 2 8 0.0000 0 105 465 1500 -375 SystemC\001
4 1 0 50 -1 2 8 0.0000 0 105 450 750 1200 Mod\350le \001
4 1 0 50 -1 2 8 0.0000 0 105 450 1500 -600 Mod\350le \001