Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig
r81 r88 8 8 -2 9 9 1200 2 10 6 -1425 -600 2850 4050 10 6 900 -1500 2100 -750 11 6 900 -1500 2100 -1200 12 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 13 2100 -1200 900 -1200 900 -1500 2100 -1500 2100 -1200 14 4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -1350 D\351but\001 15 -6 16 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 17 3 0 1.00 60.00 120.00 18 1500 -1200 1500 -750 19 -6 11 20 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525 21 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850 22 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 375 600 225 1500 375 2100 150 12 23 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950 13 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 285014 24 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 15 25 3 0 1.00 60.00 120.00 16 1650 600 2250 1050 17 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 18 3 0 1.00 60.00 120.00 19 1350 600 1050 1050 26 1500 825 2250 1050 20 27 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 21 28 3 0 1.00 60.00 120.00 … … 38 45 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 39 46 3 0 1.00 60.00 120.00 40 -750 525 -750 - 75 1200 -75 1200 15047 -750 525 -750 -975 1200 -975 1200 -750 41 48 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 42 49 3 0 1.00 60.00 120.00 43 50 900 3075 -750 3075 -750 975 44 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 245 3 0 1.00 60.00 120.0046 1500 -300 1500 15047 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 548 2100 -300 900 -300 900 -600 2100 -600 2100 -30049 51 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 50 52 2100 4050 900 4050 900 3750 2100 3750 2100 4050 51 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 552 2100 600 900 600 900 150 2100 150 2100 60053 53 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 54 54 1350 1500 150 1500 150 1050 1350 1050 1350 1500 55 55 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 56 56 2850 1500 1650 1500 1650 1050 2850 1050 2850 1500 57 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 58 4 1 0 50 -1 2 8 0.0000 0 90 990 2250 1275 TestBench VHDL\001 59 4 1 0 50 -1 2 8 0.0000 0 105 1005 750 1275 G\351n\351rateur VHDL\001 60 4 1 0 50 -1 2 8 0.0000 0 105 465 1500 375 SystemC\001 61 4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 62 4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 63 4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -450 D\351but\001 64 4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 65 4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 66 -6 57 2 1 0 1 0 7 50 -1 20 0.000 0 0 7 1 0 2 58 3 0 1.00 60.00 120.00 59 1500 825 1050 1050 60 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 2 61 1500 600 1500 825 62 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 63 3 0 1.00 60.00 120.00 64 2100 375 2250 375 2250 -900 1800 -900 1800 -750 65 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 66 3 0 1.00 60.00 120.00 67 1500 -300 1500 150 68 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 69 2100 -300 900 -300 900 -750 2100 -750 2100 -300 67 70 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001 68 71 4 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001 69 72 4 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001 70 73 4 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001 71 4 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001 74 4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 75 4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 76 4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 77 4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 78 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 750 ok\001 79 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 375 Test\001 80 4 0 0 51 -1 0 8 0.0000 0 75 120 2025 225 ko\001 72 81 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001 82 4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 83 4 2 0 51 -1 0 8 0.0000 0 75 120 825 2025 ko\001 84 4 1 0 50 -1 2 8 0.0000 0 75 375 750 1425 VHDL\001 85 4 1 0 50 -1 2 8 0.0000 0 75 375 2250 1425 VHDL\001 86 4 1 0 50 -1 2 8 0.0000 0 90 615 2250 1200 TestBench \001 87 4 1 0 50 -1 2 8 0.0000 0 105 465 1500 -375 SystemC\001 88 4 1 0 50 -1 2 8 0.0000 0 105 450 750 1200 Mod\350le \001 89 4 1 0 50 -1 2 8 0.0000 0 105 450 1500 -600 Mod\350le \001
Note: See TracChangeset
for help on using the changeset viewer.