[88] | 1 | /* |
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| 2 | * $Id: Morpheo_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #include "TopLevel/include/Morpheo.h" |
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| 9 | #include "Behavioural/include/Allocation.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | |
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| 13 | #undef FUNCTION |
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| 14 | #define FUNCTION "Morpheo::allocation" |
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| 15 | void Morpheo::allocation |
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| 16 | ( |
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| 17 | #ifdef STATISTICS |
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| 18 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 19 | #else |
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| 20 | void |
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| 21 | #endif |
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| 22 | ) |
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| 23 | { |
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| 24 | log_begin(Morpheo,FUNCTION); |
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| 25 | |
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| 26 | _component = new behavioural::Component (_usage); |
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| 27 | |
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| 28 | behavioural::Entity * entity = _component->set_entity (_name |
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| 29 | ,"Morpheo" |
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| 30 | #ifdef POSITION |
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| 31 | ,COMBINATORY |
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| 32 | #endif |
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| 33 | ); |
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| 34 | |
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| 35 | _interfaces = entity->set_interfaces(); |
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| 36 | |
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| 37 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 38 | { |
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| 39 | behavioural::Interface * interface = _interfaces->set_interface("" |
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| 40 | #ifdef POSITION |
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| 41 | ,IN |
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| 42 | ,SOUTH, |
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| 43 | "Generalist interface" |
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| 44 | #endif |
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| 45 | ); |
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| 46 | |
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| 47 | in_CLOCK = interface->set_signal_clk ("clock" ,1, behavioural::CLOCK_VHDL_YES); |
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| 48 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, behavioural::RESET_VHDL_YES); |
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| 49 | } |
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| 50 | |
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| 51 | |
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| 52 | // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 53 | { |
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[112] | 54 | ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port); |
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[88] | 55 | |
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| 56 | ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL); |
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| 57 | ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,behavioural::ACK); |
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| 58 | ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Ticache_context_t ,_size_icache_thread_id); |
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| 59 | ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Ticache_packet_t ,_size_icache_packet_id); |
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| 60 | ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address ); |
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| 61 | ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type ); |
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[112] | 62 | |
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| 63 | ALLOC1_INTERFACE_END(_nb_icache_port); |
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[88] | 64 | } |
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| 65 | |
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| 66 | // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 67 | { |
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[112] | 68 | ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port); |
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[88] | 69 | |
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| 70 | ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL); |
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| 71 | ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,behavioural::ACK); |
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| 72 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Ticache_context_t ,_size_icache_thread_id); |
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| 73 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id); |
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| 74 | ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error); |
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[112] | 75 | |
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| 76 | ALLOC1_INTERFACE_END(_nb_icache_port); |
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[88] | 77 | } |
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| 78 | { |
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[112] | 79 | ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]); |
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[88] | 80 | |
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| 81 | _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]); |
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[112] | 82 | |
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| 83 | ALLOC2_INTERFACE_END(_nb_icache_port,_icache_nb_instruction[it1]); |
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[88] | 84 | } |
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| 85 | |
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| 86 | // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 87 | { |
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[112] | 88 | ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port); |
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[88] | 89 | |
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| 90 | ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL); |
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| 91 | ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,behavioural::ACK); |
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| 92 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id); |
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| 93 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id); |
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| 94 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_size_dcache_address); |
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| 95 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data); |
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| 96 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type); |
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[112] | 97 | |
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| 98 | ALLOC1_INTERFACE_END(_nb_dcache_port); |
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[88] | 99 | } |
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| 100 | |
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| 101 | // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 102 | { |
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[112] | 103 | ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port); |
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[88] | 104 | |
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| 105 | ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL); |
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| 106 | ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,behavioural::ACK); |
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| 107 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id); |
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| 108 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id); |
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| 109 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data); |
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| 110 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error); |
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[112] | 111 | |
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| 112 | ALLOC1_INTERFACE_END(_nb_dcache_port); |
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[88] | 113 | } |
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| 114 | |
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| 115 | // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 116 | { |
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[112] | 117 | ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_nb_thread); |
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[88] | 118 | |
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| 119 | ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1); |
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[112] | 120 | |
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| 121 | ALLOC1_INTERFACE_END(_nb_thread); |
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[88] | 122 | } |
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| 123 | |
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| 124 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 125 | |
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| 126 | std::string name; |
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| 127 | |
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| 128 | { |
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| 129 | name = _name+"_core"; |
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| 130 | log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); |
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| 131 | |
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| 132 | _component_core = new morpheo::behavioural::core::Core |
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| 133 | (name.c_str() |
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| 134 | #ifdef STATISTICS |
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| 135 | ,param_statistics |
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| 136 | #endif |
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| 137 | ,_param_core |
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| 138 | ,_usage); |
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| 139 | |
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| 140 | _component->set_component (_component_core->_component |
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| 141 | #ifdef POSITION |
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| 142 | , 50, 50, 10, 10 |
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| 143 | #endif |
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| 144 | ); |
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| 145 | } |
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| 146 | |
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| 147 | // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 148 | std::string src,dest; |
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| 149 | |
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| 150 | // =================================================================== |
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| 151 | // =====[ core ]====================================================== |
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| 152 | // =================================================================== |
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| 153 | { |
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| 154 | src = _name+"_core"; |
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| 155 | log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); |
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| 156 | |
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| 157 | // ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 158 | { |
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| 159 | dest = _name; |
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| 160 | #ifdef POSITION |
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| 161 | _component->interface_map (src ,"", |
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| 162 | dest,""); |
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| 163 | #endif |
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| 164 | PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); |
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| 165 | PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); |
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| 166 | } |
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| 167 | |
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| 168 | // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 169 | for (uint32_t i=0; i<_nb_icache_port; ++i) |
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| 170 | { |
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| 171 | dest = _name; |
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| 172 | #ifdef POSITION |
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| 173 | _component->interface_map (src ,"icache_req_"+toString(i), |
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| 174 | dest,"icache_req_"+toString(i)); |
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| 175 | #endif |
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| 176 | |
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| 177 | PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" , |
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| 178 | dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" ); |
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| 179 | PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" , |
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| 180 | dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" ); |
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| 181 | if (_have_port_icache_thread_id) |
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| 182 | PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID", |
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| 183 | dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID"); |
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| 184 | if (_have_port_icache_packet_id) |
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| 185 | PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID", |
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| 186 | dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID"); |
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| 187 | PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" , |
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| 188 | dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ); |
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| 189 | PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" , |
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| 190 | dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ); |
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| 191 | } |
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| 192 | |
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| 193 | // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 194 | for (uint32_t i=0; i<_nb_icache_port; ++i) |
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| 195 | { |
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| 196 | dest = _name; |
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| 197 | #ifdef POSITION |
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| 198 | _component->interface_map (src ,"icache_rsp_"+toString(i), |
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| 199 | dest,"icache_rsp_"+toString(i)); |
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| 200 | #endif |
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| 201 | |
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| 202 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" , |
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| 203 | dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" ); |
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| 204 | PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" , |
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| 205 | dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" ); |
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| 206 | if (_have_port_icache_thread_id) |
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| 207 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID", |
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| 208 | dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID"); |
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| 209 | if (_have_port_icache_packet_id) |
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| 210 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID", |
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| 211 | dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID"); |
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| 212 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" , |
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| 213 | dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" ); |
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| 214 | |
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| 215 | for (uint32_t j=0; j<_icache_nb_instruction[i]; ++j) |
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| 216 | { |
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| 217 | dest = _name; |
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| 218 | #ifdef POSITION |
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| 219 | _component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j), |
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| 220 | dest,"icache_rsp_"+toString(i)+"_"+toString(j)); |
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| 221 | #endif |
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| 222 | |
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| 223 | PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION", |
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| 224 | dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION"); |
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| 225 | } |
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| 226 | } |
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| 227 | |
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| 228 | // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 229 | for (uint32_t i=0; i<_nb_dcache_port; ++i) |
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| 230 | { |
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| 231 | dest = _name; |
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| 232 | #ifdef POSITION |
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| 233 | _component->interface_map (src ,"dcache_req_"+toString(i), |
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| 234 | dest,"dcache_req_"+toString(i)); |
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| 235 | #endif |
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| 236 | |
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| 237 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" , |
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| 238 | dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" ); |
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| 239 | PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" , |
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| 240 | dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" ); |
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| 241 | if (_have_port_dcache_thread_id) |
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| 242 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID", |
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| 243 | dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID"); |
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| 244 | if (_have_port_dcache_packet_id) |
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| 245 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID", |
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| 246 | dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID"); |
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| 247 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" , |
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| 248 | dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ); |
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| 249 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" , |
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| 250 | dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ); |
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| 251 | PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" , |
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| 252 | dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ); |
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| 253 | } |
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| 254 | |
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| 255 | // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 256 | for (uint32_t i=0; i<_nb_dcache_port; ++i) |
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| 257 | { |
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| 258 | dest = _name; |
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| 259 | #ifdef POSITION |
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| 260 | _component->interface_map (src ,"dcache_rsp_"+toString(i), |
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| 261 | dest,"dcache_rsp_"+toString(i)); |
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| 262 | #endif |
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| 263 | |
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| 264 | PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" , |
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| 265 | dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" ); |
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| 266 | PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" , |
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| 267 | dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" ); |
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| 268 | if (_have_port_dcache_thread_id) |
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| 269 | PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID", |
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| 270 | dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID"); |
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| 271 | if (_have_port_dcache_packet_id) |
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| 272 | PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID", |
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| 273 | dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID"); |
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| 274 | PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" , |
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| 275 | dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" ); |
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| 276 | PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" , |
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| 277 | dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" ); |
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| 278 | } |
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| 279 | |
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| 280 | // ~~~~~[ Interface "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 281 | for (uint32_t i=0; i<_nb_thread; ++i) |
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| 282 | { |
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| 283 | dest = _name; |
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| 284 | #ifdef POSITION |
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| 285 | _component->interface_map (src ,"interrupt_"+toString(i), |
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| 286 | dest,"interrupt_"+toString(i)); |
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| 287 | #endif |
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| 288 | |
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| 289 | PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE", |
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| 290 | dest, "in_INTERRUPT_"+toString(i)+"_ENABLE"); |
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| 291 | } |
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| 292 | } |
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| 293 | |
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| 294 | |
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| 295 | // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 296 | if (DEBUG_Morpheo == true) |
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| 297 | _component->test_map(); |
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| 298 | |
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| 299 | #ifdef POSITION |
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| 300 | if (usage_is_set(_usage,USE_POSITION)) |
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| 301 | _component->generate_file(); |
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| 302 | #endif |
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| 303 | |
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| 304 | log_end(Morpheo,FUNCTION); |
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| 305 | }; |
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| 306 | }; // end namespace morpheo |
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