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Morpheo_allocation.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
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File size: 13.1 KB

Line
1	/*
2	* $Id: Morpheo_allocation.cpp 145 2010-10-13 18:15:51Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "TopLevel/include/Morpheo.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12
13	#undef FUNCTION
14	#define FUNCTION "Morpheo::allocation"
15	void Morpheo::allocation
16	(
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * param_statistics
19	#else
20	void
21	#endif
22	)
23	{
24	log_begin(Morpheo,FUNCTION);
25
26	// _function_pointer = new behavioural::Function_pointer();
27
28	_component = new behavioural::Component (_usage);
29
30	behavioural::Entity * entity = _component->set_entity (_name
31	,"Morpheo"
32	#ifdef POSITION
33	,COMBINATORY
34	#endif
35	);
36
37	_interfaces = entity->set_interfaces();
38
39	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
40	{
41	behavioural::Interface * interface = _interfaces->set_interface(""
42	#ifdef POSITION
43	,IN
44	,SOUTH,
45	"Generalist interface"
46	#endif
47	);
48
49	in_CLOCK = interface->set_signal_clk ("clock" ,1, behavioural::CLOCK_VHDL_YES);
50	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, behavioural::RESET_VHDL_YES);
51	}
52
53
54	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
55	{
56	ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port);
57
58	ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL);
59	ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,behavioural::ACK);
60	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Ticache_context_t ,_size_icache_thread_id);
61	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Ticache_packet_t ,_size_icache_packet_id);
62	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address );
63	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type );
64
65	ALLOC1_INTERFACE_END(_nb_icache_port);
66	}
67
68	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
69	{
70	ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port);
71
72	ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL);
73	ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,behavioural::ACK);
74	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Ticache_context_t ,_size_icache_thread_id);
75	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id);
76	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error);
77
78	ALLOC1_INTERFACE_END(_nb_icache_port);
79	}
80	{
81	ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]);
82
83	_ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]);
84
85	ALLOC2_INTERFACE_END(_nb_icache_port,_icache_nb_instruction[it1]);
86	}
87
88	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
89	{
90	ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port);
91
92	ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL);
93	ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,behavioural::ACK);
94	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
95	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
96	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_size_dcache_address);
97	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data);
98	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type);
99
100	ALLOC1_INTERFACE_END(_nb_dcache_port);
101	}
102
103	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
104	{
105	ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port);
106
107	ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL);
108	ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,behavioural::ACK);
109	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
110	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
111	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data);
112	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error);
113
114	ALLOC1_INTERFACE_END(_nb_dcache_port);
115	}
116
117	// ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
118	{
119	ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_nb_thread);
120
121	ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1);
122
123	ALLOC1_INTERFACE_END(_nb_thread);
124	}
125
126	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
127
128	std::string name;
129
130	{
131	name = _name+"_core";
132	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
133
134	_component_core = new morpheo::behavioural::core::Core
135	(name.c_str()
136	#ifdef STATISTICS
137	,param_statistics
138	#endif
139	,_param_core
140	,_usage
141	// ,_function_pointer
142	);
143
144	_component->set_component (_component_core->_component
145	#ifdef POSITION
146	, 50, 50, 10, 10
147	#endif
148	);
149	}
150
151	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
152	std::string src,dest;
153
154	// ===================================================================
155	// =====[ core ]======================================================
156	// ===================================================================
157	{
158	src = _name+"_core";
159	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
160
161	// ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
162	{
163	dest = _name;
164	#ifdef POSITION
165	_component->interface_map (src ,"",
166	dest,"");
167	#endif
168	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
169	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
170	}
171
172	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
173	for (uint32_t i=0; i<_nb_icache_port; ++i)
174	{
175	dest = _name;
176	#ifdef POSITION
177	_component->interface_map (src ,"icache_req_"+toString(i),
178	dest,"icache_req_"+toString(i));
179	#endif
180
181	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" ,
182	dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" );
183	PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" ,
184	dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" );
185	if (_have_port_icache_thread_id)
186	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID",
187	dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID");
188	if (_have_port_icache_packet_id)
189	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID",
190	dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID");
191	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ,
192	dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" );
193	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ,
194	dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" );
195	}
196
197	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
198	for (uint32_t i=0; i<_nb_icache_port; ++i)
199	{
200	dest = _name;
201	#ifdef POSITION
202	_component->interface_map (src ,"icache_rsp_"+toString(i),
203	dest,"icache_rsp_"+toString(i));
204	#endif
205
206	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" ,
207	dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" );
208	PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" ,
209	dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" );
210	if (_have_port_icache_thread_id)
211	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID",
212	dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID");
213	if (_have_port_icache_packet_id)
214	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID",
215	dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID");
216	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" ,
217	dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" );
218
219	for (uint32_t j=0; j<_icache_nb_instruction[i]; ++j)
220	{
221	dest = _name;
222	#ifdef POSITION
223	_component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j),
224	dest,"icache_rsp_"+toString(i)+"_"+toString(j));
225	#endif
226
227	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION",
228	dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION");
229	}
230	}
231
232	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
233	for (uint32_t i=0; i<_nb_dcache_port; ++i)
234	{
235	dest = _name;
236	#ifdef POSITION
237	_component->interface_map (src ,"dcache_req_"+toString(i),
238	dest,"dcache_req_"+toString(i));
239	#endif
240
241	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" ,
242	dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" );
243	PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" ,
244	dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" );
245	if (_have_port_dcache_thread_id)
246	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID",
247	dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID");
248	if (_have_port_dcache_packet_id)
249	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID",
250	dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID");
251	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ,
252	dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" );
253	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ,
254	dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" );
255	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ,
256	dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" );
257	}
258
259	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
260	for (uint32_t i=0; i<_nb_dcache_port; ++i)
261	{
262	dest = _name;
263	#ifdef POSITION
264	_component->interface_map (src ,"dcache_rsp_"+toString(i),
265	dest,"dcache_rsp_"+toString(i));
266	#endif
267
268	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" ,
269	dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" );
270	PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" ,
271	dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" );
272	if (_have_port_dcache_thread_id)
273	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID",
274	dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID");
275	if (_have_port_dcache_packet_id)
276	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID",
277	dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID");
278	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" ,
279	dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" );
280	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" ,
281	dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" );
282	}
283
284	// ~~~~~[ Interface "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
285	for (uint32_t i=0; i<_nb_thread; ++i)
286	{
287	dest = _name;
288	#ifdef POSITION
289	_component->interface_map (src ,"interrupt_"+toString(i),
290	dest,"interrupt_"+toString(i));
291	#endif
292
293	PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE",
294	dest, "in_INTERRUPT_"+toString(i)+"_ENABLE");
295	}
296	}
297
298
299	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
300	if (DEBUG_Morpheo == true)
301	_component->test_map();
302
303	#ifdef POSITION
304	if (usage_is_set(_usage,USE_POSITION))
305	_component->generate_file();
306	#endif
307
308	log_end(Morpheo,FUNCTION);
309	};
310	}; // end namespace morpheo

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source: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp @ 145

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