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source: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago
1) Stat_list : fix retire old and new register bug 2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step) 3) Model : add class Model (cf Morpheo.sim) 4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array. 5) Script : add distexe.sh 6) Add Comparator, Multiplier, Divider. But this component are not implemented 7) Software : add Dhrystone
Property svn:keywords set to `Id`
File size: 13.0 KB

Line
1	/*
2	* $Id: Morpheo_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "TopLevel/include/Morpheo.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12
13	#undef FUNCTION
14	#define FUNCTION "Morpheo::allocation"
15	void Morpheo::allocation
16	(
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * param_statistics
19	#else
20	void
21	#endif
22	)
23	{
24	log_begin(Morpheo,FUNCTION);
25
26	_component = new behavioural::Component (_usage);
27
28	behavioural::Entity * entity = _component->set_entity (_name
29	,"Morpheo"
30	#ifdef POSITION
31	,COMBINATORY
32	#endif
33	);
34
35	_interfaces = entity->set_interfaces();
36
37	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
38	{
39	behavioural::Interface * interface = _interfaces->set_interface(""
40	#ifdef POSITION
41	,IN
42	,SOUTH,
43	"Generalist interface"
44	#endif
45	);
46
47	in_CLOCK = interface->set_signal_clk ("clock" ,1, behavioural::CLOCK_VHDL_YES);
48	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, behavioural::RESET_VHDL_YES);
49	}
50
51
52	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
53	{
54	ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port);
55
56	ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL);
57	ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,behavioural::ACK);
58	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Ticache_context_t ,_size_icache_thread_id);
59	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Ticache_packet_t ,_size_icache_packet_id);
60	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address );
61	ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type );
62
63	ALLOC1_INTERFACE_END(_nb_icache_port);
64	}
65
66	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
67	{
68	ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port);
69
70	ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL);
71	ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,behavioural::ACK);
72	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Ticache_context_t ,_size_icache_thread_id);
73	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id);
74	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error);
75
76	ALLOC1_INTERFACE_END(_nb_icache_port);
77	}
78	{
79	ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]);
80
81	_ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]);
82
83	ALLOC2_INTERFACE_END(_nb_icache_port,_icache_nb_instruction[it1]);
84	}
85
86	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
87	{
88	ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port);
89
90	ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL);
91	ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,behavioural::ACK);
92	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
93	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
94	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_size_dcache_address);
95	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data);
96	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type);
97
98	ALLOC1_INTERFACE_END(_nb_dcache_port);
99	}
100
101	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
102	{
103	ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port);
104
105	ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL);
106	ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,behavioural::ACK);
107	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id);
108	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id);
109	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data);
110	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error);
111
112	ALLOC1_INTERFACE_END(_nb_dcache_port);
113	}
114
115	// ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
116	{
117	ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_nb_thread);
118
119	ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1);
120
121	ALLOC1_INTERFACE_END(_nb_thread);
122	}
123
124	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
125
126	std::string name;
127
128	{
129	name = _name+"_core";
130	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
131
132	_component_core = new morpheo::behavioural::core::Core
133	(name.c_str()
134	#ifdef STATISTICS
135	,param_statistics
136	#endif
137	,_param_core
138	,_usage);
139
140	_component->set_component (_component_core->_component
141	#ifdef POSITION
142	, 50, 50, 10, 10
143	#endif
144	);
145	}
146
147	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
148	std::string src,dest;
149
150	// ===================================================================
151	// =====[ core ]======================================================
152	// ===================================================================
153	{
154	src = _name+"_core";
155	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
156
157	// ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
158	{
159	dest = _name;
160	#ifdef POSITION
161	_component->interface_map (src ,"",
162	dest,"");
163	#endif
164	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
165	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
166	}
167
168	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
169	for (uint32_t i=0; i<_nb_icache_port; ++i)
170	{
171	dest = _name;
172	#ifdef POSITION
173	_component->interface_map (src ,"icache_req_"+toString(i),
174	dest,"icache_req_"+toString(i));
175	#endif
176
177	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" ,
178	dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" );
179	PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" ,
180	dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" );
181	if (_have_port_icache_thread_id)
182	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID",
183	dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID");
184	if (_have_port_icache_packet_id)
185	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID",
186	dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID");
187	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ,
188	dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" );
189	PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ,
190	dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" );
191	}
192
193	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
194	for (uint32_t i=0; i<_nb_icache_port; ++i)
195	{
196	dest = _name;
197	#ifdef POSITION
198	_component->interface_map (src ,"icache_rsp_"+toString(i),
199	dest,"icache_rsp_"+toString(i));
200	#endif
201
202	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" ,
203	dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" );
204	PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" ,
205	dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" );
206	if (_have_port_icache_thread_id)
207	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID",
208	dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID");
209	if (_have_port_icache_packet_id)
210	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID",
211	dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID");
212	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" ,
213	dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" );
214
215	for (uint32_t j=0; j<_icache_nb_instruction[i]; ++j)
216	{
217	dest = _name;
218	#ifdef POSITION
219	_component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j),
220	dest,"icache_rsp_"+toString(i)+"_"+toString(j));
221	#endif
222
223	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION",
224	dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION");
225	}
226	}
227
228	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
229	for (uint32_t i=0; i<_nb_dcache_port; ++i)
230	{
231	dest = _name;
232	#ifdef POSITION
233	_component->interface_map (src ,"dcache_req_"+toString(i),
234	dest,"dcache_req_"+toString(i));
235	#endif
236
237	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" ,
238	dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" );
239	PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" ,
240	dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" );
241	if (_have_port_dcache_thread_id)
242	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID",
243	dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID");
244	if (_have_port_dcache_packet_id)
245	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID",
246	dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID");
247	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ,
248	dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" );
249	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ,
250	dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" );
251	PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ,
252	dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" );
253	}
254
255	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
256	for (uint32_t i=0; i<_nb_dcache_port; ++i)
257	{
258	dest = _name;
259	#ifdef POSITION
260	_component->interface_map (src ,"dcache_rsp_"+toString(i),
261	dest,"dcache_rsp_"+toString(i));
262	#endif
263
264	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" ,
265	dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" );
266	PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" ,
267	dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" );
268	if (_have_port_dcache_thread_id)
269	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID",
270	dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID");
271	if (_have_port_dcache_packet_id)
272	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID",
273	dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID");
274	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" ,
275	dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" );
276	PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" ,
277	dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" );
278	}
279
280	// ~~~~~[ Interface "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
281	for (uint32_t i=0; i<_nb_thread; ++i)
282	{
283	dest = _name;
284	#ifdef POSITION
285	_component->interface_map (src ,"interrupt_"+toString(i),
286	dest,"interrupt_"+toString(i));
287	#endif
288
289	PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE",
290	dest, "in_INTERRUPT_"+toString(i)+"_ENABLE");
291	}
292	}
293
294
295	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
296	if (DEBUG_Morpheo == true)
297	_component->test_map();
298
299	#ifdef POSITION
300	if (usage_is_set(_usage,USE_POSITION))
301	_component->generate_file();
302	#endif
303
304	log_end(Morpheo,FUNCTION);
305	};
306	}; // end namespace morpheo

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