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source: trunk/Platforms/Test/src/test.cpp @ 128

Last change on this file since 128 was 124, checked in by rosiere, 15 years ago
1) Add test and configuration 2) Fix Bug 3) Add log file in load store unit 4) Fix Bug in environment
Property svn:keywords set to `Id`
File size: 30.3 KB

Line
1	/*
2	* $Id: test.cpp 124 2009-06-17 12:11:25Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Platforms : Morpheo + Environment
7	*/
8
9	#define CYCLE_MAX 0
10
11	#include "../include/test.h"
12
13	#include "Environment.h"
14	#include "Behavioural/include/Allocation.h"
15	#include "Common/include/Time.h"
16	#include "../../../IPs/systemC/shared/mapping_memory.h"
17	#include "../../../IPs/systemC/processor/Morpheo/Common/include/Test.h"
18
19	using namespace std;
20	using namespace environment;
21	using namespace morpheo;
22
23	int test(string filename_simulator,
24	string filename_generator,
25	string filename_instance ,
26	string filename_software ,
27	uint32_t nb_cache_dedicated,
28	uint32_t nb_cache_shared ,
29	uint32_t cache_size ,
30	uint32_t cache_ratio ,
31	morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void)
32	)
33	{
34	//==============================================================================
35	//===== [ DECLARATION ]=========================================================
36	//==============================================================================
37
38
39	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
40	//~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
41	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
42
43	// 1) Translation
44	if (setlocale (LC_ALL, "") == NULL)
45	{
46	cerr << "Error setlocale." << endl;
47	exit (EXIT_FAILURE);
48	}
49
50	// 2) Morpheo Construction
51	Morpheo * morpheo = new Morpheo
52	("morpheo",
53	filename_simulator,
54	filename_generator,
55	filename_instance ,
56	get_custom_information
57	);
58
59	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
60	//~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
62
63	uint32_t nb_thread = morpheo->_nb_thread;
64	uint32_t nb_entity = 1;
65
66	// Cache access
67	uint32_t * iaccess_nb_context = new uint32_t [nb_entity];
68	uint32_t * iaccess_nb_instruction= new uint32_t [nb_entity];
69	uint32_t * iaccess_nb_packet = new uint32_t [nb_entity];
70	uint32_t * iaccess_size_address = new uint32_t [nb_entity];
71	uint32_t * iaccess_size_data = new uint32_t [nb_entity];
72
73	uint32_t * daccess_nb_context = new uint32_t [nb_entity];
74	uint32_t * daccess_nb_packet = new uint32_t [nb_entity];
75	uint32_t * daccess_size_address = new uint32_t [nb_entity];
76	uint32_t * daccess_size_data = new uint32_t [nb_entity];
77
78	uint32_t * buffer_irsp_size = new uint32_t [nb_entity];
79	uint32_t * buffer_drsp_size = new uint32_t [nb_entity];
80
81	for (uint32_t i=0; i<nb_entity; i++)
82	{
83	iaccess_nb_context [i] = morpheo->_nb_thread;
84	iaccess_nb_instruction [i] = max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port);
85	iaccess_nb_packet [i] = 1<<morpheo->_size_icache_packet_id;
86	iaccess_size_address [i] = morpheo->_size_icache_address;
87	iaccess_size_data [i] = morpheo->_size_icache_instruction;
88
89	daccess_nb_context [i] = morpheo->_nb_thread;
90	daccess_nb_packet [i] = 1<<morpheo->_size_dcache_packet_id;
91	daccess_size_address [i] = morpheo->_size_dcache_address;
92	daccess_size_data [i] = morpheo->_size_dcache_data;
93
94	buffer_irsp_size [i] = 8;
95	buffer_drsp_size [i] = 8;
96	}
97
98	uint32_t cache_nb_line ;
99	uint32_t cache_size_line ;
100	uint32_t cache_size_word ;
101	uint32_t cache_associativity ;
102	uint32_t cache_hit_latence ;
103	uint32_t cache_miss_penality ;
104
105	// Instruction/Data cache
106	uint32_t * icache_nb_level = new uint32_t [nb_entity];
107	uint32_t * icache_nb_port = new uint32_t [nb_entity];
108	uint32_t ** icache_nb_line = new uint32_t * [nb_entity];
109	uint32_t ** icache_size_line = new uint32_t * [nb_entity];
110	uint32_t ** icache_size_word = new uint32_t * [nb_entity];
111	uint32_t ** icache_associativity = new uint32_t * [nb_entity];
112	uint32_t ** icache_hit_latence = new uint32_t * [nb_entity];
113	uint32_t ** icache_miss_penality = new uint32_t * [nb_entity];
114
115	uint32_t * dcache_nb_level = new uint32_t [nb_entity];
116	uint32_t * dcache_nb_port = new uint32_t [nb_entity];
117	uint32_t ** dcache_nb_line = new uint32_t * [nb_entity];
118	uint32_t ** dcache_size_line = new uint32_t * [nb_entity];
119	uint32_t ** dcache_size_word = new uint32_t * [nb_entity];
120	uint32_t ** dcache_associativity = new uint32_t * [nb_entity];
121	uint32_t ** dcache_hit_latence = new uint32_t * [nb_entity];
122	uint32_t ** dcache_miss_penality = new uint32_t * [nb_entity];
123
124	for (uint32_t i=0; i<nb_entity; i++)
125	{
126	cache_size_word = max(max<uint32_t>(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port)*morpheo->_size_icache_instruction,morpheo->_size_dcache_data)/8;
127	cache_size_line = 8;
128
129	if (cache_size<(cache_size_line*cache_size_word))
130	{
131	cerr << "cache is too small" << endl;
132	exit(EXIT_FAILURE);
133	}
134
135	cache_nb_line = cache_size/(cache_size_line*cache_size_word);
136	cache_associativity = 1;
137	cache_hit_latence = 1;
138	cache_miss_penality = 5;
139
140	icache_nb_level [i] = nb_cache_dedicated;
141	icache_nb_port [i] = morpheo->_nb_icache_port;
142	icache_nb_line [i] = new uint32_t [icache_nb_level[i]];
143	icache_size_line [i] = new uint32_t [icache_nb_level[i]];
144	icache_size_word [i] = new uint32_t [icache_nb_level[i]];
145	icache_associativity [i] = new uint32_t [icache_nb_level[i]];
146	icache_hit_latence [i] = new uint32_t [icache_nb_level[i]];
147	icache_miss_penality [i] = new uint32_t [icache_nb_level[i]];
148
149	dcache_nb_level [i] = icache_nb_level [i];
150	dcache_nb_port [i] = morpheo->_nb_dcache_port;
151	dcache_nb_line [i] = new uint32_t [dcache_nb_level[i]];
152	dcache_size_line [i] = new uint32_t [dcache_nb_level[i]];
153	dcache_size_word [i] = new uint32_t [dcache_nb_level[i]];
154	dcache_associativity [i] = new uint32_t [dcache_nb_level[i]];
155	dcache_hit_latence [i] = new uint32_t [dcache_nb_level[i]];
156	dcache_miss_penality [i] = new uint32_t [dcache_nb_level[i]];
157
158	for (uint32_t j=0; j<icache_nb_level[i]; ++j)
159	{
160	icache_nb_line [i][j] = cache_nb_line ;
161	icache_size_line [i][j] = cache_size_line ;
162	icache_size_word [i][j] = cache_size_word ;
163	icache_associativity [i][j] = cache_associativity;
164	icache_hit_latence [i][j] = cache_hit_latence ;
165	icache_miss_penality [i][j] = cache_miss_penality;
166
167	dcache_nb_line [i][j] = cache_nb_line ;
168	dcache_size_line [i][j] = cache_size_line ;
169	dcache_size_word [i][j] = cache_size_word ;
170	dcache_associativity [i][j] = cache_associativity;
171	dcache_hit_latence [i][j] = cache_hit_latence ;
172	dcache_miss_penality [i][j] = cache_miss_penality;
173
174	cache_nb_line *= cache_ratio;
175	cache_size_line *= cache_ratio;
176	// cache_size_word *= cache_ratio;
177	cache_associativity *= cache_ratio;
178	cache_hit_latence *= cache_ratio;
179	cache_miss_penality *= cache_ratio;
180	}
181	}
182
183	// Cache shared
184	uint32_t * cache_shared_nb_line = new uint32_t [nb_cache_shared];
185	uint32_t * cache_shared_size_line = new uint32_t [nb_cache_shared];
186	uint32_t * cache_shared_size_word = new uint32_t [nb_cache_shared];
187	uint32_t * cache_shared_associativity = new uint32_t [nb_cache_shared];
188	uint32_t * cache_shared_hit_latence = new uint32_t [nb_cache_shared];
189	uint32_t * cache_shared_miss_penality = new uint32_t [nb_cache_shared];
190
191	for (uint32_t i=0; i<nb_cache_shared; ++i)
192	{
193	cache_shared_nb_line [i] = cache_nb_line ;
194	cache_shared_size_line [i] = cache_size_line ;
195	cache_shared_size_word [i] = cache_size_word ;
196	cache_shared_associativity [i] = cache_associativity;
197	cache_shared_hit_latence [i] = cache_hit_latence ;
198	cache_shared_miss_penality [i] = cache_miss_penality;
199
200	cache_nb_line *= cache_ratio;
201	cache_size_line *= cache_ratio;
202	// cache_size_word *= cache_ratio;
203	cache_associativity *= cache_ratio;
204	cache_hit_latence *= cache_ratio;
205	cache_miss_penality *= cache_ratio;
206	}
207
208	// TTY
209	uint32_t nb_component_tty = 1;
210	uint32_t * tty_address = new uint32_t [nb_component_tty];
211	uint32_t * nb_tty = new uint32_t [nb_component_tty];
212	for (uint32_t i=0; i<nb_component_tty; ++i)
213	{
214	tty_address [i] = TTY_BASE;
215	nb_tty [i] = nb_thread;
216	}
217	string ** name_tty = new string * [nb_component_tty];
218	for (uint32_t i=0; i<nb_component_tty; ++i)
219	{
220	name_tty [i] = new string [nb_tty[i]];
221	for (uint32_t j=0; j<nb_tty[i]; ++j)
222	name_tty [i][j] = "tty_"+toString(i)+"_"+toString(j);
223	}
224
225	// Ramlock
226	uint32_t nb_component_ramlock = 1;
227	uint32_t * ramlock_address = new uint32_t [nb_component_ramlock];
228	uint32_t * nb_lock = new uint32_t [nb_component_ramlock];
229	for (uint32_t i=0; i<nb_component_ramlock; ++i)
230	{
231	ramlock_address [i] = RAMLOCK_BASE;
232	nb_lock [i] = 100*nb_thread;
233	}
234
235	// Sim2OS
236	uint32_t sim2os_address = SIM2OS_BASE;
237	uint32_t sim2os_size = SIM2OS_SIZE;
238
239	SOCLIB_SEGMENT_TABLE * segtable = new SOCLIB_SEGMENT_TABLE;
240	segtable->setMSBNumber (8);
241	segtable->setDefaultTarget(0,0);
242
243	// Add a segment ,name ,address of base ,size ,global index,local index,uncache
244	segtable->addSegment("text" ,TEXT_BASE ,TEXT_SIZE ,0 ,0 ,false);
245	segtable->addSegment("data" ,DATA_CACHED_BASE ,DATA_CACHED_SIZE ,0 ,0 ,false);
246	segtable->addSegment("data_stack" ,DATA_STACK_BASE ,DATA_STACK_SIZE ,0 ,0 ,false);
247	segtable->addSegment("data_unc" ,DATA_UNCACHED_BASE,DATA_UNCACHED_SIZE,0 ,0 ,true );
248
249	Parameters * param_environment = new Parameters
250	(nb_thread,
251	nb_entity,
252
253	iaccess_nb_context,
254	iaccess_nb_instruction,
255	iaccess_nb_packet,
256	iaccess_size_address,
257	iaccess_size_data,
258
259	daccess_nb_context,
260	daccess_nb_packet,
261	daccess_size_address,
262	daccess_size_data,
263
264	buffer_irsp_size,
265	buffer_drsp_size,
266
267	icache_nb_level ,
268	icache_nb_port ,
269	icache_nb_line ,
270	icache_size_line ,
271	icache_size_word ,
272	icache_associativity,
273	icache_hit_latence ,
274	icache_miss_penality,
275	dcache_nb_level ,
276	dcache_nb_port ,
277	dcache_nb_line ,
278	dcache_size_line ,
279	dcache_size_word ,
280	dcache_associativity,
281	dcache_hit_latence ,
282	dcache_miss_penality,
283
284	nb_cache_shared ,
285	// cache_shared_nb_port ,
286	cache_shared_nb_line ,
287	cache_shared_size_line ,
288	cache_shared_size_word ,
289	cache_shared_associativity ,
290	cache_shared_hit_latence ,
291	cache_shared_miss_penality ,
292
293	nb_component_tty,
294	tty_address,
295	nb_tty,
296	name_tty,
297	false,
298
299	nb_component_ramlock,
300	ramlock_address,
301	nb_lock,
302
303	sim2os_address,
304	sim2os_size,
305	segtable
306	);
307
308	// cout << param_environment->print(0) << endl;
309
310	segtable->print();
311
312	Environment * environment = new Environment ("environment",param_environment);
313
314	const char * sections_text [] = {".text",NULL};
315	const char * sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL};
316
317	if (environment->init("text" , filename_software.c_str(), sections_text) == false) exit (EXIT_FAILURE);
318	if (environment->init("data" , filename_software.c_str(), sections_data) == false) exit (EXIT_FAILURE);
319
320	//==============================================================================
321	//===== [ SIGNAL ]==============================================================
322	//==============================================================================
323
324	sc_clock * CLOCK = new sc_clock ("clock", 1.0, 0.5);
325	sc_signal<Tcontrol_t> * NRESET = new sc_signal<Tcontrol_t> ("NRESET");
326
327	sc_signal<Tcontrol_t > ** ICACHE_REQ_VAL ;
328	sc_signal<Tcontrol_t > ** ICACHE_REQ_ACK ;
329	sc_signal<Ticache_context_t > ** ICACHE_REQ_THREAD_ID ;
330	sc_signal<Ticache_packet_t > ** ICACHE_REQ_PACKET_ID ;
331	sc_signal<Ticache_address_t > ** ICACHE_REQ_ADDRESS ;
332	sc_signal<Ticache_type_t > ** ICACHE_REQ_TYPE ;
333
334	sc_signal<Tcontrol_t > ** ICACHE_RSP_VAL ;
335	sc_signal<Tcontrol_t > ** ICACHE_RSP_ACK ;
336	sc_signal<Ticache_context_t > ** ICACHE_RSP_THREAD_ID ;
337	sc_signal<Ticache_packet_t > ** ICACHE_RSP_PACKET_ID ;
338	sc_signal<Ticache_instruction_t> *** ICACHE_RSP_INSTRUCTION;
339	sc_signal<Ticache_error_t > ** ICACHE_RSP_ERROR ;
340
341	sc_signal<Tcontrol_t > ** DCACHE_REQ_VAL ;
342	sc_signal<Tcontrol_t > ** DCACHE_REQ_ACK ;
343	sc_signal<Tdcache_context_t > ** DCACHE_REQ_THREAD_ID ;
344	sc_signal<Tdcache_packet_t > ** DCACHE_REQ_PACKET_ID ;
345	sc_signal<Tdcache_address_t > ** DCACHE_REQ_ADDRESS ;
346	sc_signal<Tdcache_data_t > ** DCACHE_REQ_WDATA ;
347	sc_signal<Tdcache_type_t > ** DCACHE_REQ_TYPE ;
348
349	sc_signal<Tcontrol_t > ** DCACHE_RSP_VAL ;
350	sc_signal<Tcontrol_t > ** DCACHE_RSP_ACK ;
351	sc_signal<Tdcache_context_t > ** DCACHE_RSP_THREAD_ID ;
352	sc_signal<Tdcache_packet_t > ** DCACHE_RSP_PACKET_ID ;
353	sc_signal<Tdcache_data_t > ** DCACHE_RSP_RDATA ;
354	sc_signal<Tdcache_error_t > ** DCACHE_RSP_ERROR ;
355
356	sc_signal<Tcontrol_t > ** INTERRUPT_ENABLE ;
357
358	ALLOC1_SC_SIGNAL(ICACHE_REQ_VAL ,"ICACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
359	ALLOC1_SC_SIGNAL(ICACHE_REQ_ACK ,"ICACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
360	ALLOC1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,"ICACHE_REQ_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
361	ALLOC1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,"ICACHE_REQ_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
362	ALLOC1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,"ICACHE_REQ_ADDRESS ",Ticache_address_t ,morpheo->_nb_icache_port);
363	ALLOC1_SC_SIGNAL(ICACHE_REQ_TYPE ,"ICACHE_REQ_TYPE ",Ticache_type_t ,morpheo->_nb_icache_port);
364
365	ALLOC1_SC_SIGNAL(ICACHE_RSP_VAL ,"ICACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_icache_port);
366	ALLOC1_SC_SIGNAL(ICACHE_RSP_ACK ,"ICACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_icache_port);
367	ALLOC1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,"ICACHE_RSP_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port);
368	ALLOC1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,"ICACHE_RSP_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port);
369	ALLOC2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,"ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
370	ALLOC1_SC_SIGNAL(ICACHE_RSP_ERROR ,"ICACHE_RSP_ERROR ",Ticache_error_t ,morpheo->_nb_icache_port);
371
372	ALLOC1_SC_SIGNAL(DCACHE_REQ_VAL ,"DCACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
373	ALLOC1_SC_SIGNAL(DCACHE_REQ_ACK ,"DCACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
374	ALLOC1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,"DCACHE_REQ_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
375	ALLOC1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,"DCACHE_REQ_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
376	ALLOC1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,"DCACHE_REQ_ADDRESS ",Tdcache_address_t ,morpheo->_nb_dcache_port);
377	ALLOC1_SC_SIGNAL(DCACHE_REQ_WDATA ,"DCACHE_REQ_WDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
378	ALLOC1_SC_SIGNAL(DCACHE_REQ_TYPE ,"DCACHE_REQ_TYPE ",Tdcache_type_t ,morpheo->_nb_dcache_port);
379
380	ALLOC1_SC_SIGNAL(DCACHE_RSP_VAL ,"DCACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port);
381	ALLOC1_SC_SIGNAL(DCACHE_RSP_ACK ,"DCACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port);
382	ALLOC1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,"DCACHE_RSP_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port);
383	ALLOC1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,"DCACHE_RSP_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port);
384	ALLOC1_SC_SIGNAL(DCACHE_RSP_RDATA ,"DCACHE_RSP_RDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port);
385	ALLOC1_SC_SIGNAL(DCACHE_RSP_ERROR ,"DCACHE_RSP_ERROR ",Tdcache_error_t ,morpheo->_nb_dcache_port);
386
387	ALLOC1_SC_SIGNAL(INTERRUPT_ENABLE ,"INTERRUPT_ENABLE ",Tcontrol_t ,morpheo->_nb_thread);
388
389	//==============================================================================
390	//===== [ INSTANCE ]============================================================
391	//==============================================================================
392
393	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
394	//~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
395	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
396
397	((morpheo->in_CLOCK)) ((CLOCK));
398	((morpheo->in_NRESET)) ((NRESET));
399
400	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_VAL ,ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
401	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_REQ_ACK ,ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
402	if (morpheo->_have_port_icache_thread_id)
403	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_THREAD_ID ,ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
404	if (morpheo->_have_port_icache_packet_id)
405	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_PACKET_ID ,ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
406	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_ADDRESS ,ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
407	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_TYPE ,ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
408
409	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_VAL ,ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
410	_INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_RSP_ACK ,ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
411	if (morpheo->_have_port_icache_thread_id)
412	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_THREAD_ID ,ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
413	if (morpheo->_have_port_icache_packet_id)
414	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_PACKET_ID ,ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
415	_INSTANCE2_SC_SIGNAL(morpheo, in_ICACHE_RSP_INSTRUCTION ,ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
416	_INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_ERROR ,ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
417
418	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_VAL ,DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
419	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_REQ_ACK ,DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
420	if (morpheo->_have_port_dcache_thread_id)
421	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_THREAD_ID ,DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
422	if (morpheo->_have_port_dcache_packet_id)
423	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_PACKET_ID ,DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
424	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_ADDRESS ,DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
425	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_WDATA ,DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
426	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_TYPE ,DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
427
428	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_VAL ,DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
429	_INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_RSP_ACK ,DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
430	if (morpheo->_have_port_dcache_thread_id)
431	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_THREAD_ID ,DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
432	if (morpheo->_have_port_dcache_packet_id)
433	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_PACKET_ID ,DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
434	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_RDATA ,DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
435	_INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_ERROR ,DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
436
437	_INSTANCE1_SC_SIGNAL(morpheo, in_INTERRUPT_ENABLE ,INTERRUPT_ENABLE ,morpheo->_nb_thread);
438
439	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
440	//~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
441	//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
442
443	((environment->CLOCK)) ((CLOCK));
444	((environment->NRESET)) ((NRESET));
445
446	for (uint32_t i=0; i<morpheo->_nb_icache_port; ++i)
447	{
448	((environment->ICACHE_REQ_VAL [0][i] )) ((ICACHE_REQ_VAL [i] ));
449	((environment->ICACHE_REQ_ACK [0][i] )) ((ICACHE_REQ_ACK [i] ));
450	((environment->ICACHE_REQ_CONTEXT_ID [0][i] )) ((ICACHE_REQ_THREAD_ID [i] ));
451	((environment->ICACHE_REQ_PACKET_ID [0][i] )) ((ICACHE_REQ_PACKET_ID [i] ));
452	((environment->ICACHE_REQ_ADDRESS [0][i] )) ((ICACHE_REQ_ADDRESS [i] ));
453	((environment->ICACHE_REQ_TYPE [0][i] )) ((ICACHE_REQ_TYPE [i] ));
454
455	((environment->ICACHE_RSP_VAL [0][i] )) ((ICACHE_RSP_VAL [i] ));
456	((environment->ICACHE_RSP_ACK [0][i] )) ((ICACHE_RSP_ACK [i] ));
457	((environment->ICACHE_RSP_CONTEXT_ID [0][i] )) ((ICACHE_RSP_THREAD_ID [i] ));
458	((environment->ICACHE_RSP_PACKET_ID [0][i] )) ((ICACHE_RSP_PACKET_ID [i] ));
459	((environment->ICACHE_RSP_ERROR [0][i] )) ((ICACHE_RSP_ERROR [i] ));
460
461	for (uint32_t j=0; j<morpheo->_icache_nb_instruction[i]; ++j)
462	((environment->ICACHE_RSP_INSTRUCTION [0][i][j])) ((ICACHE_RSP_INSTRUCTION [i][j]));
463	}
464	for (uint32_t i=0; i<morpheo->_nb_dcache_port; ++i)
465	{
466	((environment->DCACHE_REQ_VAL [0][i] )) ((DCACHE_REQ_VAL [i] ));
467	((environment->DCACHE_REQ_ACK [0][i] )) ((DCACHE_REQ_ACK [i] ));
468	((environment->DCACHE_REQ_CONTEXT_ID [0][i] )) ((DCACHE_REQ_THREAD_ID [i] ));
469	((environment->DCACHE_REQ_PACKET_ID [0][i] )) ((DCACHE_REQ_PACKET_ID [i] ));
470	((environment->DCACHE_REQ_ADDRESS [0][i] )) ((DCACHE_REQ_ADDRESS [i] ));
471	((environment->DCACHE_REQ_WDATA [0][i] )) ((DCACHE_REQ_WDATA [i] ));
472	((environment->DCACHE_REQ_TYPE [0][i] )) ((DCACHE_REQ_TYPE [i] ));
473
474	((environment->DCACHE_RSP_VAL [0][i] )) ((DCACHE_RSP_VAL [i] ));
475	((environment->DCACHE_RSP_ACK [0][i] )) ((DCACHE_RSP_ACK [i] ));
476	((environment->DCACHE_RSP_CONTEXT_ID [0][i] )) ((DCACHE_RSP_THREAD_ID [i] ));
477	((environment->DCACHE_RSP_PACKET_ID [0][i] )) ((DCACHE_RSP_PACKET_ID [i] ));
478	((environment->DCACHE_RSP_RDATA [0][i] )) ((DCACHE_RSP_RDATA [i] ));
479	((environment->DCACHE_RSP_ERROR [0][i] )) ((DCACHE_RSP_ERROR [i] ));
480	}
481
482	//_INSTANCE2_SC_SIGNAL(environment,INTERRUPT_ENABLE ,1,morpheo->_nb_thread);
483
484	//==============================================================================
485	//===== [ SIMULATION ]==========================================================
486	//==============================================================================
487
488	// initialisation
489	cerr << "<test> Simulation Init" << endl;
490
491	sc_start(0);
492
493	cerr << "<test> Simulation Start" << endl;
494
495	bool morpheo_error = false;
496	try
497	{
498	Time * _time_global = new Time();
499
500	for (uint32_t i=0; i<morpheo->_nb_thread; ++i)
501	INTERRUPT_ENABLE[i]->write(0);
502
503	NRESET->write(0);
504	SC_START(5);
505	NRESET->write(1);
506
507	// Infinite loop
508	do
509	{
510	// Time * _time_local = new Time();
511	SC_START(100000);
512	// delete _time_local;
513	} while (not morpheo ->simulation_end() and // morpheo condition stop
514	not environment->simulation_end()); // test ok
515	delete _time_global;
516	}
517	catch (morpheo::ErrorMorpheo & error)
518	{
519	std::cerr << error.what() << std::endl
520	<< STR_KO << std::endl;
521
522	morpheo_error = true;
523	}
524
525	bool morpheo_end = morpheo->simulation_end();
526	bool environment_end = environment->simulation_end();
527
528
529	//==============================================================================
530	//===== [ DESTRUCTION ]=========================================================
531	//==============================================================================
532
533	delete CLOCK;
534	delete NRESET;
535
536	DELETE1_SC_SIGNAL(ICACHE_REQ_VAL ,morpheo->_nb_icache_port);
537	DELETE1_SC_SIGNAL(ICACHE_REQ_ACK ,morpheo->_nb_icache_port);
538	DELETE1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port);
539	DELETE1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port);
540	DELETE1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port);
541	DELETE1_SC_SIGNAL(ICACHE_REQ_TYPE ,morpheo->_nb_icache_port);
542
543	DELETE1_SC_SIGNAL(ICACHE_RSP_VAL ,morpheo->_nb_icache_port);
544	DELETE1_SC_SIGNAL(ICACHE_RSP_ACK ,morpheo->_nb_icache_port);
545	DELETE1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port);
546	DELETE1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port);
547	DELETE1_SC_SIGNAL(ICACHE_RSP_ERROR ,morpheo->_nb_icache_port);
548	DELETE2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]);
549
550	DELETE1_SC_SIGNAL(DCACHE_REQ_VAL ,morpheo->_nb_dcache_port);
551	DELETE1_SC_SIGNAL(DCACHE_REQ_ACK ,morpheo->_nb_dcache_port);
552	DELETE1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port);
553	DELETE1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port);
554	DELETE1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port);
555	DELETE1_SC_SIGNAL(DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port);
556	DELETE1_SC_SIGNAL(DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port);
557
558	DELETE1_SC_SIGNAL(DCACHE_RSP_VAL ,morpheo->_nb_dcache_port);
559	DELETE1_SC_SIGNAL(DCACHE_RSP_ACK ,morpheo->_nb_dcache_port);
560	DELETE1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port);
561	DELETE1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port);
562	DELETE1_SC_SIGNAL(DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port);
563	DELETE1_SC_SIGNAL(DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port);
564
565	DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread);
566
567	delete environment;
568
569	delete param_environment;
570	delete segtable;
571
572	delete [] nb_lock ;
573	delete [] ramlock_address;
574
575	for (uint32_t i=0;i<nb_component_tty;++i)
576	delete [] name_tty [i];
577	delete [] name_tty;
578	delete [] nb_tty;
579	delete [] tty_address;
580
581	delete [] cache_shared_miss_penality;
582	delete [] cache_shared_hit_latence ;
583	delete [] cache_shared_associativity;
584	delete [] cache_shared_size_word ;
585	delete [] cache_shared_size_line ;
586	delete [] cache_shared_nb_line ;
587
588	for (uint32_t i=0; i<nb_entity; i++)
589	{
590	delete [] dcache_miss_penality [i];
591	delete [] dcache_hit_latence [i];
592	delete [] dcache_associativity [i];
593	delete [] dcache_size_word [i];
594	delete [] dcache_size_line [i];
595	delete [] dcache_nb_line [i];
596	}
597	delete [] dcache_miss_penality ;
598	delete [] dcache_hit_latence ;
599	delete [] dcache_associativity ;
600	delete [] dcache_size_word ;
601	delete [] dcache_size_line ;
602	delete [] dcache_nb_line ;
603	delete [] dcache_nb_level ;
604	delete [] dcache_nb_port ;
605
606	for (uint32_t i=0; i<nb_entity; i++)
607	{
608	delete [] icache_miss_penality [i];
609	delete [] icache_hit_latence [i];
610	delete [] icache_associativity [i];
611	delete [] icache_size_word [i];
612	delete [] icache_size_line [i];
613	delete [] icache_nb_line [i];
614	}
615	delete [] icache_miss_penality;
616	delete [] icache_hit_latence ;
617	delete [] icache_associativity;
618	delete [] icache_size_word ;
619	delete [] icache_size_line ;
620	delete [] icache_nb_line ;
621	delete [] icache_nb_level ;
622	delete [] icache_nb_port ;
623
624	delete [] buffer_drsp_size ;
625	delete [] buffer_irsp_size ;
626	delete [] daccess_size_data ;
627	delete [] daccess_size_address ;
628	delete [] daccess_nb_packet ;
629	delete [] daccess_nb_context ;
630	delete [] iaccess_size_data ;
631	delete [] iaccess_size_address ;
632	delete [] iaccess_nb_packet ;
633	delete [] iaccess_nb_instruction;
634	delete [] iaccess_nb_context ;
635
636	delete morpheo;
637
638	bool test_ok = false;
639	if (not morpheo_error)
640	{
641	if (not morpheo_end and not environment_end)
642	{
643	cerr << "<test> Simulation End : Unknow" << endl;
644	}
645	else
646	{
647	if (morpheo_end)
648	{
649	cout << "<test> Simulation End : MORPHEO" << endl;
650	test_ok = true;
651	}
652	if (environment_end)
653	{
654	cout << "<test> Simulation End : ENVIRONMENT" << endl;
655	test_ok = true;
656	}
657	}
658	}
659
660	if (test_ok)
661	{
662	cout << STR_OK << endl;
663	return EXIT_SUCCESS;
664	}
665	else
666	{
667	cout << STR_KO << endl;
668	return EXIT_FAILURE;
669	}
670	}

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