Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp
r98 r100 27 27 if (PORT_READ(in_NRESET)) 28 28 { 29 30 29 // Init 31 30 Tcontrol_t ack [_param->_nb_context]; … … 36 35 { 37 36 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); 38 37 38 // No access 39 39 Tcontrol_t btb_val = false; 40 40 Tcontrol_t dir_val = false; … … 42 42 Tcontrol_t upt_val = false; 43 43 44 // Get ack 44 45 Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); 45 46 Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); … … 47 48 Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); 48 49 50 // Read context_id 49 51 Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority 50 52 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); 51 53 54 // Now : ack transaction 52 55 ack [context] = 1; 53 56 54 57 if (PORT_READ(in_PREDICT_VAL[context]) == 0) 55 58 { 59 // Nothing 56 60 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); 57 61 … … 63 67 else 64 68 { 69 // Have transaction 65 70 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); 66 71 72 // Read information (PC) 67 73 Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); 68 74 Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); 69 75 Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); 70 76 71 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x ",pc_previous);72 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x ",pc_current);77 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x (0x%.8x)",pc_previous,pc_previous<<2); 78 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x (0x%.8x)",pc_current ,pc_current <<2); 73 79 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); 74 80 … … 80 86 81 87 // STEP (1) - Compute the address source 82 // if pc_current is a ds take, then pc_previous is a branchement 88 // -> if pc_current is a ds take, then pc_previous is a branchement 89 // get branchement address to send at the BTB 83 90 Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; 91 // Address_lsb = position in fetch packet 84 92 Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 85 93 Taddress_t address_msb; 86 94 87 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x ",address);95 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x (0x%.8x)",address,address<<2); 88 96 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); 89 97 90 98 // STEP (2) - Test if branch (access at branch_target_buffer) 99 // Access at the btb 91 100 btb_val = true; 92 101 102 // Create the request 93 103 if (_param->_have_port_context_id) 94 104 PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); 95 105 PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); 96 106 107 // Transaction can be ack if btb is not busy 97 108 ack [context] &= btb_ack; 98 109 99 110 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); 100 111 101 // BTB_ack = 0 ? 112 // BTB_ack = 0 ? else can continue 102 113 if (not btb_ack) 103 114 continue; 104 115 105 // special case :106 // if pc_current _is_ds, then pc_previous have branch, also hit must be set.107 // else : a another branchhave eject this branch : can't accurate116 // Test a special case : 117 // if pc_current is a delay slot, then pc_previous is a branchement instruction, also hit must be set. 118 // else : an another branch instruction have eject this branch : can't accurate 108 119 Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); 109 120 Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); … … 112 123 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); 113 124 114 // STEP (3) : Test if have branchin the packet125 // STEP (3) : Test if BTB find a branch instruction in the packet 115 126 if (hit == 1) 116 127 { 128 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB hit : no sequential order"); 129 117 130 // STEP (3a) : branch - test condition 118 131 bool use_dir = false; 119 132 bool use_ras = false; 120 133 bool use_upt = false; 121 122 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 123 Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 124 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 125 Tcontrol_t push ; 126 Tcontrol_t direction; 127 128 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); 129 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); 130 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); 131 132 switch (condition) 133 { 134 case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j 135 { 136 // use none unit (dir, upt and ras) 137 direction = true; 138 pc_next = address_dest; 139 branch_state = BRANCH_STATE_NSPEC_TAKE; 140 break; 141 } 142 case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal 143 { 144 use_upt = true; 145 use_ras = true; 146 push = true; 147 direction = true; 148 pc_next = address_dest; 149 branch_state = BRANCH_STATE_NSPEC_TAKE; 150 break; 151 } 152 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 153 case BRANCH_CONDITION_FLAG_SET : // l.bf 154 { 155 use_upt = true; 156 use_dir = true; 157 // Test direction 158 direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same 159 if (direction = 1) 160 { 161 branch_state = BRANCH_STATE_SPEC_TAKE; 162 pc_next = address_dest; 163 } 164 else 165 { 166 branch_state = BRANCH_STATE_SPEC_NTAKE; 167 pc_next = address_src+2; // +1 = delay slot 168 } 169 break; 170 } 171 case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) 172 { 173 use_upt = true; 174 use_ras = true; 175 push = true; 176 direction = true; 177 pc_next = address_dest; 178 branch_state = BRANCH_STATE_SPEC_TAKE; 179 break; 180 } 181 case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr 182 { 183 use_upt = true; 184 use_ras = true; 185 push = true; 186 direction = true; 187 pc_next = address_dest; 188 branch_state = BRANCH_STATE_NSPEC_TAKE; 189 break; 190 } 191 case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) 192 { 193 use_upt = true; 194 use_ras = true; 195 push = false; 196 direction = true; 197 pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); 198 branch_state = BRANCH_STATE_SPEC_TAKE; 199 break; 200 } 201 default : 202 { 203 ERRORMORPHEO(FUNCTION,"Unknow Condition"); 204 break; 205 } 206 } 207 208 if (use_dir) 209 { 210 ack[context] &= dir_ack; 211 PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); 212 PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take 213 // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); 214 } 215 216 if (use_ras) 217 { 218 ack[context] &= ras_ack; 219 if (_param->_have_port_context_id) 220 PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); 221 PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); 222 PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 223 224 is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate 225 } 226 227 if (use_upt) 228 { 229 ack[context] &= upt_ack; 230 231 if (_param->_have_port_context_id) 232 PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); 233 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); 234 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); 235 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); 236 PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); 237 PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); 238 // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); 239 PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); 240 // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); 241 } 242 243 // ack = 1 if : 244 // * btb_ack 245 // * use_dir and dir_ack 246 // * use_ras and ras_ack 247 // * use_upt and upt_ack 248 // ack [context] = (btb_ack and 249 // (use_dir and dir_ack) and 250 // (use_ras and ras_ack) and 251 // (use_upt and upt_ack)); 252 253 dir_val = (btb_ack and 254 use_dir and 255 // use_ras and 256 // use_upt and 257 // (not use_dir or (use_dir and dir_ack)) and 258 (not use_ras or (use_ras and ras_ack)) and 259 (not use_upt or (use_upt and upt_ack))); 260 261 ras_val = (btb_ack and 262 // use_dir and 263 use_ras and 264 // use_upt and 265 (not use_dir or (use_dir and dir_ack)) and 266 // (not use_ras or (use_ras and ras_ack)) and 267 (not use_upt or (use_upt and upt_ack))); 268 269 upt_val = (btb_ack and 270 // use_dir and 271 // use_ras and 272 use_upt and 273 (not use_dir or (use_dir and dir_ack)) and 274 (not use_ras or (use_ras and ras_ack))// and 275 // (not use_upt or (use_upt and upt_ack)) 276 ); 277 278 // pc_next - is previously computed 279 // branch_state - is previously computed 280 281 Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; 282 283 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); 134 135 Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 136 Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; 137 138 inst_ifetch_ptr = address_src_lsb; 139 140 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src,address_src<<2); 284 141 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); 285 142 286 if (address_src_lsb == (_param->_nb_instruction [context]-1)) 143 // Special case : 144 // * BTB hit and the branchement is the PC current and it's the last slot. 145 // -> next pc must be the delay slot 146 if ((not pc_current_is_ds_take) and // if pc_current is ds_take, alors pc_next is the destination of branchement 147 (address_src_lsb == (_param->_nb_instruction [context]-1))) 287 148 { 288 149 // branch is in the last slot of the packet 289 150 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); 290 151 152 // Branch is the last slot : next paquet is the delay slot 153 pc_next = address_src+1; // sequencial 154 pc_next_is_ds_take = 1; 291 155 address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) 292 pc_next_is_ds_take = 1;156 branch_state = BRANCH_STATE_NONE; 293 157 } 294 158 else 295 159 { 160 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 161 Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 162 Tcontrol_t push ; 163 Tcontrol_t direction; 164 165 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); 166 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x (0x%.8x)",address_src ,address_src <<2); 167 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x (0x%.8x)",address_dest,address_dest<<2); 168 169 switch (condition) 170 { 171 case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j 172 { 173 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); 174 175 // use none unit (dir, upt and ras) 176 direction = true; 177 pc_next = address_dest; 178 branch_state = BRANCH_STATE_NSPEC_TAKE; 179 break; 180 } 181 case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal 182 { 183 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); 184 185 use_upt = true; 186 use_ras = true; 187 push = true; 188 direction = true; 189 pc_next = address_dest; 190 branch_state = BRANCH_STATE_NSPEC_TAKE; 191 break; 192 } 193 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 194 case BRANCH_CONDITION_FLAG_SET : // l.bf 195 { 196 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); 197 198 use_upt = true; 199 use_dir = true; 200 // Test direction 201 direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same 202 if (direction = 1) 203 { 204 branch_state = BRANCH_STATE_SPEC_TAKE; 205 pc_next = address_dest; 206 } 207 else 208 { 209 branch_state = BRANCH_STATE_SPEC_NTAKE; 210 pc_next = address_src+2; // +1 = delay slot 211 } 212 break; 213 } 214 case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) 215 { 216 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK"); 217 218 use_upt = true; 219 use_ras = true; 220 push = true; 221 direction = true; 222 pc_next = address_dest; 223 branch_state = BRANCH_STATE_SPEC_TAKE; 224 break; 225 } 226 case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr 227 { 228 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); 229 230 use_upt = true; 231 use_ras = true; 232 push = true; 233 direction = true; 234 pc_next = address_dest; 235 branch_state = BRANCH_STATE_NSPEC_TAKE; 236 break; 237 } 238 case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) 239 { 240 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); 241 use_upt = true; 242 use_ras = true; 243 push = false; 244 direction = true; 245 pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); 246 branch_state = BRANCH_STATE_SPEC_TAKE; 247 break; 248 } 249 default : 250 { 251 ERRORMORPHEO(FUNCTION,"Unknow Condition"); 252 break; 253 } 254 } 255 256 if (use_dir) 257 { 258 ack[context] &= dir_ack; 259 PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); 260 PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest<address_src); // if destination is previous : the static direction is take 261 // PORT_WRITE(out_PREDICT_DIR_LAST_TAKE [i], PORT_READ(in_PREDICT_BTB_LAST_TAKE [i])); 262 } 263 264 if (use_ras) 265 { 266 ack[context] &= ras_ack; 267 if (_param->_have_port_context_id) 268 PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); 269 PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); 270 PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); 271 272 is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate 273 } 274 275 if (use_upt) 276 { 277 ack[context] &= upt_ack; 278 279 if (_param->_have_port_context_id) 280 PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); 281 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); 282 PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); 283 PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); 284 PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); 285 PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); 286 // PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); 287 PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); 288 // PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); 289 } 290 291 // ack = 1 if : 292 // * btb_ack 293 // * use_dir and dir_ack 294 // * use_ras and ras_ack 295 // * use_upt and upt_ack 296 // ack [context] = (btb_ack and 297 // (use_dir and dir_ack) and 298 // (use_ras and ras_ack) and 299 // (use_upt and upt_ack)); 300 301 dir_val = (btb_ack and 302 use_dir and 303 // use_ras and 304 // use_upt and 305 // (not use_dir or (use_dir and dir_ack)) and 306 (not use_ras or (use_ras and ras_ack)) and 307 (not use_upt or (use_upt and upt_ack))); 308 309 ras_val = (btb_ack and 310 // use_dir and 311 use_ras and 312 // use_upt and 313 (not use_dir or (use_dir and dir_ack)) and 314 // (not use_ras or (use_ras and ras_ack)) and 315 (not use_upt or (use_upt and upt_ack))); 316 317 upt_val = (btb_ack and 318 // use_dir and 319 // use_ras and 320 use_upt and 321 (not use_dir or (use_dir and dir_ack)) and 322 (not use_ras or (use_ras and ras_ack))// and 323 // (not use_upt or (use_upt and upt_ack)) 324 ); 325 326 // pc_next - is previously computed 327 // branch_state - is previously computed 328 329 296 330 // branch is in the last slot of the packet 297 331 address_msb = (address_src_lsb+2); // +1 == delayed slot 298 332 pc_next_is_ds_take = 0; 299 333 } 300 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); 301 302 inst_ifetch_ptr = address_src_lsb; 334 303 335 // branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; 304 336 } … … 308 340 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); 309 341 310 pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial 342 // Take the address packet base and add new packet 343 pc_next = pc_current-address_lsb+_param->_nb_instruction [context]; // sequencial 311 344 pc_next_is_ds_take = 0; // no branch, also no delay slot 312 345 inst_ifetch_ptr = 0; … … 316 349 address_msb = _param->_nb_instruction [context]; 317 350 } 318 319 PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); 320 PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); 321 322 Taddress_t address_limit_min = address_lsb; 323 Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); 324 325 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); 326 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); 327 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); 328 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); 329 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); 330 331 for (uint32_t j=0; j<address_limit_min; j++) 332 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid 333 for (uint32_t j=address_limit_min; j<address_limit_max; j++) 334 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Vald packet 335 for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) 336 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid 337 if (_param->_have_port_inst_ifetch_ptr) 338 PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); 339 PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); 340 if (_param->_have_port_depth) 341 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); 351 352 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); 353 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next : 0x%.8x (0x%.8x)",pc_next,pc_next<<2); 354 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_next_is_ds_take : %d" ,pc_next_is_ds_take); 355 356 // Write Output 357 PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); 358 PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); 359 360 // Create enable mask 361 Taddress_t address_limit_min = address_lsb; 362 Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); 363 364 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); 365 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); 366 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0" ,address_limit_min); 367 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_limit_min,address_limit_max); 368 log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",address_limit_max,_param->_nb_instruction [context]); 369 370 for (uint32_t j=0; j<address_limit_min; j++) 371 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // Before the address : not valid 372 for (uint32_t j=address_limit_min; j<address_limit_max; j++) 373 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 1); // Valid packet 374 for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) 375 PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid 376 377 if (_param->_have_port_inst_ifetch_ptr) 378 PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); 379 PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); 380 if (_param->_have_port_depth) 381 PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); 342 382 } 343 383 … … 348 388 PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); 349 389 } 350 390 391 // Write output 351 392 for (uint32_t i=0; i<_param->_nb_context; i++) 352 393 PORT_WRITE(out_PREDICT_ACK[i],ack[i]);
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