Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp
r95 r100 22 22 void Return_Address_Stack::transition (void) 23 23 { 24 log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); 24 log_begin(Return_Address_Stack,FUNCTION); 25 log_function(Return_Address_Stack,FUNCTION,_name.c_str()); 25 26 26 27 if (PORT_READ(in_NRESET)==0) 27 28 { 29 // Reset all structure 28 30 for (uint32_t i=0; i<_param->_nb_context; i++) 29 31 { 30 32 reg_TOP [i] = 0; 31 reg_BOTTOM [i] = 0;33 // reg_BOTTOM [i] = 0; 32 34 reg_NB_ELT [i] = 0; 33 35 34 36 reg_PREDICT_TOP [i] = 0; 35 reg_PREDICT_BOTTOM [i] = 0;37 // reg_PREDICT_BOTTOM [i] = 0; 36 38 reg_PREDICT_NB_ELT [i] = 0; 37 38 for (uint32_t j=0; j<_param->_size_queue [i]; j++)39 {40 reg_stack[i][j]._val = false;41 reg_stack[i][j]._predict = false;42 reg_stack[i][j]._miss = false;43 }44 39 } 45 40 } … … 52 47 if (PORT_READ(in_PREDICT_VAL [i]) and internal_PREDICT_ACK [i]) 53 48 { 54 log_printf(TRACE,Return_Address_Stack,FUNCTION,"PREDICT[%d] : Transaction",i); 49 log_printf(TRACE,Return_Address_Stack,FUNCTION," * PREDICT [%d] : Transaction",i); 50 51 // Read information and pointer 55 52 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 56 53 Tcontrol_t push = PORT_READ(in_PREDICT_PUSH [i]); 54 57 55 Tptr_t top_old = reg_PREDICT_TOP [context]; 58 56 Tptr_t top_new = top_old; 59 Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; 60 61 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 62 63 // Hit : push or (val and not miss and not empty) 57 // Tptr_t bottom_old = reg_PREDICT_BOTTOM [context]; 58 // Tptr_t bottom_new = bottom_old; 59 Tptr_t nb_elt_old = reg_PREDICT_NB_ELT [context]; 60 Tptr_t nb_elt_new = nb_elt_old; 61 62 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 63 64 // Hit : push or not empty 64 65 // Miss : ifetch is stall, no update 66 67 // Test if hit 65 68 if (internal_PREDICT_HIT [i]) 66 69 { 67 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 68 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 69 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 70 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 71 70 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 71 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 72 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 73 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 74 75 // Test if push 72 76 if (push) 73 77 { 78 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); 79 74 80 // push : increase the top (circular) 75 81 top_new = (top_old+1)%_param->_size_queue[context]; 76 77 reg_stack [context][top_new]._val = true; // New addr 78 reg_stack [context][top_new]._predict = true; // Is speculative (erase a old addr (or not)) 79 //reg_stack [context][top_new]._miss = ; 82 83 // Write new value in Queue 80 84 reg_stack [context][top_new]._address = PORT_READ(in_PREDICT_ADDRESS_PUSH [i]); 81 85 82 // the stack is full, erase the most old stack83 84 86 // Test if full 85 if (reg_PREDICT_NB_ELT[context]==_param->_size_queue[context]) 86 reg_PREDICT_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 87 // A new data is write : the stack is not empty 88 if (reg_PREDICT_NB_ELT[context]< _param->_size_queue[context]) 89 reg_PREDICT_NB_ELT[context]++; 87 // -> is full, the push erase the oldest value in stack, also nb_elt is the same 88 // -> is not full, increase nb_elt 89 // if (nb_elt_old==_param->_size_queue[context]) 90 // bottom_new = (bottom_old+1)%_param->_size_queue[context]; 91 // else 92 // nb_elt_new ++; 93 if (nb_elt_old!=_param->_size_queue[context]) 94 nb_elt_new ++; 90 95 } 91 96 else 92 97 { 93 98 // pop 94 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 95 96 //reg_stack [context][top_new]._val = ; 97 //reg_stack [context][top_new]._predict = ; 98 //reg_stack [context][top_new]._miss = ; 99 //reg_stack [context][top_new]._address = ; 100 101 // the stack is empty 102 if (reg_PREDICT_NB_ELT[context]>0) 99 log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); 100 101 // Test if the stack is empty 102 if (nb_elt_old>0) 103 103 { 104 104 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 105 reg_PREDICT_NB_ELT[context]--;105 nb_elt_new --; 106 106 } 107 // no else : can't pop 107 108 } 108 109 109 reg_PREDICT_TOP [context] = top_new; 110 111 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 112 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",reg_PREDICT_TOP [context]); 113 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",reg_PREDICT_BOTTOM [context]); 114 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",reg_PREDICT_NB_ELT [context]); 115 } 116 } 110 // Write new pointer 111 reg_PREDICT_TOP [context] = top_new; 112 // reg_PREDICT_BOTTOM [context] = bottom_new; 113 reg_PREDICT_NB_ELT [context] = nb_elt_new; 114 115 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 116 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 117 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 118 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 119 } 120 } 117 121 118 122 // =================================================================== … … 122 126 if (PORT_READ(in_DECOD_VAL [i]) and internal_DECOD_ACK [i]) 123 127 { 124 log_printf(TRACE,Return_Address_Stack,FUNCTION,"DECOD[%d] : Transaction",i); 128 log_printf(TRACE,Return_Address_Stack,FUNCTION," * DECOD [%d] : Transaction",i); 129 130 // Read information 125 131 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 126 132 Tcontrol_t push = PORT_READ(in_DECOD_PUSH [i]); 133 134 // Read pointer 127 135 Tptr_t top_old = reg_TOP [context]; 128 136 Tptr_t top_new = top_old; 129 Tptr_t bottom_old = reg_BOTTOM [context]; 130 //Tcontrol_t hit = internal_DECOD_HIT [i]; 131 Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 132 133 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 134 135 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 136 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 137 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 138 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 139 140 if (push) 141 { 142 // push : increase the top (circular) 143 top_new = (top_old+1)%_param->_size_queue[context]; 144 145 reg_stack [context][top_new]._val = true; // New address 146 reg_stack [context][top_new]._predict = false; // No speculative 147 reg_stack [context][top_new]._miss = false; 148 reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 149 150 // Test if full : if true, then icrease the bottom (erase the most old stack) 151 if (reg_NB_ELT[context]==_param->_size_queue[context]) 152 reg_BOTTOM [context] = (bottom_old+1)%_param->_size_queue[context]; 153 // A new data is write : the stack is not empty 154 if (reg_NB_ELT[context]< _param->_size_queue[context]) 155 reg_NB_ELT[context]++; 156 } 157 else 158 { 159 // pop 160 // top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 161 162 //reg_stack [context][top_new]._val = ; 163 //reg_stack [context][top_new]._predict = ; 164 //reg_stack [context][top_new]._miss = ; 165 //reg_stack [context][top_new]._address = ; 166 167 // the stack is empty 168 if (reg_NB_ELT[context]>0) 169 { 170 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 171 reg_NB_ELT[context] --; 172 } 173 } 174 175 reg_TOP [context] = top_new; 176 177 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 178 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",reg_TOP [context]); 179 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",reg_BOTTOM [context]); 180 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",reg_NB_ELT [context]); 181 137 // Tptr_t bottom_old = reg_BOTTOM [context]; 138 // Tptr_t bottom_new = bottom_old; 139 Tptr_t nb_elt_old = reg_NB_ELT [context]; 140 Tptr_t nb_elt_new = nb_elt_old; 141 142 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context : %d",context); 143 144 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 145 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 146 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 147 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 148 149 // Test if push 150 if (push) 151 { 152 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push (call procedure)"); 153 154 // push : increase the top (circular) 155 top_new = (top_old+1)%_param->_size_queue[context]; 156 157 // Write new value in Queue 158 reg_stack [context][top_new]._address = PORT_READ(in_DECOD_ADDRESS_PUSH [i]); 159 160 // Test if full 161 // -> is full, the push erase the oldest value in stack, also nb_elt is the same 162 // -> is not full, increase nb_elt 163 // if (nb_elt_old==_param->_size_queue[context]) 164 // bottom_new = (bottom_old+1)%_param->_size_queue[context]; 165 // else 166 // nb_elt_new ++; 167 if (nb_elt_old!=_param->_size_queue[context]) 168 nb_elt_new ++; 169 } 170 else 171 { 172 // pop 173 log_printf(TRACE,Return_Address_Stack,FUNCTION," * pop (return procedure)"); 174 175 // Test if the stack is empty 176 if (nb_elt_old>0) 177 { 178 top_new = (top_old==0)?(_param->_size_queue[context]-1):(top_old-1); 179 nb_elt_new --; 180 } 181 // no else : can't pop 182 } 183 184 // Write new pointer 185 reg_TOP [context] = top_new; 186 // reg_BOTTOM [context] = bottom_new; 187 reg_NB_ELT [context] = nb_elt_new; 188 189 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 190 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 191 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 192 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 193 182 194 // have previous miss of ifetch ? 183 195 // 2 miss : 184 196 // 1) miss predict : is very limited (local at context), can be update very quickly 185 197 // 2) miss decod : result is in commit stage ... 186 if (miss) 187 { 188 reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; 189 reg_PREDICT_TOP [context] = reg_TOP [context]; 190 reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; 198 199 // manage by Update_Fetch_Prediction_Table and Update_Prediction_Table 200 // Note : 201 // if decod miss : ifetch can have predict call and return branchement. Also, the head of decod can be false 202 203 // Tcontrol_t miss = PORT_READ(in_DECOD_MISS_PREDICTION [i]); 204 205 // if (miss) 206 // { 207 // reg_PREDICT_BOTTOM [context] = reg_BOTTOM [context]; 208 // reg_PREDICT_TOP [context] = reg_TOP [context]; 209 // reg_PREDICT_NB_ELT [context] = reg_NB_ELT [context]; 191 210 192 // Scan full assoc !!!193 for (uint32_t j=0; j<_param->_size_queue [context]; j++)194 // Test if this slot is tagged with "predict" : if true, tagged as miss195 if (reg_stack [context][j]._predict)196 {197 reg_stack [context][j]._predict = false;198 reg_stack [context][j]._miss = true;199 }200 }211 // // Scan full assoc !!! 212 // for (uint32_t j=0; j<_param->_size_queue [context]; j++) 213 // // Test if this slot is tagged with "predict" : if true, tagged as miss 214 // if (reg_stack [context][j]._predict) 215 // { 216 // reg_stack [context][j]._predict = false; 217 // reg_stack [context][j]._miss = true; 218 // } 219 // } 201 220 } 202 221 … … 207 226 if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) 208 227 { 209 throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); 210 211 212 // Tcontrol_t miss = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); 213 // // 214 // if (miss) 215 // { 216 // Tcontrol_t context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 217 // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 218 // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 219 // Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); 220 // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 221 // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 222 223 // if (push) 224 // { 225 // // // push 226 // // top_new = (top_old+1)%_param->_size_queue[context]; 227 228 // // reg_stack [context][index]._val = true; 229 // // reg_stack [context][index]._predict = false; 230 // // reg_stack [context][index]._miss = false; 231 // // reg_stack [context][index]._address = PORT_READ(in_UPDATE_ADDRESS [i]); 232 233 // } 234 // else 235 // { 236 // // //reg_stack [context][top_new]._val = ; 237 // // //reg_stack [context][top_new]._predict = ; 238 // // //reg_stack [context][top_new]._miss = ; 239 // // //reg_stack [context][top_new]._address = ; 240 // } 241 242 // // // // Mouais bof ....... 243 // // // reg_PREDICT_TOP [context] = index; 244 // } 228 log_printf(TRACE,Return_Address_Stack,FUNCTION," * UPDATE [%d] : Transaction",i); 229 230 Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; 231 Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); 232 233 log_printf(TRACE,Return_Address_Stack,FUNCTION," * context_id : %d",context_id); 234 log_printf(TRACE,Return_Address_Stack,FUNCTION," * flush : %d",flush ); 235 236 // An miss prediction on call/return = Return Address Stack is corrupted. 237 if (flush) 238 { 239 // All pointer is set at 0 240 reg_TOP [context_id] = 0; 241 // reg_BOTTOM [context_id] = 0; 242 reg_NB_ELT [context_id] = 0; 243 244 reg_PREDICT_TOP [context_id] = 0; 245 // reg_PREDICT_BOTTOM [context_id] = 0; 246 reg_PREDICT_NB_ELT [context_id] = 0; 247 } 248 else 249 { 250 // if miss_prediction -> restore queue 251 // else, the prediction is correct 252 Tcontrol_t miss_prediction = PORT_READ(in_UPDATE_MISS_PREDICTION [i]); 253 254 log_printf(TRACE,Return_Address_Stack,FUNCTION," * miss_prediction : %d",miss_prediction); 255 256 #ifdef DEBUG_TEST 257 Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 258 Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 259 log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); 260 log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); 261 262 // if (prediction_ifetch) 263 // { 264 // if (index != reg_PREDICT_TOP [context_id]) 265 // throw ERRORMORPHEO(FUNCTION,_("Index is different of predict_top")); 266 // } 267 // else 268 // { 269 // if (index != reg_TOP [context_id]) 270 // throw ERRORMORPHEO(FUNCTION,_("Index is different of top")); 271 // } 272 273 #endif 274 if (miss_prediction) 275 { 276 Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); 277 log_printf(TRACE,Return_Address_Stack,FUNCTION," * push : %d",push); 278 #ifndef DEBUG_TEST 279 Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); 280 Tcontrol_t prediction_ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); 281 log_printf(TRACE,Return_Address_Stack,FUNCTION," * index : %d",index); 282 log_printf(TRACE,Return_Address_Stack,FUNCTION," * prediction_ifetch : %d",prediction_ifetch); 283 #endif 284 285 286 Tptr_t top_old = (prediction_ifetch)?reg_PREDICT_TOP [context_id]:reg_TOP [context_id]; 287 Tptr_t top_new = top_old; 288 289 // Tptr_t bottom_old = (prediction_ifetch)?reg_PREDICT_BOTTOM [context_id]:reg_BOTTOM [context_id]; 290 // Tptr_t bottom_new = bottom_old; 291 292 Tptr_t nb_elt_old = (prediction_ifetch)?reg_PREDICT_NB_ELT [context_id]:reg_NB_ELT [context_id]; 293 Tptr_t nb_elt_new = nb_elt_old; 294 295 log_printf(TRACE,Return_Address_Stack,FUNCTION," * before"); 296 if (prediction_ifetch) 297 { 298 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_old); 299 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_old); 300 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_old); 301 } 302 else 303 { 304 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_old); 305 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_old); 306 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_old); 307 } 308 309 // if previous is push, pop the value 310 // else is previous is pop, push the poped value 311 if (push) 312 { 313 // previous is push, now must be pop 314 315 // Test if the stack is empty 316 if (nb_elt_old>0) // ?? 317 { 318 top_new = (top_old==0)?(_param->_size_queue[context_id]-1):(top_old-1); 319 nb_elt_new --; 320 } 321 } 322 else 323 { 324 // previous is pop, now must be push 325 Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); 326 327 // push : increase the top (circular) 328 // if (nb_elt_old==_param->_size_queue[context_id]) 329 // bottom_new = (bottom_old+1)%_param->_size_queue[context_id]; 330 // else 331 // nb_elt_new ++; 332 333 if (nb_elt_old!=_param->_size_queue[context_id]) 334 nb_elt_new ++; 335 336 top_new = index; 337 338 reg_stack [context_id][index]._address = address; 339 } 340 341 log_printf(TRACE,Return_Address_Stack,FUNCTION," * after"); 342 343 if (prediction_ifetch) 344 { 345 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_top : %d",top_new); 346 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_bottom : %d",bottom_new); 347 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_predict_nb_elt : %d",nb_elt_new); 348 349 reg_PREDICT_TOP [context_id] = top_new ; 350 // reg_PREDICT_BOTTOM [context_id] = bottom_new; 351 reg_PREDICT_NB_ELT [context_id] = nb_elt_new; 352 } 353 else 354 { 355 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_top : %d",top_new); 356 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_bottom : %d",bottom_new); 357 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_nb_elt : %d",nb_elt_new); 358 359 reg_TOP [context_id] = top_new ; 360 // reg_BOTTOM [context_id] = bottom_new; 361 reg_NB_ELT [context_id] = nb_elt_new; 362 } 363 } 364 } 245 365 } 246 366 } 367 368 #if defined(DEBUG_Return_Address_Stack) and DEBUG>=DEBUG_TRACE 369 log_printf(TRACE,Return_Address_Stack,FUNCTION," * Dump RAS"); 370 for (uint32_t i=0; i<_param->_nb_context; ++i) 371 { 372 log_printf(TRACE,Return_Address_Stack,FUNCTION," * Return Address Stack [%d]",i); 373 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_TOP : %d",reg_TOP [i]); 374 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); 375 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); 376 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_TOP : %d",reg_PREDICT_TOP [i]); 377 // log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_BOTTOM : %d",reg_PREDICT_BOTTOM [i]); 378 log_printf(TRACE,Return_Address_Stack,FUNCTION," * reg_PREDICT_NB_ELT : %d",reg_PREDICT_NB_ELT [i]); 379 380 for (uint32_t j=0; j<_param->_size_queue[i]; ++j) 381 log_printf(TRACE,Return_Address_Stack,FUNCTION," [%d] %.8x (%.8x)",j,reg_stack [i][j]._address,reg_stack [i][j]._address<<2); 382 } 383 #endif 247 384 248 385 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) … … 250 387 #endif 251 388 252 log_ printf(FUNC,Return_Address_Stack,FUNCTION,"End");389 log_end(Return_Address_Stack,FUNCTION); 253 390 }; 254 391
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