Changeset 100 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp
r88 r100 30 30 uint32_t bank_nb_access [_param->_nb_bank]; 31 31 Tcontrol_t commit_ack [_param->_nb_inst_commit]; 32 32 33 // Initialisation 33 34 for (uint32_t i=0; i<_param->_nb_bank; i++) … … 38 39 } 39 40 40 // commit interface 41 // commit interface -> scan all entry (Out of Order) 41 42 for (uint32_t i=0; i<_param->_nb_inst_commit; i++) 42 43 { 43 44 commit_ack [i] = false; 44 45 45 // Test if have instruction46 // Test if have valid instruction 46 47 if (PORT_READ(in_COMMIT_VAL [i])) 47 48 { 48 Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; 49 uint32_t num_bank = packet >> _param->_shift_num_bank; 49 // packet_id number can 50 Tpacket_t packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; 51 uint32_t num_bank = packet_id >> _param->_shift_num_bank; 50 52 uint32_t num_bank_access = bank_nb_access [num_bank]; 51 53 … … 60 62 internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i; 61 63 62 Tpacket_t packet_id = packet& _param->_mask_size_bank;64 Tpacket_t num_packet = packet_id & _param->_mask_size_bank; 63 65 64 66 // find the good entry !!! … … 67 69 it!=_rob[num_bank].end(); 68 70 it++) 69 if ((*it)->ptr == packet_id)71 if ((*it)->ptr == num_packet) 70 72 { 71 73 entry = (*it);
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