Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp

Timestamp:

Jan 15, 2009, 6:19:08 PM (15 years ago)

Author:

rosiere

Message:

1) Add soc test
2) fix bug (Pc management, Decod and execute, Update prediction ...)

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (modified) (9 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp

@@ -260 +260 @@
             (    internal_MEMORY_IN_ACK  == 1))
           {
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_IN [%d]",internal_MEMORY_IN_PORT);
+
             // Test operation :
             //~~~~~~~~~~~~~~~~~
@@ -440 +442 @@
             (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
           {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT transaction");
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * MEMORY_OUT[0] transaction");
 
             switch (internal_MEMORY_OUT_SELECT_QUEUE)
@@ -498 +500 @@
             (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
           {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ");
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_REQ[0]");
 
             switch (internal_DCACHE_REQ_SELECT_QUEUE)
@@ -602 +604 @@
             (    internal_DCACHE_RSP_ACK == 1))
           {
-            log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP");
+            log_printf(TRACE,Load_store_unit,FUNCTION,"  * DCACHE_RSP [0]");
 
             // don't use context_id : because there are one queue for all thread
@@ -610 +612 @@
             Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d", packet_id);
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    * original packet_id : %d"  , packet_id);
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    * rdata              : %.8x", rdata);
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    * error              : %d"  , error);
             
             if (DCACHE_RSP_IS_LOAD(packet_id) == 1)
@@ -623 +627 @@
                   throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons."));
 #endif
-                
+
+                _load_queue [packet_id]._rdata = rdata;
                 
                 if (error != DCACHE_ERROR_NONE)
@@ -639 +644 @@
                     // FIXME : convention : if bus error, the cache return the fautive address !
                     // But, the load's address is aligned !
-                    _load_queue [packet_id]._rdata = rdata;
-                
+
                     switch (_load_queue [packet_id]._state)
                       {
@@ -695 +699 @@
             uint32_t j = (*_speculative_access_queue_control)[i];
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _speculative_access_queue[j]._context_id          ,
@@ -719 +723 @@
             uint32_t j = i;
 
-            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s",
+            log_printf(TRACE,Load_store_unit,FUNCTION,"    [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s",
                        j,
                        _load_queue[j]._context_id          ,