Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp
r88 r101 18 18 log_printf(FUNC,RegisterFile,"transition","Begin"); 19 19 20 for (uint32_t i=0; i<_param->_nb_port_write; i++)20 if (_param->_have_init_value and (PORT_READ(in_NRESET) == 0)) 21 21 { 22 // Have a write? 23 if ( PORT_READ(in_WRITE_VAL[i]) == true) 24 { 22 for (uint32_t i=0; i<_param->_nb_word; ++i) 23 reg_DATA[i] = fromString<Tdata_t>(_param->_init_value); 24 } 25 else 26 { 27 for (uint32_t i=0; i<_param->_nb_port_write; i++) 28 { 29 // Have a write? 30 if ( PORT_READ(in_WRITE_VAL[i]) == true) 31 { 25 32 #ifdef STATISTICS 26 if (usage_is_set(_usage,USE_STATISTICS)) 27 (*_stat_nb_write) ++; 28 #endif 29 30 Taddress_t address; 31 if (_param->_have_port_address) 32 address = PORT_READ(in_WRITE_ADDRESS[i]); 33 else 34 address = 0; 35 36 Tdata_t data = PORT_READ(in_WRITE_DATA [i]); 37 38 log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 39 40 // Write in registerFile 41 reg_DATA[address] = data; 42 } 43 } 44 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 45 { 46 // Have a read_write? 47 if (PORT_READ(in_READ_WRITE_VAL[i]) == true) 48 { 49 if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE) 50 { 51 #ifdef STATISTICS 52 if (usage_is_set(_usage,USE_STATISTICS)) 33 if (usage_is_set(_usage,USE_STATISTICS)) 53 34 (*_stat_nb_write) ++; 54 35 #endif 55 56 Taddress_t address; 57 if (_param->_have_port_address) 58 address = PORT_READ(in_READ_WRITE_ADDRESS[i]); 59 else 60 address = 0; 61 Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); 62 63 log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 64 65 // Write in registerFile 66 reg_DATA[address] = data; 67 } 36 37 Taddress_t address = (_param->_have_port_address)?PORT_READ(in_WRITE_ADDRESS[i]):0; 38 Tdata_t data = PORT_READ(in_WRITE_DATA [i]); 39 40 log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 41 42 // Write in registerFile 43 reg_DATA[address] = data; 44 } 45 } 46 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 47 { 48 // Have a read_write? 49 if (PORT_READ(in_READ_WRITE_VAL[i]) == true) 50 { 51 if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE) 52 { 68 53 #ifdef STATISTICS 69 else 70 { 71 if (usage_is_set(_usage,USE_STATISTICS)) 72 (*_stat_nb_read) ++; 73 } 54 if (usage_is_set(_usage,USE_STATISTICS)) 55 (*_stat_nb_write) ++; 74 56 #endif 75 } 57 58 Taddress_t address = (_param->_have_port_address)?PORT_READ(in_READ_WRITE_ADDRESS[i]):0; 59 Tdata_t data = PORT_READ(in_READ_WRITE_WDATA [i]); 60 61 log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data)); 62 63 // Write in registerFile 64 reg_DATA[address] = data; 65 } 66 #ifdef STATISTICS 67 else 68 { 69 if (usage_is_set(_usage,USE_STATISTICS)) 70 (*_stat_nb_read) ++; 71 } 72 #endif 73 } 74 } 76 75 } 77 76
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