- Timestamp:
- Feb 5, 2009, 12:18:31 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine
- Files:
-
- 22 edited
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Commit_unit/SelfTest/src/test.cpp (modified) (7 diffs)
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Commit_unit/include/Commit_unit.h (modified) (3 diffs)
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Commit_unit/include/Types.h (modified) (4 diffs)
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Commit_unit/src/Commit_unit_allocation.cpp (modified) (3 diffs)
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Commit_unit/src/Commit_unit_deallocation.cpp (modified) (3 diffs)
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Commit_unit/src/Commit_unit_genMealy_retire.cpp (modified) (1 diff)
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Commit_unit/src/Commit_unit_genMoore.cpp (modified) (2 diffs)
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Commit_unit/src/Commit_unit_transition.cpp (modified) (17 diffs)
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Rename_unit/Rename_select/SelfTest/src/test.cpp (modified) (9 diffs)
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Rename_unit/Rename_select/include/Rename_select.h (modified) (2 diffs)
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Rename_unit/Rename_select/src/Rename_select.cpp (modified) (2 diffs)
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Rename_unit/Rename_select/src/Rename_select_allocation.cpp (modified) (2 diffs)
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Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (modified) (2 diffs)
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Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (modified) (1 diff)
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Rename_unit/SelfTest/src/test.cpp (modified) (6 diffs)
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Rename_unit/include/Rename_unit.h (modified) (2 diffs)
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Rename_unit/src/Rename_unit_allocation.cpp (modified) (4 diffs)
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Rename_unit/src/Rename_unit_deallocation.cpp (modified) (2 diffs)
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SelfTest/src/test.cpp (modified) (6 diffs)
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include/OOO_Engine.h (modified) (2 diffs)
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src/OOO_Engine_allocation.cpp (modified) (6 diffs)
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src/OOO_Engine_deallocation.cpp (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r104 r105 68 68 ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 69 69 ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ," in_INSERT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 71 71 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ," in_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 153 153 ALLOC_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); 154 154 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); 155 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t ); 155 156 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); 156 157 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 205 206 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 206 207 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 207 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS 208 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 208 209 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 209 210 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 302 303 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); 303 304 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS ); 305 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL ); 304 306 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR ); 305 307 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); … … 418 420 in_INSERT_IS_DELAY_SLOT [i][j]->write(0); 419 421 in_INSERT_NO_EXECUTE [i][j]->write(0); 420 in_INSERT_ADDRESS 422 in_INSERT_ADDRESS_NEXT [i][j]->write(addr); 421 423 in_INSERT_EXCEPTION [i][j]->write(0); 422 424 in_INSERT_EXCEPTION_USE [i][j]->write(0); … … 615 617 DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 616 618 DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 617 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS 619 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 618 620 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 619 621 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 698 700 DELETE_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ); 699 701 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS ); 702 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ); 700 703 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ); 701 704 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r104 r105 83 83 public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] 84 84 public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] 85 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS 85 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert] 86 86 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] 87 87 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] … … 179 179 public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; 180 180 public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; 181 public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EPCR_VAL ; 181 182 public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; 182 183 public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; … … 229 230 private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] 230 231 231 232 //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] 232 233 private : Taddress_t ** reg_PC_CURRENT ;//[nb_front_end][nb_context] 233 234 private : Taddress_t ** reg_PC_CURRENT_IS_DS ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r100 r105 42 42 ROB_END_BRANCH_MISS_SPECULATIVE, // 43 43 ROB_END_BRANCH_MISS , // 44 ROB_END_LOAD_MISS_SPECULATIVE , // 45 ROB_END_LOAD_MISS_UPDATE , // 46 ROB_END_LOAD_MISS , // 44 47 ROB_END_MISS , // 45 48 ROB_END_EXCEPTION_WAIT_HEAD , // 46 ROB_END_EXCEPTION // 49 ROB_END_EXCEPTION_UPDATE , // 50 ROB_END_EXCEPTION // 47 51 } rob_state_t; 48 52 … … 58 62 public : Toperation_t operation ; 59 63 public : Tcontrol_t is_delay_slot ; 60 64 //public : Tgeneral_data_t address ; 61 65 public : Tcontrol_t use_store_queue ; 62 66 public : Tcontrol_t use_load_queue ; … … 86 90 public : Tspecial_data_t flags ; 87 91 public : Tcontrol_t no_sequence ; 88 public : Tgeneral_data_t data_commit ; // branch's destination 92 //public : Tgeneral_data_t data_commit ; // branch's destination 93 public : Taddress_t address_next ; 89 94 90 95 // public : entry_t (uint32_t ptr , … … 177 182 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break; 178 183 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS : return "ROB_END_BRANCH_MISS" ; break; 184 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS_SPECULATIVE : return "ROB_END_LOAD_MISS_SPECULATIVE" ; break; 185 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS_UPDATE : return "ROB_END_LOAD_MISS_UPDATE" ; break; 186 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS : return "ROB_END_LOAD_MISS" ; break; 179 187 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS : return "ROB_END_MISS" ; break; 180 188 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "ROB_END_EXCEPTION_WAIT_HEAD" ; break; 189 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_UPDATE : return "ROB_END_EXCEPTION_UPDATE" ; break; 181 190 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "ROB_END_EXCEPTION" ; break; 182 191 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r104 r105 71 71 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 74 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 75 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 192 192 ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 193 193 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 194 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 194 195 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 195 196 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); … … 284 285 ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 285 286 286 287 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 287 288 ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 288 289 ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r104 r105 39 39 DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 40 40 DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 41 DELETE2_SIGNAL( in_INSERT_ADDRESS 41 DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 42 42 DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 43 43 DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); … … 129 129 DELETE_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,1 ); 130 130 DELETE_SIGNAL (out_UPDATE_ADDRESS ,_param->_size_instruction_address ); 131 DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,1 ); 131 132 DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); 132 133 DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,1 ); … … 188 189 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 189 190 DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 190 191 // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 191 192 DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); 192 193 DELETE2(reg_PC_CURRENT_IS_DS ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r104 r105 80 80 (state == ROB_END_KO ) or 81 81 (state == ROB_END_BRANCH_MISS) or 82 (state == ROB_END_LOAD_MISS ) or 82 83 (state == ROB_END_MISS )// or 83 84 // (state == ROB_END_EXCEPTION) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r104 r105 99 99 if (_param->_have_port_depth) 100 100 PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); 101 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry-> data_commit);101 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->address_next ); 102 102 // PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i],(entry->flags&FLAG_F)!=0); 103 103 PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); … … 117 117 // =================================================================== 118 118 { 119 Tcontrol_t val = false; 120 121 if (not _rob[reg_NUM_BANK_HEAD].empty()) 122 { 123 entry_t * entry = _rob [reg_NUM_BANK_HEAD].front(); 124 rob_state_t state = entry->state; 125 126 val = (state == ROB_END_EXCEPTION); 127 128 if (val) 129 { 130 throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 131 } 132 } 119 internal_UPDATE_VAL = 0; 120 internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD; 121 122 if (not _rob[internal_UPDATE_NUM_BANK].empty()) 123 { 124 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); 125 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",internal_UPDATE_NUM_BANK); 126 127 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 128 129 switch (entry->state) 130 { 131 case ROB_END_EXCEPTION_UPDATE : 132 { 133 internal_UPDATE_VAL = 1; 134 throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 135 break; 136 } 137 case ROB_END_LOAD_MISS_UPDATE : 138 { 139 log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); 140 141 internal_UPDATE_VAL = 1; 142 143 Tcontext_t front_end_id = entry->front_end_id; 144 Tcontext_t context_id = entry->context_id ; 145 146 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 147 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 148 149 if (_param->_have_port_front_end_id) 150 PORT_WRITE(out_UPDATE_FRONT_END_ID ,front_end_id); 151 if (_param->_have_port_context_id) 152 PORT_WRITE(out_UPDATE_CONTEXT_ID ,context_id ); 153 if (_param->_have_port_depth) 154 PORT_WRITE(out_UPDATE_DEPTH ,entry->depth); 155 PORT_WRITE(out_UPDATE_TYPE ,EVENT_TYPE_LOAD_MISS_SPECULATION); 156 // PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,reg_PC_CURRENT_IS_DS [front_end_id][context_id]); 157 // PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_CURRENT [front_end_id][context_id]); 158 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id]); 159 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,reg_PC_NEXT [front_end_id][context_id]); 160 // PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); 161 // // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); 162 163 PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,0); 164 PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_NEXT [front_end_id][context_id]); 165 PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,0); 166 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,); 167 PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); 168 // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); 169 170 break; 171 } 172 default : 173 { 174 // internal_UPDATE_VAL = 0; 175 } 176 } 177 } 178 179 PORT_WRITE(out_UPDATE_VAL, internal_UPDATE_VAL); 180 181 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE (end)"); 133 182 } 134 183 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r104 r105 51 51 reg_PC_CURRENT_IS_DS [i][j] = 0; 52 52 reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; 53 //reg_PC_NEXT [i][j] = (0x100+4)>>2;53 reg_PC_NEXT [i][j] = (0x100+4)>>2; 54 54 } 55 55 … … 138 138 entry->operation = operation; 139 139 entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); 140 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);140 // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 141 141 entry->exception = exception; 142 142 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); … … 162 162 entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); 163 163 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 164 entry->no_sequence = type == TYPE_BRANCH; 165 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 164 166 165 167 // Test if exception : … … 295 297 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 296 298 // Store OK, Load and other instruction 297 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_ MISS:ROB_END_OK_SPECULATIVE); break;}299 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} 298 300 default : 299 301 { … … 304 306 305 307 // update Re Order Buffer 306 entry->state = state; 307 entry->exception = exception; 308 entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); 309 entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); 310 entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]); 308 entry->state = state; 309 entry->exception = exception; 310 entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); 311 entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); 312 // jalr, jr : address_dest is in register 313 if ((entry->type == TYPE_BRANCH) and 314 (entry->operation == OPERATION_BRANCH_L_JALR) and 315 (entry->read_rb)) 316 entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); 311 317 } 312 318 } … … 345 351 Ttype_t type = entry->type ; 346 352 347 if (state == ROB_END_BRANCH_MISS) 353 if ((state == ROB_END_OK ) or // LOAD_MISS 354 // (state == ROB_END_KO ) or 355 (state == ROB_END_BRANCH_MISS)// or 356 // (state == ROB_END_LOAD_MISS ) or 357 // (state == ROB_END_MISS ) or 358 // (state == ROB_END_EXCEPTION ) 359 ) 360 { 361 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 362 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 363 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; 364 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 365 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 366 } 367 368 if ((state == ROB_END_BRANCH_MISS) or 369 (state == ROB_END_LOAD_MISS)) 348 370 { 349 371 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 350 372 reg_EVENT_FLUSH [front_end_id][context_id] = true; 351 352 // TODO Compute address !!!!!!!!!!!353 373 } 354 374 … … 412 432 // =====[ UPDATE ]==================================================== 413 433 // =================================================================== 414 { 415 // Not yet implemented 416 } 434 if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) 435 { 436 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); 437 438 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 439 440 switch (entry->state) 441 { 442 // case ROB_END_EXCEPTION_UPDATE : 443 // { 444 // entry->state = ROB_END_KO; 445 // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 446 // break; 447 // } 448 case ROB_END_LOAD_MISS_UPDATE : 449 { 450 log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); 451 452 entry->state = ROB_END_LOAD_MISS; 453 break; 454 } 455 default : 456 { 457 throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); 458 break; 459 } 460 } 461 462 } 417 463 418 464 // =================================================================== … … 438 484 439 485 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 440 //Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;441 //Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);486 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 487 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 442 488 443 489 // is a valid instruction ? … … 455 501 // ....... max ...X... min ....... KO 456 502 457 // Tcontrol_t is_valid = ((depth == depth_min) or458 // depth_full or459 // ((depth_min <= depth_max)?460 // ((depth >= depth_min) and (depth <=depth_max)):461 // ((depth >= depth_min) or (depth <=depth_max))));462 463 503 bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 464 Tcontrol_t is_valid = ((depth == depth_min) and not flush); 504 505 Tcontrol_t is_valid = (((depth == depth_min) or 506 depth_full or 507 ((depth_min <= depth_max)? 508 ((depth >= depth_min) and (depth <=depth_max)): 509 ((depth >= depth_min) or (depth <=depth_max)))) 510 and not flush); 511 512 // Tcontrol_t is_valid = ((depth == depth_min) and not flush); 465 513 466 514 log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); 467 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ",is_valid);515 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); 468 516 log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); 469 517 log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); 470 // log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 518 log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 519 log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); 471 520 log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 472 521 … … 481 530 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 482 531 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 532 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 483 533 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 484 534 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} … … 498 548 case ROB_END_KO : 499 549 case ROB_END_BRANCH_MISS : 550 case ROB_END_LOAD_MISS_UPDATE : 551 case ROB_END_LOAD_MISS : 552 case ROB_END_EXCEPTION_UPDATE : 500 553 case ROB_END_EXCEPTION : 501 554 default : … … 517 570 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 518 571 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 572 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 519 573 default : {break;} 520 574 } … … 528 582 switch (state) 529 583 { 530 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}531 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION ; break;}584 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 585 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 532 586 default : {break;} 533 587 } … … 549 603 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 550 604 { 551 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] num_inst_all : %d, num_inst_mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);552 605 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); 606 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); 607 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); 608 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x - %d %d",reg_PC_CURRENT [i][j], reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 609 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x",reg_PC_NEXT [i][j]); 553 610 } 554 611 … … 567 624 it++) 568 625 { 569 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %. 8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",626 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 570 627 x, 571 628 (*it)->front_end_id , … … 575 632 (*it)->type , 576 633 (*it)->operation , 577 578 634 // (*it)->address , 635 // (*it)->address << 2 , 579 636 (*it)->is_delay_slot , 580 637 (*it)->use_store_queue , … … 603 660 (*it)->num_reg_re_phy_new ); 604 661 605 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x ",662 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", 606 663 (*it)->exception_use , 607 664 (*it)->exception , 608 665 (*it)->flags , 609 666 (*it)->no_sequence , 610 (*it)->data_commit 667 (*it)->address_next , 668 (*it)->address_next<<2 611 669 ); 612 670 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp
r97 r105 59 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 62 62 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 63 63 ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 84 84 ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); 85 85 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); 86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS",Taddress_t ,_param->_nb_inst_rename);86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,"out_RENAME_OUT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_inst_rename); 87 87 ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); 88 88 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IMMEDIAT ,"out_RENAME_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_rename); … … 121 121 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 122 122 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 123 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS 123 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 124 124 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 125 125 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 149 149 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename); 150 150 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IS_DELAY_SLOT,_param->_nb_inst_rename); 151 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS 151 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename); 152 152 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename); 153 153 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IMMEDIAT ,_param->_nb_inst_rename); … … 213 213 in_RENAME_IN_NO_EXECUTE [i][j]->write(rand()%2); 214 214 in_RENAME_IN_IS_DELAY_SLOT[i][j]->write(rand()%2); 215 in_RENAME_IN_ADDRESS 215 in_RENAME_IN_ADDRESS_NEXT [i][j]->write(address++ ); 216 216 in_RENAME_IN_HAS_IMMEDIAT [i][j]->write(range<Tcontrol_t >(rand(),1 )); 217 217 in_RENAME_IN_IMMEDIAT [i][j]->write(range<Tgeneral_data_t >(rand(),_param->_size_general_data )); … … 259 259 260 260 // Test 261 address = out_RENAME_OUT_ADDRESS [i]->read();261 address = out_RENAME_OUT_ADDRESS_NEXT [i]->read(); 262 262 263 263 TEST(bool, address<nb_rename_in, true); … … 269 269 for (uint32_t x=0; x<_param->_nb_front_end; x++) 270 270 for (uint32_t y=0; y<_param->_nb_inst_decod[x]; y++) 271 if (in_RENAME_IN_ADDRESS [x][y]->read() == address)271 if (in_RENAME_IN_ADDRESS_NEXT [x][y]->read() == address) 272 272 { 273 273 find = true; … … 329 329 delete [] in_RENAME_IN_NO_EXECUTE ; 330 330 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 331 delete [] in_RENAME_IN_ADDRESS 331 delete [] in_RENAME_IN_ADDRESS_NEXT ; 332 332 delete [] in_RENAME_IN_HAS_IMMEDIAT ; 333 333 delete [] in_RENAME_IN_IMMEDIAT ; … … 354 354 delete [] out_RENAME_OUT_NO_EXECUTE ; 355 355 delete [] out_RENAME_OUT_IS_DELAY_SLOT; 356 delete [] out_RENAME_OUT_ADDRESS 356 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 357 357 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; 358 358 delete [] out_RENAME_OUT_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h
r97 r105 76 76 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 78 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS 78 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 102 102 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] 103 103 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] 104 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS 104 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS_NEXT ;//[nb_inst_rename] 105 105 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] 106 106 public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_IMMEDIAT ;//[nb_inst_rename] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp
r88 r105 97 97 << (*(in_RENAME_IN_NO_EXECUTE [i][j])) 98 98 << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])) 99 << (*(in_RENAME_IN_ADDRESS 99 << (*(in_RENAME_IN_ADDRESS_NEXT [i][j])) 100 100 << (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])) 101 101 << (*(in_RENAME_IN_IMMEDIAT [i][j])) … … 163 163 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_VAL [i][j])); 164 164 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])); 165 (*(out_RENAME_OUT_ADDRESS 166 (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_ADDRESS[i][j]));165 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_VAL [i][j])); 166 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_ADDRESS_NEXT [i][j])); 167 167 (*(out_RENAME_OUT_HAS_IMMEDIAT [x])) (*(in_RENAME_IN_VAL [i][j])); 168 168 (*(out_RENAME_OUT_HAS_IMMEDIAT [x])) (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
r97 r105 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 99 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address );101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp
r88 r105 40 40 delete [] in_RENAME_IN_NO_EXECUTE ; 41 41 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 42 delete [] in_RENAME_IN_ADDRESS 42 delete [] in_RENAME_IN_ADDRESS_NEXT ; 43 43 delete [] in_RENAME_IN_HAS_IMMEDIAT ; 44 44 delete [] in_RENAME_IN_IMMEDIAT ; … … 66 66 delete [] out_RENAME_OUT_TYPE ; 67 67 delete [] out_RENAME_OUT_OPERATION ; 68 delete [] out_RENAME_OUT_ADDRESS 68 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 69 69 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; 70 70 delete [] out_RENAME_OUT_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
r88 r105 75 75 PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); 76 76 PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y])); 77 PORT_WRITE(out_RENAME_OUT_ADDRESS [i],PORT_READ(in_RENAME_IN_ADDRESS[x][y]));77 PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT [x][y])); 78 78 PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT [x][y])); 79 79 PORT_WRITE(out_RENAME_OUT_IMMEDIAT [i],PORT_READ(in_RENAME_IN_IMMEDIAT [x][y])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp
r104 r105 57 57 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);59 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 81 81 ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,"out_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_insert); 82 82 ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,"out_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_insert); 83 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS ,"out_INSERT_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_insert);83 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,"out_INSERT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_insert); 84 84 ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,"out_INSERT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_insert); 85 85 ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT ,"out_INSERT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_insert); … … 155 155 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 156 156 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 157 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS 157 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 158 158 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 159 159 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 183 183 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 184 184 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 185 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS 185 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 186 186 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); 187 187 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); … … 297 297 DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 298 298 DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 299 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS 299 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 300 300 DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 301 301 DELETE2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 322 322 DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 323 323 DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 324 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS 324 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 325 325 DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); 326 326 DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
r104 r105 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 80 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS 80 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 82 82 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 104 104 public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] 105 105 public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] 106 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS 106 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS_NEXT ;//[nb_inst_insert] 107 107 public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] 108 108 public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r104 r105 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 99 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address );101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 301 301 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT", 302 302 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT"); 303 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS ",304 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS ");303 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , 304 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); 305 305 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" , 306 306 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); … … 349 349 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_DEPTH" , 350 350 dest,"out_INSERT_" +toString(i)+"_DEPTH" ); 351 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS ",352 dest,"out_INSERT_" +toString(i)+"_ADDRESS ");351 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS_NEXT", 352 dest,"out_INSERT_" +toString(i)+"_ADDRESS_NEXT"); 353 353 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_HAS_IMMEDIAT", 354 354 dest,"out_INSERT_" +toString(i)+"_HAS_IMMEDIAT"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
r104 r105 37 37 DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 38 38 DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 39 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data);39 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 40 40 DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 41 41 DELETE2_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); … … 62 62 DELETE1_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert,1 ); 63 63 DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); 64 DELETE1_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_general_data);64 DELETE1_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert,_param->_size_instruction_address ); 65 65 DELETE1_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert,1 ); 66 66 DELETE1_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r101 r105 57 57 ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ," in_RENAME_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 ALLOC2_SC_SIGNAL( in_RENAME_IMMEDIAT ," in_RENAME_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 143 143 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 144 144 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); 145 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 145 146 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 146 147 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 193 194 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 194 195 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 195 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS 196 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 196 197 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 197 198 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 292 293 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); 293 294 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); 295 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 294 296 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); 295 297 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); … … 376 378 DELETE2_SC_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 377 379 DELETE2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 378 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS 380 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 379 381 DELETE2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 380 382 DELETE2_SC_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 462 464 DELETE_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ); 463 465 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ); 466 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 464 467 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ); 465 468 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r101 r105 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 79 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS 79 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 169 169 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_IS_DELAY_SLOT ; 170 170 public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS ; 171 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 171 172 public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EPCR ; 172 173 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r104 r105 66 66 _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 67 67 _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS",Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 182 182 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 183 183 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 184 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); 184 185 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 185 186 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); … … 412 413 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT", 413 414 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT"); 414 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS ",415 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS ");415 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS_NEXT" , 416 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" ); 416 417 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_HAS_IMMEDIAT" , 417 418 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_HAS_IMMEDIAT" ); … … 476 477 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , 477 478 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); 478 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS ",479 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS ");479 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS_NEXT" , 480 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); 480 481 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_EXCEPTION_USE" , 481 482 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_EXCEPTION_USE" ); … … 754 755 755 756 // in_INSERT_DEPTH - component_rename_unit 756 // in_INSERT_ADDRESS 757 // in_INSERT_ADDRESS_NEXT - component_rename_unit 757 758 // in_INSERT_EXCEPTION_USE - component_rename_unit 758 759 // in_INSERT_EXCEPTION - component_rename_unit … … 946 947 PORT_MAP(_component,src ,"out_UPDATE_IS_DELAY_SLOT" ,dest,"out_COMMIT_EVENT_IS_DELAY_SLOT" ); 947 948 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS" ,dest,"out_COMMIT_EVENT_ADDRESS" ); 949 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EPCR_VAL",dest,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL"); 948 950 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EPCR" ,dest,"out_COMMIT_EVENT_ADDRESS_EPCR" ); 949 951 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EEAR_VAL",dest,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
r101 r105 36 36 DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 37 37 DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 38 DELETE2_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data);38 DELETE2_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 39 39 DELETE2_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 40 40 DELETE2_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data ); … … 84 84 DELETE2_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_exception ); 85 85 DELETE2_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); 86 DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_ general_data);86 DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_instruction_address ); 87 87 DELETE2_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data ); 88 88 … … 110 110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); 111 111 DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); 112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_ general_data);112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 113 113 DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); 114 114 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); … … 122 122 DELETE_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); 123 123 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); 124 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); 124 125 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); 125 126 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); … … 128 129 DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 129 130 DELETE2_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 130 DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_ general_data);131 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_ general_data);131 DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_instruction_address); 132 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_instruction_address); 132 133 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 133 134 DELETE2_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end,_param->_nb_context[it1],1 );
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