Changeset 105
- Timestamp:
- Feb 5, 2009, 12:18:31 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 71 edited
- 9 copied
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp
r98 r105 72 72 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end); 73 73 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"out_COMMIT_EVENT_FRONT_END_ADDRESS ",Taddress_t ,_param->_nb_front_end); 74 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ",Tcontrol_t ,_param->_nb_front_end); 74 75 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ",Taddress_t ,_param->_nb_front_end); 75 76 ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_front_end); … … 83 84 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ," in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_ooo_engine); 84 85 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine); 86 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); 85 87 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine); 86 88 ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); … … 208 210 INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end); 209 211 INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end); 212 INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ,_param->_nb_front_end); 210 213 INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end); 211 214 INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end); … … 222 225 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine); 223 226 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine); 227 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ,_param->_nb_ooo_engine); 224 228 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine); 225 229 INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); … … 421 425 in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i]->write(rand()%2); 422 426 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i]->write(range<Taddress_t>(rand(),_param->_size_instruction_address)); 427 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL[i]->write(rand()%2); 423 428 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i]->write(range<Taddress_t>(rand(),_param->_size_instruction_address)); 424 429 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL[i]->write(rand()%2); … … 549 554 TEST(Taddress_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS [x]->read(), 550 555 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i]->read()); 556 TEST(Tcontrol_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL [x]->read(), 557 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL[i]->read()); 551 558 TEST(Taddress_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR [x]->read(), 552 559 in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i]->read()); … … 691 698 DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end); 692 699 DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end); 700 DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ,_param->_nb_front_end); 693 701 DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end); 694 702 DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end); … … 702 710 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine); 703 711 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine); 712 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ,_param->_nb_ooo_engine); 704 713 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine); 705 714 DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h
r98 r105 93 93 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ;//[nb_front_end] 94 94 public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS ;//[nb_front_end] 95 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ;//[nb_front_end] 95 96 public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ;//[nb_front_end] 96 97 public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ;//[nb_front_end] … … 105 106 public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ;//[nb_ooo_engine] 106 107 public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine] 108 public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ;//[nb_ooo_engine] 107 109 public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ;//[nb_ooo_engine] 108 110 public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ;//[nb_ooo_engine] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp
r98 r105 138 138 << (*(in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i])) 139 139 << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i])) 140 << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL [i])) 140 141 << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i])) 141 142 << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL [i])) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp
r98 r105 97 97 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); 98 98 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); 99 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1); 99 100 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); 100 101 ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); … … 113 114 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); 114 115 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); 116 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1); 115 117 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); 116 118 ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp
r98 r105 52 52 DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end,1); 53 53 DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_size_instruction_address); 54 DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL ,_param->_nb_front_end,1); 54 55 DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end,_param->_size_spr); 55 56 DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end,1); … … 64 65 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine,1); 65 66 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_size_instruction_address); 67 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL ,_param->_nb_ooo_engine,1); 66 68 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine,_param->_size_spr); 67 69 DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_commit_event.cpp
r88 r105 51 51 PORT_WRITE(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i])); 52 52 PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i])); 53 PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL [i])); 53 54 PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i])); 54 55 PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL [i])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl.cpp
r103 r105 33 33 (_param->_size_queue, 34 34 _param->_size_internal_queue, 35 _param->_nb_bypass_write 35 _param->_nb_bypass_write, 36 false, 37 false 36 38 ); 37 39 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
r101 r105 73 73 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 74 74 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); 75 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 75 76 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 76 77 ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 155 156 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); 156 157 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS ); 158 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 157 159 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); 158 160 INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); … … 214 216 215 217 const bool test1 = true; 216 const bool test2 = true;218 const bool test2 = false; 217 219 const bool test3 = true; 218 220 const bool test4 = true; … … 925 927 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 926 928 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 929 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0); 927 930 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 928 931 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); … … 1019 1022 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 1020 1023 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 1024 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(0); 1021 1025 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 1022 1026 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); … … 1113 1117 in_COMMIT_EVENT_ADDRESS ->write(0xa00); 1114 1118 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); 1119 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1); 1115 1120 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); 1116 1121 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); … … 1207 1212 in_COMMIT_EVENT_ADDRESS ->write(0xd00); 1208 1213 in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); 1214 in_COMMIT_EVENT_ADDRESS_EPCR_VAL ->write(1); 1209 1215 in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); 1210 1216 in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); … … 1325 1331 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ); 1326 1332 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ); 1333 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 1327 1334 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ); 1328 1335 DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
r101 r105 91 91 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_IS_DELAY_SLOT ; 92 92 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS ; 93 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 93 94 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; 94 95 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Types.h
r101 r105 25 25 typedef enum 26 26 { 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_ADDR , // update address manager 32 CONTEXT_STATE_KO_MISS_WAITEND , // wait end of event (miss (branch, load)) 33 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 34 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 35 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 36 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 37 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 38 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 39 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 40 CONTEXT_STATE_KO_CSYNC_FLUSH , 41 CONTEXT_STATE_KO_CSYNC_ADDR , 42 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 43 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 44 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 27 CONTEXT_STATE_OK , // none event 28 CONTEXT_STATE_KO_EXCEP , // wait end of event (exception) 29 CONTEXT_STATE_KO_EXCEP_ADDR , // update address manager 30 CONTEXT_STATE_KO_EXCEP_SPR , // update spr (epc, esr, sr[DSX]) 31 CONTEXT_STATE_KO_MISS_BRANCH_ADDR , // update address manager 32 CONTEXT_STATE_KO_MISS_BRANCH_WAITEND, // wait end of event (miss branch) 33 CONTEXT_STATE_KO_MISS_LOAD_ADDR , // update address manager 34 CONTEXT_STATE_KO_MISS_LOAD_WAITEND , // wait end of event (miss load)) 35 // CONTEXT_STATE_KO_MSYNC , // wait completion of all memory operation 36 // CONTEXT_STATE_KO_MSYNC_ISSUE , // issue msync operation 37 CONTEXT_STATE_KO_MSYNC_EXEC , // wait completion of msync operation 38 // CONTEXT_STATE_KO_PSYNC , // wait completion of all operation and after flush pipeline 39 CONTEXT_STATE_KO_PSYNC_FLUSH , // wait completion of all 40 CONTEXT_STATE_KO_PSYNC_ADDR , // wait completion of all 41 // CONTEXT_STATE_KO_CSYNC , // wait completion of all operation and after flush pipeline and flush ALL units (MMU, cache ...) 42 CONTEXT_STATE_KO_CSYNC_FLUSH , 43 CONTEXT_STATE_KO_CSYNC_ADDR , 44 // CONTEXT_STATE_KO_SPR , // wait completion of all operation 45 // CONTEXT_STATE_KO_SPR_ISSUE , // issue spr's access 46 CONTEXT_STATE_KO_SPR_EXEC // wait completion of all operation (spr access) 45 47 } context_state_t; 46 48 … … 56 58 switch (x) 57 59 { 58 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 59 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 60 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 61 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_ADDR : return "context_state_ko_miss_addr" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_WAITEND : return "context_state_ko_miss_waitend"; break; 64 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 65 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 67 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 68 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 69 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 70 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 71 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 73 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 60 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_OK : return "context_state_ok" ; break; 61 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP : return "context_state_ko_excep" ; break; 62 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_ADDR : return "context_state_ko_excep_addr" ; break; 63 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_EXCEP_SPR : return "context_state_ko_excep_spr" ; break; 64 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_ADDR : return "context_state_ko_miss_branch_addr" ; break; 65 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : return "context_state_ko_miss_branch_waitend"; break; 66 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_ADDR : return "context_state_ko_miss_load_addr" ; break; 67 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MISS_LOAD_WAITEND : return "context_state_ko_miss_load_waitend" ; break; 68 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC : return "context_state_ko_msync" ; break; 69 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_ISSUE : return "context_state_ko_msync_issue" ; break; 70 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_MSYNC_EXEC : return "context_state_ko_msync_exec" ; break; 71 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC : return "context_state_ko_psync" ; break; 72 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_FLUSH : return "context_state_ko_psync_flush" ; break; 73 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_PSYNC_ADDR : return "context_state_ko_psync_addr" ; break; 74 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC : return "context_state_ko_csync" ; break; 75 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_FLUSH : return "context_state_ko_csync_flush" ; break; 76 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_CSYNC_ADDR : return "context_state_ko_csync_addr" ; break; 77 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR : return "context_state_ko_spr" ; break; 78 // case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_ISSUE : return "context_state_ko_spr_issue" ; break; 79 case morpheo::behavioural::core::multi_front_end::front_end::context_state::CONTEXT_STATE_KO_SPR_EXEC : return "context_state_ko_spr_exec" ; break; 76 80 default : return "" ; break; 77 81 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
r98 r105 95 95 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 96 96 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 97 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 97 98 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 98 99 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
r98 r105 53 53 DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1); 54 54 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address); 55 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,_param->_size_instruction_address); 55 56 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); 56 57 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_size_instruction_address); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
r101 r105 31 31 context_state_t state = reg_STATE [i]; 32 32 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or 34 (state == CONTEXT_STATE_KO_MISS_ADDR ) or 35 (state == CONTEXT_STATE_KO_PSYNC_ADDR) or 33 Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR ) or 34 (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or 35 (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or 36 (state == CONTEXT_STATE_KO_PSYNC_ADDR ) or 36 37 (state == CONTEXT_STATE_KO_CSYNC_ADDR)); 37 38 … … 40 41 Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); 41 42 Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; 42 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);43 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ ADDR) and (reg_EVENT_IS_DS_TAKE [i]);43 Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); 44 Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); 44 45 // excep : address exception 45 46 // miss : address delay_slot, and address dest … … 51 52 switch (state) 52 53 { 53 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 54 case CONTEXT_STATE_KO_MISS_ADDR : (type = EVENT_TYPE_MISS_SPECULATION ); break; 55 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 56 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 57 default : (type = EVENT_TYPE_NONE ); break; 54 case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; 55 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: (type = EVENT_TYPE_BRANCH_MISS_SPECULATION); break; 56 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : (type = EVENT_TYPE_LOAD_MISS_SPECULATION ); break; 57 case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; 58 case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; 59 default : (type = EVENT_TYPE_NONE ); break; 58 60 } 59 61 // (type = EVENT_TYPE_SPR_ACCESS ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp
r101 r105 65 65 break; 66 66 } 67 case CONTEXT_STATE_KO_MISS_ WAITEND :67 case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND : 68 68 { 69 69 // Wait end of all instruction … … 71 71 72 72 // state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod) 73 state = CONTEXT_STATE_KO_MISS_ADDR; 73 state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 74 break; 75 } 76 case CONTEXT_STATE_KO_MISS_LOAD_WAITEND : 77 { 78 // Wait end of all instruction 79 if (inst_all == 0) 80 state = CONTEXT_STATE_KO_MISS_LOAD_ADDR; 81 74 82 break; 75 83 } … … 79 87 break; 80 88 } 81 case CONTEXT_STATE_KO_MISS_ADDR : 89 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR : 90 { 91 // nothing, wait the update of internal register (pc) 92 break; 93 } 94 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 82 95 { 83 96 // nothing, wait the update of internal register (pc) … … 198 211 199 212 // priority : miss > excep > spr/sync 200 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0);213 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == EVENT_TYPE_EXCEPTION)?1:0); 201 214 uint8_t priority1 = 2; // miss 202 215 … … 212 225 { 213 226 Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); 214 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_ ADDR;215 reg_STATE [i] = CONTEXT_STATE_KO_MISS_ WAITEND; //@@@ TODO : make MISS fast (miss decod)227 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR; 228 reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod) 216 229 reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot 217 230 reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next … … 249 262 250 263 // miss > excep > spr/sync 251 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);264 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 252 265 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; 253 266 … … 258 271 bool is_valid = ((state == CONTEXT_STATE_OK) or 259 272 (depth1< depth0) or 260 ((depth1==depth0) and (priority1> priority0)));273 ((depth1==depth0) and (priority1>=priority0))); 261 274 262 275 if (is_valid) … … 325 338 } 326 339 case EVENT_TYPE_NONE : 327 case EVENT_TYPE_MISS_SPECULATION : 328 case EVENT_TYPE_BRANCH_NO_ACCURATE : 340 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 341 case EVENT_TYPE_LOAD_MISS_SPECULATION : 342 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 329 343 default : 330 344 { … … 359 373 Tdepth_t depth_max = _param->_array_size_depth [context]; 360 374 361 // 362 // 375 // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); 376 // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); 363 377 Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); 364 378 Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); … … 368 382 369 383 // miss > excep > spr/sync 370 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);371 uint8_t priority1 = 1; // exception384 uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 385 uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION) 372 386 373 387 // is_valid = can modify local information … … 377 391 bool is_valid = ((state == CONTEXT_STATE_OK) or 378 392 (depth1< depth0) or 379 ((depth1==depth0) and (priority1> priority0)));393 ((depth1==depth0) and (priority1>=priority0))); 380 394 381 395 if (is_valid) … … 386 400 switch (type) 387 401 { 388 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 389 case EVENT_TYPE_SPR_ACCESS : 390 case EVENT_TYPE_MSYNC : 391 case EVENT_TYPE_PSYNC : 392 case EVENT_TYPE_CSYNC : 393 case EVENT_TYPE_NONE : 394 case EVENT_TYPE_MISS_SPECULATION : 395 case EVENT_TYPE_BRANCH_NO_ACCURATE : 402 case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} 403 case EVENT_TYPE_LOAD_MISS_SPECULATION : {state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND; break;} 404 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 405 case EVENT_TYPE_SPR_ACCESS : 406 case EVENT_TYPE_MSYNC : 407 case EVENT_TYPE_PSYNC : 408 case EVENT_TYPE_CSYNC : 409 case EVENT_TYPE_NONE : 410 // case EVENT_TYPE_BRANCH_NO_ACCURATE : 396 411 default : 397 412 { … … 402 417 reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); 403 418 reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); 404 reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;419 reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 405 420 reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); 406 421 reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); 407 422 reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); 408 //reg_EVENT_IS_DS_TAKE [context] = 0;423 reg_EVENT_IS_DS_TAKE [context] = 0; 409 424 reg_EVENT_DEPTH [context] = depth; 410 425 } … … 435 450 436 451 // // miss > excep > spr/sync 437 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_ ADDR) or (state == CONTEXT_STATE_KO_MISS_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);452 // uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR) or (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR) or (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND) or (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); 438 453 // uint8_t priority1 = 2; // miss 439 454 … … 444 459 // bool is_valid = ((state == CONTEXT_STATE_OK) or 445 460 // (depth1< depth0) or 446 // ((depth1==depth0) and (priority1> priority0)));461 // ((depth1==depth0) and (priority1>=priority0))); 447 462 448 463 // if (is_valid) … … 480 495 break; 481 496 } 482 case CONTEXT_STATE_KO_MISS_ ADDR:497 case CONTEXT_STATE_KO_MISS_BRANCH_ADDR: 483 498 // { 484 499 // reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod) 485 500 // break; 486 501 // } 502 case CONTEXT_STATE_KO_MISS_LOAD_ADDR : 487 503 case CONTEXT_STATE_KO_PSYNC_ADDR : 488 504 case CONTEXT_STATE_KO_CSYNC_ADDR : -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
r101 r105 71 71 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 72 72 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 73 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_decod);73 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 74 74 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); 75 75 ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); … … 148 148 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 149 149 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 150 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS 150 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 151 151 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); 152 152 INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); … … 336 336 TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot); 337 337 TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot); 338 TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), request [context].front()._address);338 // TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), request [context].front()._address_next ); 339 339 TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat ); 340 340 if (request [context].front()._has_immediat) … … 450 450 delete [] out_DECOD_NO_EXECUTE ; 451 451 delete [] out_DECOD_IS_DELAY_SLOT ; 452 delete [] out_DECOD_ADDRESS 452 delete [] out_DECOD_ADDRESS_NEXT ; 453 453 delete [] out_DECOD_HAS_IMMEDIAT ; 454 454 delete [] out_DECOD_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
r101 r105 88 88 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] 89 89 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] 90 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS 90 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] 91 91 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] 92 92 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_IMMEDIAT ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
r101 r105 89 89 ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 90 90 ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); 91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address",Tgeneral_data_t ,_param->_size_instruction_address );91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 92 92 ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 93 93 ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
r101 r105 49 49 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 50 50 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1 ); 51 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address);51 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 52 52 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); 53 53 DELETE1_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
r101 r105 126 126 } 127 127 128 Ttype_t type= _decod_instruction->_type;129 Tdepth_t depth= (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT128 Ttype_t type = _decod_instruction->_type; 129 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT 130 130 131 131 if (_param->_have_port_context_id) … … 137 137 PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); 138 138 PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); 139 PORT_WRITE(out_DECOD_ADDRESS [i], addr); 139 // PORT_WRITE(out_DECOD_ADDRESS [i], addr); 140 // if ((type == TYPE_BRANCH) and 141 // ((_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_SET) or 142 // (_decod_instruction->_branch_condition = BRANCH_CONDITION_FLAG_UNSET))) 143 // PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address+2); 144 // else 145 PORT_WRITE(out_DECOD_ADDRESS_NEXT [i], _decod_instruction->_address_next ); 140 146 PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); 141 147 PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp
r101 r105 60 60 ALLOC1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ," in_DECOD_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 61 61 ALLOC1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ," in_DECOD_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 62 ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS ," in_DECOD_IN_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_decod);62 ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ," in_DECOD_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 63 63 ALLOC1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ," in_DECOD_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); 64 64 ALLOC1_SC_SIGNAL( in_DECOD_IN_IMMEDIAT ," in_DECOD_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); … … 84 84 ALLOC1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,"out_DECOD_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 85 85 ALLOC1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,"out_DECOD_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_decod); 86 ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,"out_DECOD_OUT_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_decod);86 ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,"out_DECOD_OUT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 87 87 ALLOC1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,"out_DECOD_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); 88 88 ALLOC1_SC_SIGNAL(out_DECOD_OUT_IMMEDIAT ,"out_DECOD_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); … … 125 125 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); 126 126 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); 127 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS 127 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); 128 128 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); 129 129 INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IMMEDIAT ,_param->_nb_inst_decod); … … 151 151 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); 152 152 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); 153 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS 153 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); 154 154 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); 155 155 INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IMMEDIAT ,_param->_nb_inst_decod); … … 227 227 Tcontext_t context = rand()%_param->_nb_context; 228 228 229 in_DECOD_IN_VAL [i]->write(i<=x);230 in_DECOD_IN_CONTEXT_ID [i]->write(context);231 in_DECOD_IN_DEPTH [i]->write(depth [context]);232 in_DECOD_IN_ADDRESS 229 in_DECOD_IN_VAL [i]->write(i<=x); 230 in_DECOD_IN_CONTEXT_ID [i]->write(context); 231 in_DECOD_IN_DEPTH [i]->write(depth [context]); 232 in_DECOD_IN_ADDRESS_NEXT [i]->write(address_tmp [context]); 233 233 234 234 address_tmp [context] ++; … … 270 270 LABEL(" * context : %d",context); 271 271 272 TEST(Tdepth_t ,out_DECOD_OUT_DEPTH [i]->read(),depth [context]);273 TEST(Taddress_t,out_DECOD_OUT_ADDRESS [i]->read(),address_dest [context]);272 TEST(Tdepth_t ,out_DECOD_OUT_DEPTH [i]->read(),depth [context]); 273 TEST(Taddress_t,out_DECOD_OUT_ADDRESS_NEXT [i]->read(),address_dest [context]); 274 274 275 275 nb_inst [context] --; … … 304 304 DELETE1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); 305 305 DELETE1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); 306 DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS 306 DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod); 307 307 DELETE1_SC_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod); 308 308 DELETE1_SC_SIGNAL( in_DECOD_IN_IMMEDIAT ,_param->_nb_inst_decod); … … 328 328 DELETE1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); 329 329 DELETE1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); 330 DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS 330 DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod); 331 331 DELETE1_SC_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod); 332 332 DELETE1_SC_SIGNAL(out_DECOD_OUT_IMMEDIAT ,_param->_nb_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h
r101 r105 75 75 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_NO_EXECUTE ;//[nb_inst_decod] 76 76 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_IS_DELAY_SLOT ;//[nb_inst_decod] 77 public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS 77 public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS_NEXT ;//[nb_inst_decod] 78 78 public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_HAS_IMMEDIAT ;//[nb_inst_decod] 79 79 public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_IMMEDIAT ;//[nb_inst_decod] … … 100 100 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_NO_EXECUTE ;//[nb_inst_decod] 101 101 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod] 102 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS 102 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS_NEXT ;//[nb_inst_decod] 103 103 public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_HAS_IMMEDIAT ;//[nb_inst_decod] 104 104 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_IMMEDIAT ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h
r88 r105 30 30 public : Tcontrol_t * _no_execute ; 31 31 public : Tcontrol_t * _is_delay_slot ; 32 public : Tgeneral_data_t * _address 32 public : Tgeneral_data_t * _address_next ; 33 33 public : Tcontrol_t * _has_immediat ; 34 34 public : Tgeneral_data_t * _immediat ; … … 56 56 _no_execute = new Tcontrol_t [_nb_inst]; 57 57 _is_delay_slot = new Tcontrol_t [_nb_inst]; 58 _address 58 _address_next = new Tgeneral_data_t [_nb_inst]; 59 59 _has_immediat = new Tcontrol_t [_nb_inst]; 60 60 _immediat = new Tgeneral_data_t [_nb_inst]; … … 85 85 delete [] _no_execute ; 86 86 delete [] _is_delay_slot ; 87 delete [] _address 87 delete [] _address_next ; 88 88 delete [] _has_immediat ; 89 89 delete [] _immediat ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp
r101 r105 67 67 ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 68 68 ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 69 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address",Tgeneral_data_t ,_param->_size_instruction_address );69 ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 70 70 ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 71 71 ALLOC1_SIGNAL_IN ( in_DECOD_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 96 96 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 97 97 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 98 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address",Tgeneral_data_t ,_param->_size_instruction_address );98 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 99 99 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp
r101 r105 37 37 DELETE1_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 38 38 DELETE1_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 39 DELETE1_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data);39 DELETE1_SIGNAL( in_DECOD_IN_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 40 40 DELETE1_SIGNAL( in_DECOD_IN_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); 41 41 DELETE1_SIGNAL( in_DECOD_IN_IMMEDIAT ,_param->_nb_inst_decod,_param->_size_general_data ); … … 61 61 DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 62 62 DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 63 DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data);63 DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 64 64 DELETE1_SIGNAL(out_DECOD_OUT_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); 65 65 DELETE1_SIGNAL(out_DECOD_OUT_IMMEDIAT ,_param->_nb_inst_decod,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp
r101 r105 71 71 72 72 log_printf(TRACE,Decod_queue,FUNCTION," * is_valid : %d",is_valid); 73 log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context);74 log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth);75 log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min);76 log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max);77 log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full);78 log_printf(TRACE,Decod_queue,FUNCTION," * address : 0x%x (0x%x)",reg_QUEUE->front()->_address[i],reg_QUEUE->front()->_address[i]<<2);73 log_printf(TRACE,Decod_queue,FUNCTION," * context : %d",context); 74 log_printf(TRACE,Decod_queue,FUNCTION," * depth : %d",depth); 75 log_printf(TRACE,Decod_queue,FUNCTION," * depth_min : %d",depth_min); 76 log_printf(TRACE,Decod_queue,FUNCTION," * depth_max : %d",depth_max); 77 log_printf(TRACE,Decod_queue,FUNCTION," * depth_full : %d",depth_full); 78 log_printf(TRACE,Decod_queue,FUNCTION," * address_next : 0x%x (0x%x)",reg_QUEUE->front()->_address_next[i],reg_QUEUE->front()->_address_next[i]<<2); 79 79 internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid) 80 80 if (is_valid) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp
r88 r105 52 52 PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [i]); 53 53 PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [i]); 54 PORT_WRITE(out_DECOD_OUT_ADDRESS [i],reg_QUEUE->front()->_address[i]);54 PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT [i],reg_QUEUE->front()->_address_next [i]); 55 55 PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT [i],reg_QUEUE->front()->_has_immediat [i]); 56 56 PORT_WRITE(out_DECOD_OUT_IMMEDIAT [i],reg_QUEUE->front()->_immediat [i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
r101 r105 62 62 entry->_no_execute [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE [i]); 63 63 entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]); 64 entry->_address [i] = PORT_READ(in_DECOD_IN_ADDRESS[i]);64 entry->_address_next [i] = PORT_READ(in_DECOD_IN_ADDRESS_NEXT [i]); 65 65 entry->_has_immediat [i] = PORT_READ(in_DECOD_IN_HAS_IMMEDIAT [i]); 66 66 entry->_immediat [i] = PORT_READ(in_DECOD_IN_IMMEDIAT [i]); … … 144 144 ,(*it)->_no_execute [i] 145 145 ,(*it)->_is_delay_slot [i] 146 ,(*it)->_address 147 ,(*it)->_address 146 ,(*it)->_address_next [i] 147 ,(*it)->_address_next [i]<<2 148 148 ,(*it)->_has_immediat [i] 149 149 ,(*it)->_immediat [i] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp
r101 r105 73 73 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); 74 74 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); 75 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_decod);75 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); 76 76 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); 77 77 ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); … … 159 159 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 160 160 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 161 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS 161 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 162 162 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); 163 163 INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); … … 421 421 // TEST(Tcontrol_t , out_DECOD_NO_EXECUTE [i]->read(), respons [context].front()._no_execute ); 422 422 TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), respons [context].front()._is_delay_slot); 423 TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), respons [context].front()._address);423 // TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), respons [context].front()._address_next ); 424 424 TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), respons [context].front()._has_immediat ); 425 425 if (respons [context].front()._has_immediat) … … 490 490 DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); 491 491 DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); 492 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS 492 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); 493 493 DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); 494 494 DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h
r101 r105 87 87 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] 88 88 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] 89 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS 89 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] 90 90 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] 91 91 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_IMMEDIAT ;//[nb_inst_decod] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp
r101 r105 89 89 ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 90 90 ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); 91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address);91 ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_NEXT ,"address_next" ,Tgeneral_data_t ,_param->_size_instruction_address ); 92 92 ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 93 93 ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 293 293 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT", 294 294 dest, "in_DECOD_IN_"+toString(i)+"_IS_DELAY_SLOT"); 295 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS ",296 dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS ");295 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" , 296 dest, "in_DECOD_IN_"+toString(i)+"_ADDRESS_NEXT" ); 297 297 COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_HAS_IMMEDIAT" , 298 298 dest, "in_DECOD_IN_"+toString(i)+"_HAS_IMMEDIAT" ); … … 435 435 // in_DECOD_IN_NO_EXECUTE - component decod 436 436 // in_DECOD_IN_IS_DELAY_SLOT - component decod 437 // in_DECOD_IN_ADDRESS 437 // in_DECOD_IN_ADDRESS_NEXT - component decod 438 438 // in_DECOD_IN_HAS_IMMEDIAT - component decod 439 439 // in_DECOD_IN_IMMEDIAT - component decod … … 478 478 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT", 479 479 dest,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT"); 480 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS ",481 dest,"out_DECOD_" +toString(i)+"_ADDRESS ");480 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_ADDRESS_NEXT" , 481 dest,"out_DECOD_" +toString(i)+"_ADDRESS_NEXT" ); 482 482 PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_HAS_IMMEDIAT" , 483 483 dest,"out_DECOD_" +toString(i)+"_HAS_IMMEDIAT" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp
r101 r105 33 33 34 34 DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id ); 35 DELETE1_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_size_ general_data);36 // DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_size_ general_data);35 DELETE1_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); 36 // DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); 37 37 DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr ); 38 38 DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_size_branch_state ); … … 48 48 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); 49 49 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); 50 DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data);50 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod,_param->_size_instruction_address ); 51 51 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); 52 52 DELETE1_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod,_param->_size_general_data ); … … 73 73 // DELETE1_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod,1 ); 74 74 DELETE1_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod,1 ); 75 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_ general_data);76 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_ general_data);75 DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 76 DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); 77 77 // DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); 78 78 … … 92 92 DELETE_SIGNAL(out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); 93 93 DELETE_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,1 ); 94 DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,_param->_size_ general_data);95 DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_ general_data);94 DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); 95 DELETE_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); 96 96 } 97 97 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r101 r105 266 266 const int32_t percent_transaction_update = 75; 267 267 const int32_t percent_transaction_branch_event = 75; 268 const int32_t percent_transaction_event = 75; 268 269 269 270 const bool test1 = true; … … 271 272 const bool test3 = true; 272 273 const bool test4 = true; 274 const bool test5 = true; 273 275 274 276 std::list<request_t> ufpt; … … 961 963 SC_START(1); 962 964 in_EVENT_VAL [context]->write(1); 963 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);965 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 964 966 965 967 SC_START(1); … … 1407 1409 SC_START(1); 1408 1410 in_EVENT_VAL [context]->write(1); 1409 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);1411 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 1410 1412 1411 1413 SC_START(1); … … 2036 2038 SC_START(1); 2037 2039 in_EVENT_VAL [context]->write(1); 2038 in_EVENT_TYPE [context]->write(EVENT_TYPE_ MISS_SPECULATION);2040 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 2039 2041 2040 2042 SC_START(1); … … 2128 2130 } 2129 2131 2132 } 2133 } 2134 2135 //--------------------------------------------------------------------- 2136 //--------------------------------------------------------------------- 2137 // COMMIT MISS : with RAS in UPFT and UPT 2138 //--------------------------------------------------------------------- 2139 //--------------------------------------------------------------------- 2140 if (test5) 2141 { 2142 uint32_t context = rand() % _param->_nb_context; 2143 uint32_t have_ufpt_ras = false; 2144 uint32_t have_upt_ras = false; 2145 2146 { 2147 LABEL("PREDICT - fill the queue"); 2148 uint32_t port = rand() % _param->_nb_inst_predict; 2149 2150 LABEL(" * context : %d",context); 2151 LABEL(" * port : %d",port); 2152 2153 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2154 { 2155 request_t request; 2156 request.context = context; 2157 request.address_src = rand(); 2158 request.address_dest = rand(); 2159 2160 request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET; 2161 2162 request.take = 1; 2163 request.take_good = 1; 2164 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 2165 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 2166 request.is_accurate = true ; 2167 request.miss_ifetch = false; 2168 request.miss_decod = false; 2169 request.miss_commit = false; 2170 request.history = i; 2171 request.ras_address = rand(); 2172 request.ras_index = rand()%_param->_size_ras_index[context]; 2173 request.ufpt_ptr = ufpt_top [context]; 2174 // request.upt_ptr; 2175 2176 bool have_transaction = false; 2177 do 2178 { 2179 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 2180 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 2181 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2182 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2183 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 2184 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 2185 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 2186 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 2187 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 2188 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 2189 2190 if (_param->_have_port_depth) 2191 { 2192 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2193 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2194 } 2195 SC_START(0); // fct melay 2196 2197 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 2198 port, 2199 in_PREDICT_VAL [port]->read(), 2200 out_PREDICT_ACK [port]->read(), 2201 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 2202 2203 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 2204 { 2205 LABEL("PREDICT [%d] - Transaction accepted",port); 2206 have_transaction = true; 2207 2208 if (_param->_have_port_depth) 2209 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 2210 2211 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 2212 } 2213 2214 SC_START(1); // transition 2215 2216 } while (not have_transaction); 2217 2218 ufpt.push_back(request); // to update 2219 2220 in_PREDICT_VAL [port]->write(0); 2221 2222 if (_param->_have_port_depth) 2223 { 2224 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2225 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2226 } 2227 } 2228 } 2229 2230 { 2231 LABEL("DECOD"); 2232 uint32_t port = rand() % _param->_nb_inst_decod; 2233 2234 LABEL(" * context : %d",context); 2235 LABEL(" * port : %d",port); 2236 2237 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2238 { 2239 request_t request = ufpt.front(); 2240 2241 bool have_transaction = false; 2242 do 2243 { 2244 in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod); 2245 in_DECOD_CONTEXT_ID [port]->write(request.context ); 2246 in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2247 in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2248 in_DECOD_BTB_CONDITION [port]->write(request.condition ); 2249 in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); 2250 in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); 2251 in_DECOD_RAS_INDEX [port]->write(request.ras_index ); 2252 in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); 2253 in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); 2254 in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); 2255 in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); 2256 2257 have_upt_ras |= (update_ras(request.condition)); 2258 2259 SC_START(0); // fct melay 2260 2261 LABEL("DECOD [%d] %d - %d", 2262 port, 2263 in_DECOD_VAL [port]->read(), 2264 out_DECOD_ACK [port]->read()); 2265 2266 if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) 2267 { 2268 LABEL("DECOD [%d] - Transaction accepted",port); 2269 have_transaction = true; 2270 2271 request.upt_ptr = upt_top [context]; 2272 upt.push_back(request); 2273 ufpt.pop_front(); 2274 2275 upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; 2276 } 2277 2278 SC_START(1); // transition 2279 2280 } while (not have_transaction); 2281 2282 in_DECOD_VAL [port]->write(0); 2283 2284 if (_param->_have_port_depth) 2285 { 2286 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2287 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2288 } 2289 } 2290 } 2291 2292 { 2293 LABEL("PREDICT - fill the queue"); 2294 uint32_t port = rand() % _param->_nb_inst_predict; 2295 2296 LABEL(" * context : %d",context); 2297 LABEL(" * port : %d",port); 2298 2299 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2300 { 2301 request_t request; 2302 request.context = context; 2303 request.address_src = rand(); 2304 request.address_dest = rand(); 2305 request.address_good = request.address_dest; 2306 request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET; 2307 2308 have_ufpt_ras |= (update_ras(request.condition)); 2309 2310 request.take = 1; 2311 request.take_good = 1; 2312 request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); 2313 request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; 2314 request.is_accurate = true ; 2315 request.miss_ifetch = false; 2316 request.miss_decod = false; 2317 request.miss_commit = true; 2318 request.history = i; 2319 request.ras_address = rand(); 2320 request.ras_index = rand()%_param->_size_ras_index[context]; 2321 request.ufpt_ptr = ufpt_top [context]; 2322 // request.upt_ptr; 2323 2324 bool have_transaction = false; 2325 do 2326 { 2327 in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict); 2328 in_PREDICT_CONTEXT_ID [port]->write(request.context ); 2329 in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); 2330 in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); 2331 in_PREDICT_BTB_CONDITION [port]->write(request.condition ); 2332 in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); 2333 in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); 2334 in_PREDICT_DIR_HISTORY [port]->write(request.history ); 2335 in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); 2336 in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); 2337 2338 if (_param->_have_port_depth) 2339 { 2340 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2341 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2342 } 2343 SC_START(0); // fct melay 2344 2345 LABEL("PREDICT [%d] %d - %d (accurate : %d).", 2346 port, 2347 in_PREDICT_VAL [port]->read(), 2348 out_PREDICT_ACK [port]->read(), 2349 in_PREDICT_BTB_IS_ACCURATE [port]->read()); 2350 2351 if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) 2352 { 2353 LABEL("PREDICT [%d] - Transaction accepted",port); 2354 have_transaction = true; 2355 2356 if (_param->_have_port_depth) 2357 TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); 2358 2359 ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; 2360 } 2361 2362 SC_START(1); // transition 2363 2364 } while (not have_transaction); 2365 2366 ufpt.push_back(request); // to update 2367 2368 in_PREDICT_VAL [port]->write(0); 2369 2370 if (_param->_have_port_depth) 2371 { 2372 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2373 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2374 } 2375 } 2376 } 2377 2378 uint32_t nb_branch_before_event = 0; 2379 { 2380 // middle 2381 std::list<request_t>::iterator it_event = upt.begin(); 2382 for (uint32_t i=0; i < (upt.size()>>1); ++i) 2383 { 2384 nb_branch_before_event ++; 2385 it_event ++; 2386 } 2387 for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it) 2388 it->miss_commit = true; 2389 2390 bool have_transaction = false; 2391 2392 do 2393 { 2394 PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event); 2395 PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION); 2396 PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr); 2397 2398 SC_START(0); 2399 2400 if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context])) 2401 { 2402 LABEL("EVENT [%d] - Transaction accepted",context); 2403 2404 have_transaction = true; 2405 } 2406 2407 SC_START(1); 2408 } 2409 while (not have_transaction); 2410 PORT_WRITE(in_EVENT_VAL [context],0); 2411 2412 upt_top_event [it_event->context] = upt_top [it_event->context]; 2413 upt_top [it_event->context] = it_event->upt_ptr; 2414 } 2415 2416 { 2417 LABEL("BRANCH_COMPLETE - Hit ifetch"); 2418 2419 uint32_t port = rand() % _param->_nb_inst_branch_complete; 2420 2421 LABEL(" * port : %d",port); 2422 2423 std::list<request_t>::iterator it_upt = upt.begin(); 2424 2425 for (uint32_t i=0; i<nb_branch_before_event; ++i) 2426 { 2427 bool have_transaction = false; 2428 2429 do 2430 { 2431 in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete); 2432 in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context ); 2433 in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); 2434 in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); 2435 in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); 2436 2437 if (_param->_have_port_depth) 2438 { 2439 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2440 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2441 } 2442 SC_START(0); 2443 2444 LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); 2445 2446 if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) 2447 { 2448 LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); 2449 LABEL(" * CONTEXT_ID : %d" ,it_upt->context ); 2450 LABEL(" * DEPTH : %d" ,it_upt->upt_ptr ); 2451 LABEL(" * CONDITION : %d" ,it_upt->condition ); 2452 LABEL(" * ADDRESS : %.8x",it_upt->address_dest); 2453 LABEL(" * FLAG : %d" ,it_upt->flag ); 2454 LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence ); 2455 2456 have_transaction = true; 2457 2458 TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); 2459 TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take ); 2460 it_upt->take_good = it_upt->take; 2461 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); 2462 TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2463 2464 it_upt++; 2465 } 2466 2467 SC_START(1); 2468 2469 } while (not have_transaction); 2470 2471 in_BRANCH_COMPLETE_VAL [port]->write(0); 2472 2473 if (_param->_have_port_depth) 2474 { 2475 TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2476 TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2477 } 2478 } 2479 } 2480 2481 if (have_ufpt_ras) 2482 { 2483 LABEL("UPDATE - Update UPFT"); 2484 2485 uint32_t port = 0; 2486 2487 LABEL(" * port : %d",port); 2488 std::list<request_t>::iterator it_ufpt = ufpt.end(); 2489 -- it_ufpt; 2490 2491 for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) 2492 { 2493 bool have_transaction = false; 2494 2495 do 2496 { 2497 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2498 2499 // if (_param->_have_port_depth) 2500 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 2501 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 2502 2503 SC_START(0); 2504 2505 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2506 2507 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2508 { 2509 LABEL("UPDATE [%d] - Transaction accepted",port); 2510 have_transaction = true; 2511 2512 if (_param->_have_port_context_id) 2513 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context); 2514 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or 2515 it_ufpt->miss_decod or 2516 it_ufpt->miss_commit )); 2517 // if (update_btb(it_ufpt->condition) or 2518 // update_dir(it_ufpt->condition)) 2519 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good); 2520 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0); 2521 // if (update_btb(it_ufpt->condition)) 2522 // { 2523 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src); 2524 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest); 2525 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition); 2526 // } 2527 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0); 2528 2529 // if (update_dir(it_ufpt->condition)) 2530 // if (_param->_have_port_history) 2531 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history); 2532 // TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition)); 2533 if (update_ras(it_ufpt->condition)) 2534 { 2535 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2536 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition)); 2537 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 2538 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 2539 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 2540 } 2541 } 2542 2543 SC_START(1); 2544 } while (not have_transaction); 2545 2546 -- it_ufpt; 2547 2548 2549 in_UPDATE_ACK [port]->write(0); 2550 // if (_param->_have_port_depth) 2551 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]); 2552 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]); 2553 } 2554 } 2555 ufpt.clear(); 2556 2557 { 2558 LABEL("UPDATE - upt (after event)"); 2559 2560 uint32_t port = 0; 2561 2562 LABEL(" * port : %d",port); 2563 2564 std::list<request_t>::iterator it_upt = upt.end(); 2565 2566 // for (uint32_t i=0; i<upt.size(); i++) 2567 2568 uint32_t size = upt.size(); 2569 2570 LABEL(" * size : %d",size); 2571 LABEL(" * nb_branch_before_event : %d",nb_branch_before_event); 2572 2573 for (uint32_t i=nb_branch_before_event; i<size; ++i) 2574 { 2575 --it_upt; 2576 2577 bool have_transaction = false; 2578 2579 if (need_update(it_upt->condition)) 2580 do 2581 { 2582 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2583 2584 // if (_param->_have_port_depth) 2585 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2586 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2587 2588 SC_START(0); 2589 2590 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2591 2592 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2593 { 2594 LABEL("UPDATE [%d] - Transaction accepted",port); 2595 LABEL(" * address_src : %.8x",it_upt->address_src); 2596 LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read()); 2597 2598 have_transaction = true; 2599 2600 bool btb_val = ((update_btb(it_upt->condition))); 2601 bool dir_val = (update_dir(it_upt->condition) and 2602 not (it_upt->miss_ifetch or it_upt->miss_decod)); 2603 bool ras_val = update_ras(it_upt->condition); 2604 2605 if (_param->_have_port_context_id) 2606 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 2607 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 2608 // TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val); 2609 2610 // if (btb_val) 2611 // { 2612 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 2613 // TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2614 // TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 2615 // } 2616 // TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val); 2617 2618 // if (dir_val) 2619 // { 2620 // TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 2621 // if (_param->_have_port_history) 2622 // TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 2623 // } 2624 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val); 2625 2626 if (ras_val) 2627 { 2628 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2629 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 2630 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2631 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2632 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2633 } 2634 // -- it_upt; 2635 } 2636 2637 SC_START(1); 2638 } while (not have_transaction); 2639 2640 upt.pop_back(); 2641 in_UPDATE_ACK [port]->write(0); 2642 // if (_param->_have_port_depth) 2643 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2644 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2645 } 2646 } 2647 2648 /* 2649 { 2650 LABEL("BRANCH_EVENT - have miss decod"); 2651 2652 uint32_t port = context; 2653 2654 { 2655 bool have_transaction = false; 2656 2657 do 2658 { 2659 in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event); 2660 2661 SC_START(0); 2662 2663 LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read()); 2664 2665 if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read()) 2666 { 2667 LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); 2668 have_transaction = true; 2669 2670 LABEL(" * event.address_src : %.8x,",event.address_src ); 2671 LABEL(" * event.address_good : %.8x,",event.address_good); 2672 LABEL(" * event.take : %.8x,",event.take ); 2673 2674 TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); 2675 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); 2676 TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good); 2677 if (event.take_good) 2678 TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good); 2679 2680 event.address_src = 0; 2681 event.take = 0; 2682 event.address_dest = 0; 2683 } 2684 2685 SC_START(1); 2686 } while (not have_transaction); 2687 2688 in_BRANCH_EVENT_ACK [port]->write(0); 2689 } 2690 } 2691 2692 { 2693 LABEL("EVENT_STATE"); 2694 2695 SC_START(1); 2696 in_EVENT_VAL [context]->write(1); 2697 in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION); 2698 2699 SC_START(1); 2700 in_EVENT_VAL [context]->write(0); 2701 in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); 2702 } 2703 */ 2704 2705 { 2706 LABEL("UPDATE - upt (before event)"); 2707 2708 uint32_t port = 0; 2709 2710 LABEL(" * port : %d",port); 2711 LABEL(" * size : %d",upt.size()); 2712 std::list<request_t>::iterator it_upt = upt.begin(); 2713 2714 for (uint32_t i=0; i<upt.size(); i++) 2715 { 2716 bool have_transaction = false; 2717 2718 do 2719 { 2720 in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update); 2721 2722 // if (_param->_have_port_depth) 2723 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2724 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2725 2726 SC_START(0); 2727 2728 LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); 2729 2730 if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) 2731 { 2732 LABEL("UPDATE [%d] - Transaction accepted",port); 2733 have_transaction = true; 2734 2735 if (_param->_have_port_context_id) 2736 TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); 2737 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 2738 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 2739 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 2740 if (update_btb(it_upt->condition)) 2741 { 2742 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); 2743 TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest); 2744 TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); 2745 } 2746 TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); 2747 2748 if (update_dir(it_upt->condition)) 2749 if (_param->_have_port_history) 2750 TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); 2751 TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); 2752 if (update_ras(it_upt->condition)) 2753 { 2754 // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); 2755 TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition)); 2756 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2757 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2758 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2759 } 2760 2761 ++ it_upt; 2762 } 2763 2764 SC_START(1); 2765 } while (not have_transaction); 2766 2767 in_UPDATE_ACK [port]->write(0); 2768 // if (_param->_have_port_depth) 2769 // TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); 2770 // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); 2771 } 2772 } 2773 2774 upt.clear(); 2775 2776 // Wait Garbage Collector 2777 { 2778 LABEL("GARBAGE COLLECTOR"); 2779 LABEL(" * upt bottom : %d",upt_bottom [context]); 2780 LABEL(" * upt top : %d",upt_top [context]); 2781 2782 upt_top [context] = (upt_top_event [context]); 2783 upt_bottom [context] = (upt_top [context]); 2784 2785 while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or 2786 (upt_top [context] != out_DEPTH_MAX [context]->read())) 2787 { 2788 SC_START(1); 2789 } 2130 2790 } 2131 2791 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r101 r105 21 21 typedef enum 22 22 { 23 EVENT_STATE_OK , // Can predict 24 EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt 25 EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt 26 EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS 27 EVENT_STATE_UPDATE_CONTEXT , // prediction unit is update, send signal to context manager 28 EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of event (send by Context State) 23 EVENT_STATE_OK , // Can predict 24 EVENT_STATE_MISS_FLUSH_UFPT , // in decod stage, detect a miss , continue to execute but flush ufpt 25 EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss , stop context and flush ufpt and upt 26 EVENT_STATE_MISS_FLUSH_UPT , // in commit stage, detect a miss , context is stop and ufpt is flush, update RAS 27 EVENT_STATE_EVENT_FLUSH_UFPT , // in commit stage, detect an event, continue to execute but flush ufpt 28 EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT, // in commit stage, detect an event, stop context and flush ufpt and upt 29 EVENT_STATE_EVENT_FLUSH_UPT , // in commit stage, detect an event, context is stop and ufpt is flush, update RAS 30 EVENT_STATE_UPDATE_CONTEXT , // prediction unit is update, send signal to context manager 31 EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of event (send by Context State) 29 32 } event_state_t; 30 33 … … 116 119 switch (x) 117 120 { 118 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; 119 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt" ; break; 120 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt" ; break; 121 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT : return "flush_upt" ; break; 122 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; 123 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT : return "wait_and_event" ; break; 124 default : return "" ; break; 121 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; 122 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT : return "miss_flush_ufpt" ; break; 123 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : return "miss_flush_ufpt_and_upt" ; break; 124 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_MISS_FLUSH_UPT : return "miss_flush_upt" ; break; 125 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UPT : return "event_flush_upt" ; break; 126 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT : return "event_flush_ufpt" ; break; 127 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: return "event_flush_ufpt_and_upt"; break; 128 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; 129 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT : return "wait_and_event" ; break; 130 default : return ""; break; 125 131 } 126 132 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r101 r105 178 178 private : bool * reg_IS_ACCURATE ; //[nb_context] 179 179 180 private : bool * reg_EVENT_VAL ; //[nb_context] 181 private : uint32_t * reg_EVENT_UPT_PTR ; //[nb_context] 182 180 183 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 181 184 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r101 r105 205 205 ALLOC1(reg_UPT_EMPTY ,bool ,_param->_nb_context); 206 206 207 ALLOC1(reg_EVENT_VAL ,bool ,_param->_nb_context); 208 ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); 209 207 210 ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); 208 211 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r101 r105 158 158 DELETE1(reg_UPT_EMPTY ,_param->_nb_context); 159 159 160 DELETE1(reg_EVENT_VAL ,_param->_nb_context); 161 DELETE1(reg_EVENT_UPT_PTR ,_param->_nb_context); 162 160 163 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 161 164 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp
r95 r105 50 50 is_accurate and 51 51 // ( 52 (event_state == EVENT_STATE_OK 53 // (event_state == EVENT_STATE_ FLUSH_UFPT ) or52 (event_state == EVENT_STATE_OK)// or 53 // (event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or 54 54 // (event_state == EVENT_STATE_UPDATE_CONTEXT)) 55 55 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r101 r105 40 40 // include ]DEPTH_MIN:DEPTH_MAX] -> speculative 41 41 42 PORT_WRITE(out_DEPTH_VAL [i],(reg_UPDATE_PREDICTION_TABLE [i][reg_UPT_TOP [i]]._state == UPDATE_PREDICTION_STATE_EMPTY)); 42 PORT_WRITE(out_DEPTH_VAL [i],((reg_UPDATE_PREDICTION_TABLE [i][reg_UPT_TOP [i]]._state == UPDATE_PREDICTION_STATE_EMPTY) 43 and (reg_EVENT_STATE [i] == EVENT_STATE_OK) 44 )); 43 45 if (_param->_have_port_depth) 44 46 { … … 59 61 bool retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt 60 62 bool retire_ras_from_upt [_param->_nb_context]; // event upt -> restore RAS, else restore others structure 63 // bool have_event [_param->_nb_context]; 61 64 bool ufpt_update [_param->_nb_context]; 62 65 bool upt_update [_param->_nb_context]; … … 68 71 event_state_t event_state = reg_EVENT_STATE [i]; 69 72 70 retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or 71 (event_state == EVENT_STATE_FLUSH_UFPT_AND_UPT)); 72 retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT); 73 retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or 74 (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 75 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT ) or 76 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT)); 77 retire_ras_from_upt [i] = ((event_state == EVENT_STATE_MISS_FLUSH_UPT) or 78 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 79 80 // have_event [i] = (event_state == EVENT_STATE_EVENT_FLUSH_UPT); 73 81 74 82 ufpt_update [i] = true; … … 168 176 (state == UPDATE_PREDICTION_STATE_KO )); 169 177 Tcontrol_t state_is_event = ((state == UPDATE_PREDICTION_STATE_KO ) or 170 (state == UPDATE_PREDICTION_STATE_EVENT)); 178 (state == UPDATE_PREDICTION_STATE_EVENT)// or 179 // ((have_event[context])?(state == UPDATE_PREDICTION_STATE_OK):false) 180 ); 181 171 182 Tcontrol_t state_is_event_update = state_is_event and need_update(condition); 172 183 Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r101 r105 50 50 reg_IS_ACCURATE [i] = true; 51 51 52 reg_EVENT_VAL [i] = false; 52 53 reg_EVENT_STATE [i] = EVENT_STATE_OK; 53 54 } … … 55 56 else 56 57 { 57 bool flush_UFPT [_param->_nb_context];58 bool flush_UFPT [_param->_nb_context]; 58 59 for (uint32_t i=0; i<_param->_nb_context; i++) 59 flush_UFPT [i] = false; 60 { 61 flush_UFPT [i] = false; 62 } 60 63 61 64 // =================================================================== … … 66 69 // * Update state -> new status is "empty" 67 70 // * Update pointer (bottom and accurate) 68 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR ");71 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)"); 69 72 for (uint32_t i=0; i<_param->_nb_context; i++) 70 73 { … … 113 116 // if (bottom = reg_UPT_UPDATE [i]) 114 117 // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; 115 if (end_ko) // free 118 119 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 120 // if (end_ko) // free 116 121 { 122 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); 123 124 reg_EVENT_VAL [i] = false; 117 125 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 118 126 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 119 127 120 128 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 121 129 reg_UPT_EMPTY [i] = false; … … 124 132 } 125 133 } 134 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)"); 126 135 127 136 // =================================================================== … … 218 227 else 219 228 { 220 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_ FLUSH_UFPT (decod - miss - flush ufpt)",context);221 reg_EVENT_STATE [context] = EVENT_STATE_ FLUSH_UFPT;229 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT (decod - miss - flush ufpt)",context); 230 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; 222 231 } 223 232 … … 273 282 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ; 274 283 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ; 275 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch284 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch 276 285 277 286 // Update pointer … … 283 292 284 293 // All case !!! 285 286 294 #ifdef DEBUG_TEST 287 295 if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY) … … 352 360 353 361 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 354 reg_UPT_EMPTY [ i] = true;362 reg_UPT_EMPTY [context] = true; 355 363 356 364 #ifdef DEBUG_TEST … … 364 372 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 365 373 event_state_t event_state = reg_EVENT_STATE [context]; 366 bool previous_update_ras = (event_state == EVENT_STATE_FLUSH_UPT); 367 bool update_ras = (new_update != depth); 368 369 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 374 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 375 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 376 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 377 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 378 // bool update_ras = (new_update != depth); 379 380 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 370 381 371 382 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 372 383 { 373 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_ FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);374 reg_EVENT_STATE [context] = EVENT_STATE_ FLUSH_UFPT_AND_UPT;384 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 385 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 375 386 } 376 387 else 377 388 { 378 if (not previous_update_ras)389 // if (not previous_update_ras) 379 390 { 380 391 // have ras prediction ? 381 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_ FLUSH_UPT (branch_complete - miss)",context);382 383 reg_EVENT_STATE [context] = EVENT_STATE_ FLUSH_UPT;392 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 393 394 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 384 395 385 396 } … … 442 453 switch (reg_EVENT_STATE [context]) 443 454 { 444 case EVENT_STATE_ FLUSH_UFPT: reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break;455 case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 445 456 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 446 case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT ; break; 457 case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; 458 case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; 459 case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; 447 460 default : break; 448 461 } … … 478 491 { 479 492 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and 480 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )493 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) ) 481 494 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 482 495 } … … 507 520 508 521 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 522 523 reg_EVENT_VAL [context] = true; 524 reg_EVENT_UPT_PTR [context] = depth; 509 525 510 526 #ifdef STATISTICS … … 541 557 if (end_event) 542 558 { 543 reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 544 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 559 // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 560 561 if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT) 562 { 563 reg_EVENT_STATE [context] = EVENT_STATE_OK; 564 } 565 else 566 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 545 567 } 546 568 else … … 593 615 if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i]) 594 616 { 617 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 618 595 619 //---------------------------------------------------------------- 596 620 // Cases … … 606 630 607 631 Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); 608 // Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); 609 632 610 633 // Test if end of miss -> all previous branch is complete 611 634 // -> all next branch is finish 612 if (event_type == EVENT_TYPE_MISS_SPECULATION) 635 636 switch (event_type) 613 637 { 614 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); 615 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); 616 617 #ifdef DEBUG_TEST 618 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 619 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 620 #endif 621 622 // Change state 623 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 624 625 reg_EVENT_STATE [i] = EVENT_STATE_OK; 626 reg_IS_ACCURATE [i] = true; 627 628 // Tdepth_t depth = reg_UPT_TOP [i]; 629 630 #ifdef DEBUG_TEST 631 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) 632 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 633 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) 634 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 635 #endif 636 637 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); 638 case EVENT_TYPE_BRANCH_MISS_SPECULATION : 639 { 640 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION"); 641 642 #ifdef DEBUG_TEST 643 if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) 644 throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); 645 #endif 646 647 // Change state 648 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); 649 650 reg_EVENT_STATE [i] = EVENT_STATE_OK; 651 reg_IS_ACCURATE [i] = true; 652 653 // Tdepth_t depth = reg_UPT_TOP [i]; 654 655 #ifdef DEBUG_TEST 656 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO_WAIT_END) 657 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 658 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END_KO) 659 // throw ERRORMORPHEO(FUNCTION,_("Event : invalid upt event state.")); 660 #endif 661 662 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",i,depth); 638 663 639 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 640 664 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 665 666 break; 667 } 668 case EVENT_TYPE_LOAD_MISS_SPECULATION : 669 case EVENT_TYPE_EXCEPTION : 670 { 671 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION"); 672 673 // Have a miss !!! 674 // Flush UPFT 675 flush_UFPT [i] = true; 676 677 // Flush UPT 678 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; 679 uint32_t top = reg_UPT_TOP [i]; 680 uint32_t bottom = reg_UPT_BOTTOM [i]; 681 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 682 uint32_t full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 683 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 684 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 685 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 686 687 688 #ifdef DEBUG_TEST 689 if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 690 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 691 #endif 692 693 // flush all slot after the event 694 for (uint32_t j=depth; 695 j!=top; 696 j=(j+1)%_param->_size_upt_queue[i]) 697 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 698 699 // test full : 700 if (full) 701 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 702 703 // reg_UPT_BOTTOM [i]; 704 // TODO : special case : event is an exception on branch, also depth is not valid 705 reg_UPT_TOP [i] = depth; // depth is again valid 706 reg_UPT_TOP_EVENT [i] = top; 707 708 if (bottom == reg_UPT_TOP [i]) 709 reg_UPT_EMPTY [i] = true; 710 711 reg_EVENT_VAL [i] = true; 712 reg_EVENT_UPT_PTR [i] = depth; 713 event_state_t event_state = reg_EVENT_STATE [i]; 714 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 715 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 716 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 717 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 718 bool update_ras = (top != depth) or full; 719 720 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 721 722 // new state : 723 // * test if ufpt is empty 724 // * ok : flush upft and upt 725 // * ko : test if have previous flush upt 726 // * ok : nothing 727 // * ko : flush upt 728 if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 729 { 730 if (update_ras) 731 { 732 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); 733 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; 734 } 735 else 736 { 737 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); 738 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; 739 } 740 } 741 else 742 { 743 // if (not previous_update_ras) 744 if (update_ras) 745 { 746 // have ras prediction ? 747 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); 748 749 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; 750 } 751 else 752 { 753 reg_EVENT_STATE [i] = EVENT_STATE_OK; 754 } 755 } 756 757 if (not previous_update_ras and update_ras) 758 { 759 reg_UPT_UPDATE [i] = new_update; 760 } 761 // else no update 762 763 reg_EVENT_DEPTH [i] = depth; 764 // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 765 // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 766 // reg_EVENT_ADDRESS_DEST [i] = good_addr; 767 768 break; 769 } 770 default : 771 { 772 // nothing 773 break; 774 } 641 775 } 642 776 } … … 706 840 { 707 841 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); 842 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); 843 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 708 844 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 709 845 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
r101 r105 68 68 ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); 69 69 ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); 70 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS",Tgeneral_data_t ,_param->_sum_inst_decod);70 ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_sum_inst_decod); 71 71 ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); 72 72 ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod); … … 97 97 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 98 98 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); 99 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ," in_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 99 100 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 100 101 ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 155 156 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); 156 157 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); 157 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS 158 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); 158 159 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); 159 160 INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); … … 188 189 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT ); 189 190 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS ); 191 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 190 192 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR ); 191 193 INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); … … 315 317 DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); 316 318 DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); 317 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS 319 DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod); 318 320 DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); 319 321 DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); … … 344 346 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ); 345 347 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ); 348 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 346 349 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ); 347 350 DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h
r101 r105 94 94 public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[sum_inst_decod] 95 95 public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[sum_inst_decod] 96 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS 96 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS_NEXT ;//[sum_inst_decod] 97 97 public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[sum_inst_decod] 98 98 public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_IMMEDIAT ;//[sum_inst_decod] … … 127 127 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_IS_DELAY_SLOT ; 128 128 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS ; 129 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 129 130 public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; 130 131 public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
r101 r105 97 97 ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ); 98 98 ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS ,"ADDRESS",Tgeneral_data_t ,_param->_size_instruction_address );99 ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Tgeneral_data_t ,_param->_size_instruction_address ); 100 100 ALLOC1_SIGNAL_OUT (out_DECOD_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ); 101 101 ALLOC1_SIGNAL_OUT (out_DECOD_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ); … … 138 138 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 139 139 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 140 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); 140 141 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 141 142 ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); … … 698 699 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT", 699 700 dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT"); 700 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS ",701 dest,"out_DECOD_"+toString(x)+"_ADDRESS ");701 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS_NEXT" , 702 dest,"out_DECOD_"+toString(x)+"_ADDRESS_NEXT" ); 702 703 PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_HAS_IMMEDIAT" , 703 704 dest,"out_DECOD_"+toString(x)+"_HAS_IMMEDIAT" ); … … 919 920 PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS" , 920 921 dest, "in_COMMIT_EVENT_ADDRESS" ); 922 PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR_VAL", 923 dest, "in_COMMIT_EVENT_ADDRESS_EPCR_VAL"); 921 924 PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR" , 922 925 dest, "in_COMMIT_EVENT_ADDRESS_EPCR" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp
r101 r105 49 49 DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod,1 ); 50 50 DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod,1 ); 51 DELETE1_SIGNAL(out_DECOD_ADDRESS 51 DELETE1_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_sum_inst_decod,_param->_size_instruction_address ); 52 52 DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod,1 ); 53 53 DELETE1_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod,_param->_size_general_data ); … … 80 80 DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); 81 81 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address ); 82 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); 82 83 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address ); 83 84 DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
r104 r105 68 68 ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 69 69 ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);70 ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ," in_INSERT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 71 71 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ," in_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 153 153 ALLOC_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); 154 154 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); 155 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,"out_UPDATE_ADDRESS_EPCR_VAL ",Tcontrol_t ); 155 156 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); 156 157 ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 205 206 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 206 207 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 207 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS 208 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 208 209 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 209 210 INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 302 303 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); 303 304 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS ); 305 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR_VAL ); 304 306 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR ); 305 307 INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); … … 418 420 in_INSERT_IS_DELAY_SLOT [i][j]->write(0); 419 421 in_INSERT_NO_EXECUTE [i][j]->write(0); 420 in_INSERT_ADDRESS 422 in_INSERT_ADDRESS_NEXT [i][j]->write(addr); 421 423 in_INSERT_EXCEPTION [i][j]->write(0); 422 424 in_INSERT_EXCEPTION_USE [i][j]->write(0); … … 615 617 DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 616 618 DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 617 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS 619 DELETE2_SC_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 618 620 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 619 621 DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 698 700 DELETE_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ); 699 701 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS ); 702 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ); 700 703 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ); 701 704 DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r104 r105 83 83 public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] 84 84 public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] 85 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS 85 public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS_NEXT ;//[nb_rename_unit][nb_inst_insert] 86 86 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] 87 87 public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] … … 179 179 public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; 180 180 public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; 181 public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EPCR_VAL ; 181 182 public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; 182 183 public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; … … 229 230 private : bool ** reg_EVENT_FLUSH ;//[nb_front_end][nb_context] 230 231 231 232 //private : Taddress_t ** reg_PC_PREVIOUS ;//[nb_front_end][nb_context] 232 233 private : Taddress_t ** reg_PC_CURRENT ;//[nb_front_end][nb_context] 233 234 private : Taddress_t ** reg_PC_CURRENT_IS_DS ;//[nb_front_end][nb_context] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h
r100 r105 42 42 ROB_END_BRANCH_MISS_SPECULATIVE, // 43 43 ROB_END_BRANCH_MISS , // 44 ROB_END_LOAD_MISS_SPECULATIVE , // 45 ROB_END_LOAD_MISS_UPDATE , // 46 ROB_END_LOAD_MISS , // 44 47 ROB_END_MISS , // 45 48 ROB_END_EXCEPTION_WAIT_HEAD , // 46 ROB_END_EXCEPTION // 49 ROB_END_EXCEPTION_UPDATE , // 50 ROB_END_EXCEPTION // 47 51 } rob_state_t; 48 52 … … 58 62 public : Toperation_t operation ; 59 63 public : Tcontrol_t is_delay_slot ; 60 64 //public : Tgeneral_data_t address ; 61 65 public : Tcontrol_t use_store_queue ; 62 66 public : Tcontrol_t use_load_queue ; … … 86 90 public : Tspecial_data_t flags ; 87 91 public : Tcontrol_t no_sequence ; 88 public : Tgeneral_data_t data_commit ; // branch's destination 92 //public : Tgeneral_data_t data_commit ; // branch's destination 93 public : Taddress_t address_next ; 89 94 90 95 // public : entry_t (uint32_t ptr , … … 177 182 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS_SPECULATIVE: return "ROB_END_BRANCH_MISS_SPECULATIVE" ; break; 178 183 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_BRANCH_MISS : return "ROB_END_BRANCH_MISS" ; break; 184 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS_SPECULATIVE : return "ROB_END_LOAD_MISS_SPECULATIVE" ; break; 185 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS_UPDATE : return "ROB_END_LOAD_MISS_UPDATE" ; break; 186 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_LOAD_MISS : return "ROB_END_LOAD_MISS" ; break; 179 187 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_MISS : return "ROB_END_MISS" ; break; 180 188 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "ROB_END_EXCEPTION_WAIT_HEAD" ; break; 189 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_UPDATE : return "ROB_END_EXCEPTION_UPDATE" ; break; 181 190 case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "ROB_END_EXCEPTION" ; break; 182 191 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r104 r105 71 71 _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]);73 _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 74 74 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); 75 75 _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); … … 192 192 ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); 193 193 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); 194 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR_VAL ,"address_epcr_val",Tcontrol_t ,1); 194 195 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); 195 196 ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); … … 284 285 ALLOC2(reg_EVENT_FLUSH ,bool ,_param->_nb_front_end,_param->_nb_context [it1]); 285 286 286 287 // ALLOC2(reg_PC_PREVIOUS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 287 288 ALLOC2(reg_PC_CURRENT ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); 288 289 ALLOC2(reg_PC_CURRENT_IS_DS ,Taddress_t ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r104 r105 39 39 DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 40 40 DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); 41 DELETE2_SIGNAL( in_INSERT_ADDRESS 41 DELETE2_SIGNAL( in_INSERT_ADDRESS_NEXT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); 42 42 DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); 43 43 DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); … … 129 129 DELETE_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,1 ); 130 130 DELETE_SIGNAL (out_UPDATE_ADDRESS ,_param->_size_instruction_address ); 131 DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR_VAL ,1 ); 131 132 DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); 132 133 DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,1 ); … … 188 189 DELETE2(reg_EVENT_STATE ,_param->_nb_front_end,_param->_nb_context [it1]); 189 190 DELETE2(reg_EVENT_FLUSH ,_param->_nb_front_end,_param->_nb_context [it1]); 190 191 // DELETE2(reg_PC_PREVIOUS ,_param->_nb_front_end,_param->_nb_context [it1]); 191 192 DELETE2(reg_PC_CURRENT ,_param->_nb_front_end,_param->_nb_context [it1]); 192 193 DELETE2(reg_PC_CURRENT_IS_DS ,_param->_nb_front_end,_param->_nb_context [it1]); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp
r104 r105 80 80 (state == ROB_END_KO ) or 81 81 (state == ROB_END_BRANCH_MISS) or 82 (state == ROB_END_LOAD_MISS ) or 82 83 (state == ROB_END_MISS )// or 83 84 // (state == ROB_END_EXCEPTION) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
r104 r105 99 99 if (_param->_have_port_depth) 100 100 PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); 101 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry-> data_commit);101 PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->address_next ); 102 102 // PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i],(entry->flags&FLAG_F)!=0); 103 103 PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); … … 117 117 // =================================================================== 118 118 { 119 Tcontrol_t val = false; 120 121 if (not _rob[reg_NUM_BANK_HEAD].empty()) 122 { 123 entry_t * entry = _rob [reg_NUM_BANK_HEAD].front(); 124 rob_state_t state = entry->state; 125 126 val = (state == ROB_END_EXCEPTION); 127 128 if (val) 129 { 130 throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 131 } 132 } 119 internal_UPDATE_VAL = 0; 120 internal_UPDATE_NUM_BANK = reg_NUM_BANK_HEAD; 121 122 if (not _rob[internal_UPDATE_NUM_BANK].empty()) 123 { 124 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); 125 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",internal_UPDATE_NUM_BANK); 126 127 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 128 129 switch (entry->state) 130 { 131 case ROB_END_EXCEPTION_UPDATE : 132 { 133 internal_UPDATE_VAL = 1; 134 throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 135 break; 136 } 137 case ROB_END_LOAD_MISS_UPDATE : 138 { 139 log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); 140 141 internal_UPDATE_VAL = 1; 142 143 Tcontext_t front_end_id = entry->front_end_id; 144 Tcontext_t context_id = entry->context_id ; 145 146 log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); 147 log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id ); 148 149 if (_param->_have_port_front_end_id) 150 PORT_WRITE(out_UPDATE_FRONT_END_ID ,front_end_id); 151 if (_param->_have_port_context_id) 152 PORT_WRITE(out_UPDATE_CONTEXT_ID ,context_id ); 153 if (_param->_have_port_depth) 154 PORT_WRITE(out_UPDATE_DEPTH ,entry->depth); 155 PORT_WRITE(out_UPDATE_TYPE ,EVENT_TYPE_LOAD_MISS_SPECULATION); 156 // PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,reg_PC_CURRENT_IS_DS [front_end_id][context_id]); 157 // PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_CURRENT [front_end_id][context_id]); 158 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id]); 159 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,reg_PC_NEXT [front_end_id][context_id]); 160 // PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); 161 // // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); 162 163 PORT_WRITE(out_UPDATE_IS_DELAY_SLOT ,0); 164 PORT_WRITE(out_UPDATE_ADDRESS ,reg_PC_NEXT [front_end_id][context_id]); 165 PORT_WRITE(out_UPDATE_ADDRESS_EPCR_VAL,0); 166 // PORT_WRITE(out_UPDATE_ADDRESS_EPCR ,); 167 PORT_WRITE(out_UPDATE_ADDRESS_EEAR_VAL,0); 168 // PORT_WRITE(out_UPDATE_ADDRESS_EEAR ,); 169 170 break; 171 } 172 default : 173 { 174 // internal_UPDATE_VAL = 0; 175 } 176 } 177 } 178 179 PORT_WRITE(out_UPDATE_VAL, internal_UPDATE_VAL); 180 181 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE (end)"); 133 182 } 134 183 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r104 r105 51 51 reg_PC_CURRENT_IS_DS [i][j] = 0; 52 52 reg_PC_CURRENT_IS_DS_TAKE [i][j] = 0; 53 //reg_PC_NEXT [i][j] = (0x100+4)>>2;53 reg_PC_NEXT [i][j] = (0x100+4)>>2; 54 54 } 55 55 … … 138 138 entry->operation = operation; 139 139 entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); 140 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]);140 // entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 141 141 entry->exception = exception; 142 142 entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); … … 162 162 entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); 163 163 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 164 entry->no_sequence = type == TYPE_BRANCH; 165 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 164 166 165 167 // Test if exception : … … 295 297 case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} 296 298 // Store OK, Load and other instruction 297 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_ MISS:ROB_END_OK_SPECULATIVE); break;}299 case ROB_OTHER_WAIT_END : {state = (have_exception)?ROB_END_EXCEPTION_WAIT_HEAD:((have_miss_speculation)?ROB_END_LOAD_MISS_SPECULATIVE:ROB_END_OK_SPECULATIVE); break;} 298 300 default : 299 301 { … … 304 306 305 307 // update Re Order Buffer 306 entry->state = state; 307 entry->exception = exception; 308 entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); 309 entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); 310 entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]); 308 entry->state = state; 309 entry->exception = exception; 310 entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); 311 entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); 312 // jalr, jr : address_dest is in register 313 if ((entry->type == TYPE_BRANCH) and 314 (entry->operation == OPERATION_BRANCH_L_JALR) and 315 (entry->read_rb)) 316 entry->address_next = PORT_READ(in_COMMIT_ADDRESS [x]); 311 317 } 312 318 } … … 345 351 Ttype_t type = entry->type ; 346 352 347 if (state == ROB_END_BRANCH_MISS) 353 if ((state == ROB_END_OK ) or // LOAD_MISS 354 // (state == ROB_END_KO ) or 355 (state == ROB_END_BRANCH_MISS)// or 356 // (state == ROB_END_LOAD_MISS ) or 357 // (state == ROB_END_MISS ) or 358 // (state == ROB_END_EXCEPTION ) 359 ) 360 { 361 // reg_PC_PREVIOUS [front_end_id][context_id] = reg_PC_CURRENT [front_end_id][context_id]; 362 reg_PC_CURRENT [front_end_id][context_id] = reg_PC_NEXT [front_end_id][context_id]; 363 reg_PC_CURRENT_IS_DS [front_end_id][context_id] = entry->type == TYPE_BRANCH; 364 reg_PC_CURRENT_IS_DS_TAKE [front_end_id][context_id] = entry->no_sequence; 365 reg_PC_NEXT [front_end_id][context_id] = (entry->no_sequence)?(entry->address_next):(reg_PC_CURRENT [front_end_id][context_id]+1); 366 } 367 368 if ((state == ROB_END_BRANCH_MISS) or 369 (state == ROB_END_LOAD_MISS)) 348 370 { 349 371 reg_EVENT_STATE [front_end_id][context_id] = EVENT_STATE_EVENT; 350 372 reg_EVENT_FLUSH [front_end_id][context_id] = true; 351 352 // TODO Compute address !!!!!!!!!!!353 373 } 354 374 … … 412 432 // =====[ UPDATE ]==================================================== 413 433 // =================================================================== 414 { 415 // Not yet implemented 416 } 434 if (internal_UPDATE_VAL and PORT_READ(in_UPDATE_ACK)) 435 { 436 log_printf(TRACE,Commit_unit,FUNCTION," * UPDATE"); 437 438 entry_t * entry = _rob [internal_UPDATE_NUM_BANK].front(); 439 440 switch (entry->state) 441 { 442 // case ROB_END_EXCEPTION_UPDATE : 443 // { 444 // entry->state = ROB_END_KO; 445 // throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); 446 // break; 447 // } 448 case ROB_END_LOAD_MISS_UPDATE : 449 { 450 log_printf(TRACE,Commit_unit,FUNCTION," * ROB_END_LOAD_MISS_UPDATE"); 451 452 entry->state = ROB_END_LOAD_MISS; 453 break; 454 } 455 default : 456 { 457 throw ERRORMORPHEO(FUNCTION,_("Update : invalid state.\n")); 458 break; 459 } 460 } 461 462 } 417 463 418 464 // =================================================================== … … 438 484 439 485 Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN[front_end_id][context_id]):0; 440 //Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0;441 //Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]);486 Tdepth_t depth_max = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MAX[front_end_id][context_id]):0; 487 Tcontrol_t depth_full = PORT_READ(in_DEPTH_FULL [front_end_id][context_id]); 442 488 443 489 // is a valid instruction ? … … 455 501 // ....... max ...X... min ....... KO 456 502 457 // Tcontrol_t is_valid = ((depth == depth_min) or458 // depth_full or459 // ((depth_min <= depth_max)?460 // ((depth >= depth_min) and (depth <=depth_max)):461 // ((depth >= depth_min) or (depth <=depth_max))));462 463 503 bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 464 Tcontrol_t is_valid = ((depth == depth_min) and not flush); 504 505 Tcontrol_t is_valid = (((depth == depth_min) or 506 depth_full or 507 ((depth_min <= depth_max)? 508 ((depth >= depth_min) and (depth <=depth_max)): 509 ((depth >= depth_min) or (depth <=depth_max)))) 510 and not flush); 511 512 // Tcontrol_t is_valid = ((depth == depth_min) and not flush); 465 513 466 514 log_printf(TRACE,Commit_unit,FUNCTION," * HEAD [%d]",i); 467 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ",is_valid);515 log_printf(TRACE,Commit_unit,FUNCTION," * is_valid : %d ((depth == depth_min) and not flush)",is_valid); 468 516 log_printf(TRACE,Commit_unit,FUNCTION," * depth : %d",depth ); 469 517 log_printf(TRACE,Commit_unit,FUNCTION," * depth_min : %d",depth_min); 470 // log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 518 log_printf(TRACE,Commit_unit,FUNCTION," * depth_max : %d",depth_max); 519 log_printf(TRACE,Commit_unit,FUNCTION," * depth_full : %d",depth_full); 471 520 log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 472 521 … … 481 530 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 482 531 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 532 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 483 533 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 484 534 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} … … 498 548 case ROB_END_KO : 499 549 case ROB_END_BRANCH_MISS : 550 case ROB_END_LOAD_MISS_UPDATE : 551 case ROB_END_LOAD_MISS : 552 case ROB_END_EXCEPTION_UPDATE : 500 553 case ROB_END_EXCEPTION : 501 554 default : … … 517 570 case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} 518 571 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 572 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 519 573 default : {break;} 520 574 } … … 528 582 switch (state) 529 583 { 530 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;}531 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION ; break;}584 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 585 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 532 586 default : {break;} 533 587 } … … 549 603 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 550 604 { 551 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] num_inst_all : %d, num_inst_mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]);552 605 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); 606 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); 607 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); 608 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x - %d %d",reg_PC_CURRENT [i][j], reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 609 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x",reg_PC_NEXT [i][j]); 553 610 } 554 611 … … 567 624 it++) 568 625 { 569 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %. 8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",626 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 570 627 x, 571 628 (*it)->front_end_id , … … 575 632 (*it)->type , 576 633 (*it)->operation , 577 578 634 // (*it)->address , 635 // (*it)->address << 2 , 579 636 (*it)->is_delay_slot , 580 637 (*it)->use_store_queue , … … 603 660 (*it)->num_reg_re_phy_new ); 604 661 605 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x ",662 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", 606 663 (*it)->exception_use , 607 664 (*it)->exception , 608 665 (*it)->flags , 609 666 (*it)->no_sequence , 610 (*it)->data_commit 667 (*it)->address_next , 668 (*it)->address_next<<2 611 669 ); 612 670 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp
r97 r105 59 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]);61 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 62 62 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 63 63 ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 84 84 ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); 85 85 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); 86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS",Taddress_t ,_param->_nb_inst_rename);86 ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS_NEXT ,"out_RENAME_OUT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_inst_rename); 87 87 ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); 88 88 ALLOC1_SC_SIGNAL(out_RENAME_OUT_IMMEDIAT ,"out_RENAME_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_rename); … … 121 121 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 122 122 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 123 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS 123 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 124 124 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 125 125 INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 149 149 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename); 150 150 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IS_DELAY_SLOT,_param->_nb_inst_rename); 151 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS 151 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS_NEXT ,_param->_nb_inst_rename); 152 152 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename); 153 153 INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IMMEDIAT ,_param->_nb_inst_rename); … … 213 213 in_RENAME_IN_NO_EXECUTE [i][j]->write(rand()%2); 214 214 in_RENAME_IN_IS_DELAY_SLOT[i][j]->write(rand()%2); 215 in_RENAME_IN_ADDRESS 215 in_RENAME_IN_ADDRESS_NEXT [i][j]->write(address++ ); 216 216 in_RENAME_IN_HAS_IMMEDIAT [i][j]->write(range<Tcontrol_t >(rand(),1 )); 217 217 in_RENAME_IN_IMMEDIAT [i][j]->write(range<Tgeneral_data_t >(rand(),_param->_size_general_data )); … … 259 259 260 260 // Test 261 address = out_RENAME_OUT_ADDRESS [i]->read();261 address = out_RENAME_OUT_ADDRESS_NEXT [i]->read(); 262 262 263 263 TEST(bool, address<nb_rename_in, true); … … 269 269 for (uint32_t x=0; x<_param->_nb_front_end; x++) 270 270 for (uint32_t y=0; y<_param->_nb_inst_decod[x]; y++) 271 if (in_RENAME_IN_ADDRESS [x][y]->read() == address)271 if (in_RENAME_IN_ADDRESS_NEXT [x][y]->read() == address) 272 272 { 273 273 find = true; … … 329 329 delete [] in_RENAME_IN_NO_EXECUTE ; 330 330 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 331 delete [] in_RENAME_IN_ADDRESS 331 delete [] in_RENAME_IN_ADDRESS_NEXT ; 332 332 delete [] in_RENAME_IN_HAS_IMMEDIAT ; 333 333 delete [] in_RENAME_IN_IMMEDIAT ; … … 354 354 delete [] out_RENAME_OUT_NO_EXECUTE ; 355 355 delete [] out_RENAME_OUT_IS_DELAY_SLOT; 356 delete [] out_RENAME_OUT_ADDRESS 356 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 357 357 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; 358 358 delete [] out_RENAME_OUT_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h
r97 r105 76 76 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 78 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS 78 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 102 102 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] 103 103 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] 104 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS 104 public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS_NEXT ;//[nb_inst_rename] 105 105 public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] 106 106 public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_IMMEDIAT ;//[nb_inst_rename] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp
r88 r105 97 97 << (*(in_RENAME_IN_NO_EXECUTE [i][j])) 98 98 << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])) 99 << (*(in_RENAME_IN_ADDRESS 99 << (*(in_RENAME_IN_ADDRESS_NEXT [i][j])) 100 100 << (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])) 101 101 << (*(in_RENAME_IN_IMMEDIAT [i][j])) … … 163 163 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_VAL [i][j])); 164 164 (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])); 165 (*(out_RENAME_OUT_ADDRESS 166 (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_ADDRESS[i][j]));165 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_VAL [i][j])); 166 (*(out_RENAME_OUT_ADDRESS_NEXT [x])) (*(in_RENAME_IN_ADDRESS_NEXT [i][j])); 167 167 (*(out_RENAME_OUT_HAS_IMMEDIAT [x])) (*(in_RENAME_IN_VAL [i][j])); 168 168 (*(out_RENAME_OUT_HAS_IMMEDIAT [x])) (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp
r97 r105 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 99 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address );101 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp
r88 r105 40 40 delete [] in_RENAME_IN_NO_EXECUTE ; 41 41 delete [] in_RENAME_IN_IS_DELAY_SLOT ; 42 delete [] in_RENAME_IN_ADDRESS 42 delete [] in_RENAME_IN_ADDRESS_NEXT ; 43 43 delete [] in_RENAME_IN_HAS_IMMEDIAT ; 44 44 delete [] in_RENAME_IN_IMMEDIAT ; … … 66 66 delete [] out_RENAME_OUT_TYPE ; 67 67 delete [] out_RENAME_OUT_OPERATION ; 68 delete [] out_RENAME_OUT_ADDRESS 68 delete [] out_RENAME_OUT_ADDRESS_NEXT ; 69 69 delete [] out_RENAME_OUT_HAS_IMMEDIAT ; 70 70 delete [] out_RENAME_OUT_IMMEDIAT ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp
r88 r105 75 75 PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); 76 76 PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y])); 77 PORT_WRITE(out_RENAME_OUT_ADDRESS [i],PORT_READ(in_RENAME_IN_ADDRESS[x][y]));77 PORT_WRITE(out_RENAME_OUT_ADDRESS_NEXT [i],PORT_READ(in_RENAME_IN_ADDRESS_NEXT [x][y])); 78 78 PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT [x][y])); 79 79 PORT_WRITE(out_RENAME_OUT_IMMEDIAT [i],PORT_READ(in_RENAME_IN_IMMEDIAT [x][y])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp
r104 r105 57 57 ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);59 ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ," in_RENAME_IN_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 81 81 ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,"out_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_insert); 82 82 ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,"out_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_insert); 83 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS ,"out_INSERT_ADDRESS",Tgeneral_data_t ,_param->_nb_inst_insert);83 ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,"out_INSERT_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_insert); 84 84 ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,"out_INSERT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_insert); 85 85 ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT ,"out_INSERT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_insert); … … 155 155 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 156 156 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 157 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS 157 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 158 158 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 159 159 INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 183 183 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 184 184 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 185 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS 185 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 186 186 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); 187 187 INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); … … 297 297 DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 298 298 DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 299 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS 299 DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 300 300 DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); 301 301 DELETE2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 322 322 DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); 323 323 DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); 324 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS 324 DELETE1_SC_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert); 325 325 DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); 326 326 DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h
r104 r105 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 79 79 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 80 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS 80 public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 82 82 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 104 104 public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] 105 105 public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] 106 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS 106 public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS_NEXT ;//[nb_inst_insert] 107 107 public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] 108 108 public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp
r104 r105 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]);71 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 72 72 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); 73 73 _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); … … 99 99 ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); 100 100 ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); 101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address",Taddress_t ,_param->_size_instruction_address );101 ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address ); 102 102 ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 103 103 ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); … … 301 301 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT", 302 302 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT"); 303 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS ",304 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS ");303 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , 304 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); 305 305 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" , 306 306 dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); … … 349 349 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_DEPTH" , 350 350 dest,"out_INSERT_" +toString(i)+"_DEPTH" ); 351 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS ",352 dest,"out_INSERT_" +toString(i)+"_ADDRESS ");351 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS_NEXT", 352 dest,"out_INSERT_" +toString(i)+"_ADDRESS_NEXT"); 353 353 PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_HAS_IMMEDIAT", 354 354 dest,"out_INSERT_" +toString(i)+"_HAS_IMMEDIAT"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp
r104 r105 37 37 DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 38 38 DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 39 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data);39 DELETE2_SIGNAL( in_RENAME_IN_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_instruction_address ); 40 40 DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); 41 41 DELETE2_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); … … 62 62 DELETE1_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert,1 ); 63 63 DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); 64 DELETE1_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_general_data);64 DELETE1_SIGNAL(out_INSERT_ADDRESS_NEXT ,_param->_nb_inst_insert,_param->_size_instruction_address ); 65 65 DELETE1_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert,1 ); 66 66 DELETE1_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert,_param->_size_general_data ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
r101 r105 57 57 ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 58 58 ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);59 ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ," in_RENAME_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 60 60 ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 61 61 ALLOC2_SC_SIGNAL( in_RENAME_IMMEDIAT ," in_RENAME_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 143 143 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); 144 144 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); 145 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL ",Tcontrol_t ); 145 146 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); 146 147 ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); … … 193 194 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 194 195 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 195 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS 196 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 196 197 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 197 198 INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 292 293 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); 293 294 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); 295 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 294 296 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); 295 297 INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); … … 376 378 DELETE2_SC_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 377 379 DELETE2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 378 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS 380 DELETE2_SC_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 379 381 DELETE2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 380 382 DELETE2_SC_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 462 464 DELETE_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ); 463 465 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ); 466 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ); 464 467 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ); 465 468 DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
r101 r105 77 77 public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] 78 78 public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] 79 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS 79 public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS_NEXT ;//[nb_front_end][nb_inst_decod] 80 80 public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] 81 81 public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IMMEDIAT ;//[nb_front_end][nb_inst_decod] … … 169 169 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_IS_DELAY_SLOT ; 170 170 public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS ; 171 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EPCR_VAL ; 171 172 public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EPCR ; 172 173 public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r104 r105 66 66 _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 67 67 _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS",Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]);68 _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 69 69 _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); 70 70 _ALLOC2_SIGNAL_IN ( in_RENAME_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); … … 182 182 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); 183 183 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); 184 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,"ADDRESS_EPCR_VAL" ,Tcontrol_t ,1 ); 184 185 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); 185 186 ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); … … 412 413 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT", 413 414 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT"); 414 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS ",415 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS ");415 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS_NEXT" , 416 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" ); 416 417 PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_HAS_IMMEDIAT" , 417 418 dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_HAS_IMMEDIAT" ); … … 476 477 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , 477 478 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); 478 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS ",479 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS ");479 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS_NEXT" , 480 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); 480 481 COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_EXCEPTION_USE" , 481 482 dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_EXCEPTION_USE" ); … … 754 755 755 756 // in_INSERT_DEPTH - component_rename_unit 756 // in_INSERT_ADDRESS 757 // in_INSERT_ADDRESS_NEXT - component_rename_unit 757 758 // in_INSERT_EXCEPTION_USE - component_rename_unit 758 759 // in_INSERT_EXCEPTION - component_rename_unit … … 946 947 PORT_MAP(_component,src ,"out_UPDATE_IS_DELAY_SLOT" ,dest,"out_COMMIT_EVENT_IS_DELAY_SLOT" ); 947 948 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS" ,dest,"out_COMMIT_EVENT_ADDRESS" ); 949 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EPCR_VAL",dest,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL"); 948 950 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EPCR" ,dest,"out_COMMIT_EVENT_ADDRESS_EPCR" ); 949 951 PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EEAR_VAL",dest,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
r101 r105 36 36 DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 37 37 DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 38 DELETE2_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data);38 DELETE2_SIGNAL( in_RENAME_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); 39 39 DELETE2_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); 40 40 DELETE2_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data ); … … 84 84 DELETE2_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_exception ); 85 85 DELETE2_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); 86 DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_ general_data);86 DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_instruction_address ); 87 87 DELETE2_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data ); 88 88 … … 110 110 DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); 111 111 DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); 112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_ general_data);112 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 113 113 DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); 114 114 DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); … … 122 122 DELETE_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); 123 123 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); 124 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR_VAL ,1 ); 124 125 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); 125 126 DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); … … 128 129 DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 129 130 DELETE2_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 130 DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_ general_data);131 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_ general_data);131 DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_instruction_address); 132 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_instruction_address); 132 133 DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); 133 134 DELETE2_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp
r101 r105 286 286 // out_DECOD_NO_EXECUTE - ooo_engine. in_RENAME_NO_EXECUTE 287 287 // out_DECOD_IS_DELAY_SLOT - ooo_engine. in_RENAME_IS_DELAY_SLOT 288 // out_DECOD_ADDRESS - ooo_engine. in_RENAME_ADDRESS288 // out_DECOD_ADDRESS_NEXT - ooo_engine. in_RENAME_ADDRESS_NEXT 289 289 // out_DECOD_HAS_IMMEDIAT - ooo_engine. in_RENAME_HAS_IMMEDIAT 290 290 // out_DECOD_IMMEDIAT - ooo_engine. in_RENAME_IMMEDIAT … … 353 353 COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS" , 354 354 dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS" ); 355 COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR_VAL", 356 dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS_EPCR_VAL"); 355 357 COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR" , 356 358 dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS_EPCR" ); … … 455 457 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT", 456 458 dest,"out_DECOD_" +toString(k)+"_IS_DELAY_SLOT"); 457 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_ADDRESS ",458 dest,"out_DECOD_" +toString(k)+"_ADDRESS ");459 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" , 460 dest,"out_DECOD_" +toString(k)+"_ADDRESS_NEXT" ); 459 461 COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_HAS_IMMEDIAT" , 460 462 dest,"out_DECOD_" +toString(k)+"_HAS_IMMEDIAT" ); … … 553 555 COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS" , 554 556 dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS" ); 557 COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS_EPCR_VAL", 558 dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS_EPCR_VAL"); 555 559 COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS_EPCR" , 556 560 dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS_EPCR" ); … … 1274 1278 // out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT - front_end. in_COMMIT_EVENT_IS_DELAY_SLOT 1275 1279 // out_COMMIT_EVENT_FRONT_END_ADDRESS - front_end. in_COMMIT_EVENT_ADDRESS 1280 // out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR_VAL - front_end. in_COMMIT_EVENT_ADDRESS_EPCR_VAL 1276 1281 // out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR - front_end. in_COMMIT_EVENT_ADDRESS_EPCR 1277 1282 // out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL - front_end. in_COMMIT_EVENT_ADDRESS_EEAR_VAL … … 1286 1291 // in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT - ooo_engine.out_COMMIT_EVENT_IS_DELAY_SLOT 1287 1292 // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS - ooo_engine.out_COMMIT_EVENT_ADDRESS 1293 // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR_VAL- ooo_engine.out_COMMIT_EVENT_ADDRESS_EPCR_VAL 1288 1294 // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR - ooo_engine.out_COMMIT_EVENT_ADDRESS_EPCR 1289 1295 // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL- ooo_engine.out_COMMIT_EVENT_ADDRESS_EEAR_VAL -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r104 r105 598 598 599 599 # define EVENT_TYPE_NONE 0 // no event 600 # define EVENT_TYPE_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) 601 # define EVENT_TYPE_EXCEPTION 2 // exception or interruption occure 602 # define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss) 600 # define EVENT_TYPE_BRANCH_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) 601 # define EVENT_TYPE_LOAD_MISS_SPECULATION 2 // miss of speculation (load or branch miss speculation) 602 # define EVENT_TYPE_EXCEPTION 3 // exception or interruption occure 603 //#define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss) 603 604 # define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction 604 605 # define EVENT_TYPE_MSYNC 5 // decod a memory synchronization -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r104 r105 10 10 #define MORPHEO_MAJOR_VERSION 0 11 11 #define MORPHEO_MINOR_VERSION 2 12 #define MORPHEO_REVISION "10 4"12 #define MORPHEO_REVISION "105" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY " 21"16 #define MORPHEO_DATE_MONTH "0 1"15 #define MORPHEO_DATE_DAY "05" 16 #define MORPHEO_DATE_MONTH "02" 17 17 #define MORPHEO_DATE_YEAR "2009" 18 18 -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg
r104 r105 6 6 <parameter name="size_ifetch_queue" value="4" /> 7 7 <parameter name="nb_inst_fetch" value="1" /> 8 <parameter name="ras_size_queue" value=" 2" />9 <parameter name="upt_size_queue" value=" 2" />10 <parameter name="ufpt_size_queue" value=" 1" />8 <parameter name="ras_size_queue" value="4" /> 9 <parameter name="upt_size_queue" value="4" /> 10 <parameter name="ufpt_size_queue" value="4" /> 11 11 12 12 <group id="0"> … … 47 47 <parameter name="nb_bypass_write" value="0" /> 48 48 </write_bloc> 49 49 50 <write_bloc id="1"> 51 <parameter name="size_write_queue" value="4" /> 52 <parameter name="size_execute_queue" value="4" /> 53 <parameter name="nb_bypass_write" value="0" /> 54 </write_bloc> 55 50 56 <load_store_unit id="0"> 51 <parameter name="size_store_queue" value=" 2" />52 <parameter name="size_load_queue" value=" 1" />53 <parameter name="size_speculative_access_queue" value=" 1" />57 <parameter name="size_store_queue" value="4" /> 58 <parameter name="size_load_queue" value="4" /> 59 <parameter name="size_speculative_access_queue" value="2" /> 54 60 <parameter name="nb_port_check" value="1" /> 55 61 <parameter name="speculative_load" value="2" /> … … 130 136 <execute_loop id="0"> 131 137 <parameter name="nb_read_unit" value="1" /> 132 <parameter name="nb_write_unit" value=" 1" />138 <parameter name="nb_write_unit" value="2" /> 133 139 <parameter name="nb_gpr_bank" value="1" /> 134 140 <parameter name="nb_gpr_port_read_by_bank" value="2" /> … … 166 172 <link name="link_read_unit_with_read_bloc" src="0" dest="0.0" /> 167 173 <link name="link_write_unit_with_write_bloc" src="0" dest="0.0" /> 174 <link name="link_write_unit_with_write_bloc" src="1" dest="0.1" /> 168 175 <link name="link_decod_bloc_with_thread" src="0" dest="0" /> 169 176 <link name="link_rename_bloc_with_front_end" src="0" dest="0" /> … … 177 184 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="1" /> 178 185 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 186 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> 179 187 <link name="link_write_bloc_and_functionnal_unit" src="0.0" dest="1" /> 188 <link name="link_write_bloc_and_functionnal_unit" src="1.0" dest="1" /> 180 189 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 181 190 -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r104 r105 8 8 <parameter name="use_vhdl_testbench_assert" value="0" /> 9 9 <parameter name="use_position" value="0" /> 10 <parameter name="use_statistics" value=" 0" />10 <parameter name="use_statistics" value="1" /> 11 11 <parameter name="use_information" value="0" /> 12 12 <parameter name="use_header" value="0" /> … … 15 15 <parameter name="statistics_period" value="0" /> 16 16 17 <parameter name="simulation_nb_cycle" value="100 " />17 <parameter name="simulation_nb_cycle" value="100000" /> 18 18 <parameter name="simulation_nb_instruction" value="0" /> 19 19 … … 23 23 <parameter name="directory_log" value="." /> 24 24 25 <parameter name="debug_level" value=" 3" />25 <parameter name="debug_level" value="0" /> 26 26 <parameter name="debug_cycle_start" value="0" /> 27 27 <parameter name="debug_cycle_stop" value="200" /> -
trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh
r88 r105 114 114 function usage () 115 115 { 116 echo "Usage : ${0} action";117 echo "Arguments : ";116 echo "Usage : ${0} action"; 117 echo "Arguments : "; 118 118 echo " * action"; 119 echo " * test : test all component"; 120 echo ' for each component, create file in ${MORPHEO_HOME}/tmp/'; 121 echo " * test_all : same as test, but don't stop at the first error"; 122 echo " * res : list test's resultat"; 123 echo " * list : list test's resultat"; 124 echo " * clean : erase file in ${MORPHEO_HOME}/tmp/ directory"; 125 echo " * clean_all : clean all component"; 126 echo " * help : print this message"; 119 echo " * systemc : test all model systemC"; 120 echo ' for each component, create file in ${MORPHEO_HOME}/tmp/'; 121 echo " * systemc_all : same as test, but don't stop at the first error"; 122 echo " * vhdl : test all model VHDL"; 123 echo ' for each component, create file in ${MORPHEO_HOME}/tmp/'; 124 echo " * vhdl_all : same as test, but don't stop at the first error"; 125 echo " * result : list test's resultat"; 126 echo " * list : list test"; 127 echo " * clean : erase file in ${MORPHEO_HOME}/tmp/ directory"; 128 echo " * clean_all : clean all component"; 129 echo " * help : print this message"; 127 130 echo ""; 128 echo "Notes : ";131 echo "Notes : "; 129 132 echo " * Morpheo environment must be positionned"; 130 133 exit; 134 } 135 136 #-----[ simulation ]---------------------------------------- 137 # arg1 : cmd (execute / sim) 138 # arg2 : all (stop) 139 # arg3 : file suffix 140 function simulation () 141 { 142 pwd=${PWD}; 143 144 nb_cpu=$(cat /proc/cpuinfo |grep -c processor); 145 146 for i in ${directory[@]}; do 147 component=$(basename ${i}); 148 dir="${path}/${i}/SelfTest"; 149 150 if test -d "${dir}"; then 151 # have previous test ok ? 152 declare -i make_test=1; 153 154 file="${tmp}/${component}.${3}" 155 156 if test -f ${file}; then 157 res_test=$(cat ${file}); 158 if test "${test_ok}" = "${res_test}"; then 159 make_test=0; 160 fi; 161 fi; 162 163 if test ${make_test} -eq 1; then 164 cd ${dir}; 165 make config; 166 make -j${nb_cpu} ${1}; 167 case ${?} in 168 "0") 169 echo ${test_ok} > ${file}; 170 ;; 171 *) 172 173 echo ${test_ko} > ${file}; 174 echo ""; 175 echo "${component} : ${test_ko}"; 176 echo ""; 177 if test ${2} = "1"; then 178 exit 1; 179 fi; 180 ;; 181 esac; 182 make clean; 183 fi; 184 else 185 echo "${component} have not SelfTest directory."; 186 fi; 187 188 cd ${pwd}; 189 done; 131 190 } 132 191 … … 139 198 fi; 140 199 141 if test -z ${MORPHEO_TOPLEVEL}; then200 if test -z "${MORPHEO_TOPLEVEL}"; then 142 201 usage ${*}; 143 202 fi; … … 147 206 fi; 148 207 149 nb_cpu=$(cat /proc/cpuinfo |grep -c processor);150 pwd=${PWD};151 208 case ${1} in 152 "test" | "test_all") 153 for i in ${directory[@]}; do 154 component=$(basename ${i}); 155 dir="${path}/${i}/SelfTest"; 156 157 if test -d "${dir}"; then 158 # have previous test ok ? 159 declare -i make_test=1; 160 161 if test -f ${tmp}/${component}; then 162 res_test=$(cat ${tmp}/${component}); 163 if test "${test_ok}" = "${res_test}"; then 164 make_test=0; 165 fi; 209 "systemc" ) 210 simulation "execute" "1" "systemc"; 211 ;; 212 213 "systemc_all") 214 simulation "execute" "0" "systemc"; 215 ;; 216 217 "vhdl" ) 218 simulation "sim" "1" "vhdl"; 219 ;; 220 221 "vhdl_all") 222 simulation "sim" "0" "vhdl"; 223 ;; 224 225 "result") 226 for x in "systemc" "vhdl"; do 227 echo "${x}"; 228 for i in ${tmp}/*.${x}; do 229 if test -f ${i}; then 230 component=$(basename ${i} .${x}); 231 res_test=$(cat ${i}); 232 233 case "${res_test}" in 234 "${test_ok}") color=32; 235 ;; 236 "${test_ko}") color=31; 237 ;; 238 *) color=39; 239 ;; 240 esac 241 echo "[1;${color}m * ${res_test} - ${component}[1;0m"; 166 242 fi; 167 168 if test ${make_test} -eq 1; then 169 cd ${dir}; 170 make config; 171 make -j${nb_cpu} execute; 172 case ${?} in 173 "0") 174 echo ${test_ok} > ${tmp}/"${component}"; 175 ;; 176 *) 177 178 echo ${test_ko} > ${tmp}/"${component}"; 179 echo ""; 180 echo "${component} : ${test_ko}"; 181 echo ""; 182 if test ${1} = "test"; then 183 exit 1; 184 fi; 185 ;; 186 esac; 187 fi; 188 else 189 echo "${component} have not SelfTest directory."; 190 fi; 191 192 cd ${pwd}; 193 done; 194 ;; 195 196 "res") 197 for i in ${tmp}/*; do 198 if test -f ${i}; then 199 component=$(basename ${i}); 200 res_test=$(cat ${i}); 201 202 203 case "${res_test}" in 204 "${test_ok}") color=32; 205 ;; 206 "${test_ko}") color=31; 207 ;; 208 *) color=39; 209 ;; 210 esac 211 echo "[1;${color}m${res_test} - ${component}[1;0m"; 212 fi; 213 done; 214 ;; 243 done; 244 done; 245 ;; 246 215 247 216 248 "list") … … 226 258 227 259 "clean_all") 260 pwd=${PWD}; 261 228 262 for i in ${directory[@]}; do 229 263 component=$(basename ${i});
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