Ignore:
Timestamp:
Feb 12, 2009, 12:55:06 PM (15 years ago)
Author:
rosiere
Message:

1) decod_queue : add reg_LAST_SLOT.
2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not)
3) Context State / UPT : Branch miss and Load miss in same cycle.
4) Free List : Bank is on LSB not MSB.
5) Platforms : move data

File:
1 edited

Legend:

Unmodified
Added
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  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp

    r105 r108  
    3131        for (uint32_t i=0; i<_param->_nb_context; i++)
    3232          reg_NB_INST [i]=0;
     33
     34        reg_LAST_SLOT = 0;
    3335      }
    3436    else
     
    6264                entry->_no_execute    [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE    [i]);
    6365                entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]);
     66#ifdef DEBUG
     67                entry->_address       [i] = PORT_READ(in_DECOD_IN_ADDRESS       [i]);
     68#endif
    6469                entry->_address_next  [i] = PORT_READ(in_DECOD_IN_ADDRESS_NEXT  [i]);
    6570                entry->_has_immediat  [i] = PORT_READ(in_DECOD_IN_HAS_IMMEDIAT  [i]);
     
    9095        if (not reg_QUEUE->empty())
    9196          {
    92             bool find = false;
     97            bool find = false;
    9398           
    9499            for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
    95100              {
    96101                // Test transaction : if ok then invalid slot
     102                // In order by rename logic
    97103                if (internal_DECOD_OUT_VAL [i] and internal_DECOD_OUT_ACK[i])
    98104                  {
    99105                    log_printf(TRACE,Decod_queue,FUNCTION,_("  * DECOD_OUT [%d]"),i);
    100106               
     107#ifdef DEBUG_TEST
     108                    if (reg_LAST_SLOT != i)
     109                      throw ERRORMORPHEO(FUNCTION,toString(_("reg_LAST_SLOT (%d) is different at decod_out port (%d)."),reg_LAST_SLOT,i));
     110#endif
     111                    reg_LAST_SLOT ++;
     112
    101113                    reg_QUEUE->front()->_val [i] = 0;
    102114
     
    108120                  }
    109121                // Test if slot is (again) valid, if yes, then have less one instruction in the entry
    110                 find |= reg_QUEUE->front()->_val [i];
     122                find |= reg_QUEUE->front()->_val [i];
    111123              }
    112124           
    113             // test if can free the entry
    114             if (not find) // no valid instruction in current slot
     125            // test if can free the entry : test if have consume all entry
     126            if (not find) // no valid instruction in current slot
    115127              {
    116128                log_printf(TRACE,Decod_queue,FUNCTION,_("    * POP  queue"));
     
    119131                delete reg_QUEUE->front();
    120132                reg_QUEUE->pop_front();
     133
     134                reg_LAST_SLOT = 0;
    121135              }
    122136          }
     
    125139#if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE)
    126140    log_printf(TRACE,Decod_queue,FUNCTION,"  * Dump decod_queue");
     141    log_printf(TRACE,Decod_queue,FUNCTION,"    * reg_LAST_SLOT : %d",reg_LAST_SLOT);
    127142    uint32_t x=0;
    128143    for (std::list<decod_queue_entry_t*>::iterator it=reg_QUEUE->begin();
     
    144159                         ,(*it)->_no_execute    [i]
    145160                         ,(*it)->_is_delay_slot [i]
    146                          ,(*it)->_address_next  [i]
    147                          ,(*it)->_address_next  [i]<<2
     161                         ,(*it)->_address       [i]
     162                         ,(*it)->_address       [i]<<2
    148163                         ,(*it)->_has_immediat  [i]
    149164                         ,(*it)->_immediat      [i]
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