Changeset 108 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
- Timestamp:
- Feb 12, 2009, 12:55:06 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r106 r108 77 77 case EVENT_STATE_WAITEND : 78 78 { 79 if (reg_NB_INST_COMMIT_ALL [i][j] == 0) 79 Tcounter_t nb_inst_all = PORT_READ(in_NB_INST_DECOD_ALL [i][j]) + reg_NB_INST_COMMIT_ALL [i][j]; 80 if (nb_inst_all == 0) 80 81 { 81 82 reg_EVENT_STATE [i][j] = EVENT_STATE_END; … … 163 164 entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); 164 165 entry->no_sequence = type == TYPE_BRANCH; 166 entry->speculative = true; 167 #ifdef DEBUG 168 entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); 169 #endif 165 170 entry->address_next = PORT_READ(in_INSERT_ADDRESS_NEXT [x][y]); 166 171 … … 173 178 // other -> wait end of instruction 174 179 // * OTHER 175 if (exception == EXCEPTION_NONE) 176 { 177 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 178 // no_execute : l.j, l.nop, l.rfe 179 180 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 181 182 switch (type) 183 { 184 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} 185 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 186 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 187 } 188 } 189 else 190 { 191 // Have an exception : wait head of ROB 192 193 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 194 195 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 196 } 180 181 // bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 182 183 // log_printf(TRACE,Commit_unit,FUNCTION," * flush : %d",flush); 184 185 // if (flush) 186 // { 187 // entry->state = ROB_END_MISS; // All type (branch, memory and others), because, is not execute 188 // } 189 // else 190 { 191 if (exception == EXCEPTION_NONE) 192 { 193 Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); 194 // no_execute : l.j, l.nop, l.rfe 195 196 log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); 197 198 switch (type) 199 { 200 case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END ; break;} 201 case TYPE_MEMORY : {entry->state=(is_store ==1)?ROB_STORE_WAIT_HEAD_OK:ROB_OTHER_WAIT_END; break;} 202 default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} 203 } 204 } 205 else 206 { 207 // Have an exception : wait head of ROB 208 209 // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap 210 211 entry->state = ROB_END_EXCEPTION_WAIT_HEAD; 212 } 213 } 197 214 198 215 // Push in rob … … 351 368 Ttype_t type = entry->type ; 352 369 353 if ((state == ROB_END_OK ) or // LOAD_MISS370 if ((state == ROB_END_OK ) or 354 371 // (state == ROB_END_KO ) or 355 (state == ROB_END_BRANCH_MISS) //or356 // (state == ROB_END_LOAD_MISS )or372 (state == ROB_END_BRANCH_MISS) or 373 (state == ROB_END_LOAD_MISS )// or 357 374 // (state == ROB_END_MISS ) or 358 375 // (state == ROB_END_EXCEPTION ) … … 468 485 // =====[ EVENT ]===================================================== 469 486 // =================================================================== 470 { 471 // Not yet implemented 472 } 487 // for (uint32_t i=0; i < _param->_nb_front_end; ++i) 488 // for (uint32_t j=0; j < _param->_nb_context[i]; ++j) 489 // if (PORT_READ(in_EVENT_VAL [i][j]) and internal_EVENT_ACK [i][j]) 490 // { 491 // log_printf(TRACE,Commit_unit,FUNCTION," * EVENT [%d][%d]",i,j); 492 493 // reg_PC_CURRENT [i][j] = PORT_READ(in_EVENT_ADDRESS [i][j]); 494 // reg_PC_CURRENT_IS_DS [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); // ?? 495 // reg_PC_CURRENT_IS_DS_TAKE [i][j] = PORT_READ(in_EVENT_IS_DS_TAKE [i][j]); 496 // reg_PC_NEXT [i][j] = PORT_READ(in_EVENT_ADDRESS_NEXT [i][j]); 497 // // PORT_READ(in_EVENT_ADDRESS_NEXT_VAL [i][j]); 498 // } 473 499 474 500 // =================================================================== … … 505 531 506 532 bool flush = reg_EVENT_FLUSH [front_end_id][context_id]; 507 508 Tcontrol_t is_valid = (( (depth == depth_min)or509 depth_full or510 ((depth_min <= depth_max)?511 ((depth >= depth_min) and (depth <=depth_max)):512 ((depth >= depth_min) or (depth <=depth_max))))533 bool speculative = entry->speculative and not (depth == depth_min); 534 Tcontrol_t is_valid = ((not speculative or 535 (speculative and (depth_full or // all is valid 536 ((depth_min <= depth_max)? // test if depth is overflow 537 ((depth >= depth_min) and (depth <=depth_max)): 538 ((depth >= depth_min) or (depth <=depth_max)))))) 513 539 and not flush); 514 540 … … 532 558 case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 533 559 case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} 560 case ROB_END_BRANCH_MISS : 534 561 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 562 case ROB_END_LOAD_MISS_UPDATE : 563 case ROB_END_LOAD_MISS : 535 564 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_MISS ; break;} 536 565 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} 537 566 //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} 538 567 case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} 568 case ROB_END_OK : 539 569 case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} 570 case ROB_END_KO : 540 571 case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} 572 case ROB_END_EXCEPTION_UPDATE : 573 case ROB_END_EXCEPTION : 541 574 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} 542 575 … … 548 581 // can't have miss speculation 549 582 case ROB_STORE_HEAD_OK : 550 case ROB_END_OK :551 case ROB_END_KO :552 case ROB_END_BRANCH_MISS :553 case ROB_END_LOAD_MISS_UPDATE :554 case ROB_END_LOAD_MISS :555 case ROB_END_EXCEPTION_UPDATE :556 case ROB_END_EXCEPTION :557 583 default : 558 584 { 559 throw ERRORMORPHEO(FUNCTION, _("Miss Speculation : Invalide state.\n"));585 throw ERRORMORPHEO(FUNCTION,toString(_("Miss Speculation : Invalide state : %s.\n"),toString(state).c_str())); 560 586 break; 561 587 } … … 566 592 // test if instruction is not speculative 567 593 //------------------------------------------------------ 568 if (entry->depth == depth_min) 594 entry->speculative = speculative; 595 // if (entry->depth == depth_min) 596 if (not speculative) 569 597 { 570 598 switch (state) … … 574 602 case ROB_END_BRANCH_MISS_SPECULATIVE : {state = ROB_END_BRANCH_MISS ; break;} 575 603 case ROB_END_LOAD_MISS_SPECULATIVE : {state = ROB_END_LOAD_MISS_UPDATE ; break;} 576 default : {break;} 604 default : {break;} // else, no change 577 605 } 578 606 } … … 587 615 case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} 588 616 case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION_UPDATE; break;} 589 default : {break;} 617 default : {break;} // else, no change 590 618 } 591 619 } … … 599 627 // =================================================================== 600 628 601 log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); 602 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); 603 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); 604 605 for (uint32_t i=0; i<_param->_nb_front_end; i++) 606 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 629 #ifdef STATISTICS 630 for (uint32_t i=0; i<_param->_nb_bank; i++) 631 if (usage_is_set(_usage,USE_STATISTICS)) 632 *(_stat_bank_nb_inst [i]) += _rob[i].size(); 633 #endif 634 635 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Commit_unit == true) 636 { 637 log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); 638 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); 639 log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); 640 641 for (uint32_t i=0; i<_param->_nb_front_end; i++) 642 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 643 { 644 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d]",i,j); 645 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_STATE : %s",toString(reg_EVENT_STATE [i][j]).c_str()); 646 log_printf(TRACE,Commit_unit,FUNCTION," * EVENT_FLUSH : %d",reg_EVENT_FLUSH [i][j]); 647 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_ALL : %d",reg_NB_INST_COMMIT_ALL[i][j]); 648 log_printf(TRACE,Commit_unit,FUNCTION," * NB_INST_MEM : %d",reg_NB_INST_COMMIT_MEM[i][j]); 649 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 650 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 651 } 652 653 for (uint32_t i=0; i<_param->_nb_bank; i++) 607 654 { 608 log_printf(TRACE,Commit_unit,FUNCTION," * [%d][%d] state : %s",i,j,toString(reg_EVENT_STATE [i][j]).c_str()); 609 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_all : %d",reg_NB_INST_COMMIT_ALL[i][j]); 610 log_printf(TRACE,Commit_unit,FUNCTION," * num_inst_mem : %d",reg_NB_INST_COMMIT_MEM[i][j]); 611 log_printf(TRACE,Commit_unit,FUNCTION," * PC_CURRENT : %.8x (%.8x) - %d %d",reg_PC_CURRENT [i][j],reg_PC_CURRENT [i][j]<<2, reg_PC_CURRENT_IS_DS [i][j], reg_PC_CURRENT_IS_DS_TAKE [i][j]); 612 log_printf(TRACE,Commit_unit,FUNCTION," * PC_NEXT : %.8x (%.8x)",reg_PC_NEXT [i][j],reg_PC_NEXT [i][j]<<2); 655 uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; 656 657 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",num_bank,(int)_rob[num_bank].size(), reg_BANK_PTR [i]); 658 659 uint32_t x=0; 660 for (std::list<entry_t*>::iterator it=_rob[num_bank].begin(); 661 it!=_rob[num_bank].end(); 662 it++) 663 { 664 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 665 x, 666 (*it)->front_end_id , 667 (*it)->context_id , 668 (*it)->rename_unit_id , 669 (*it)->depth , 670 (*it)->type , 671 (*it)->operation , 672 (*it)->is_delay_slot , 673 (*it)->use_store_queue , 674 (*it)->store_queue_ptr_write , 675 (*it)->use_load_queue , 676 (*it)->load_queue_ptr_write , 677 toString((*it)->state).c_str() , 678 (*it)->ptr ); 679 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 680 (*it)->read_ra , 681 (*it)->num_reg_ra_log , 682 (*it)->num_reg_ra_phy , 683 (*it)->read_rb , 684 (*it)->num_reg_rb_log , 685 (*it)->num_reg_rb_phy , 686 (*it)->read_rc , 687 (*it)->num_reg_rc_log , 688 (*it)->num_reg_rc_phy , 689 (*it)->write_rd , 690 (*it)->num_reg_rd_log , 691 (*it)->num_reg_rd_phy_old , 692 (*it)->num_reg_rd_phy_new , 693 (*it)->write_re , 694 (*it)->num_reg_re_log , 695 (*it)->num_reg_re_phy_old , 696 (*it)->num_reg_re_phy_new ); 697 698 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.1d - %.8x (%.8x) %.8x (%.8x)", 699 (*it)->exception_use , 700 (*it)->exception , 701 (*it)->flags , 702 (*it)->no_sequence , 703 (*it)->speculative , 704 (*it)->address , 705 (*it)->address<<2 , 706 (*it)->address_next , 707 (*it)->address_next<<2 708 ); 709 710 x++; 711 } 613 712 } 614 615 for (uint32_t i=0; i<_param->_nb_bank; i++) 616 { 617 log_printf(TRACE,Commit_unit,FUNCTION," * Bank [%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); 618 619 #ifdef STATISTICS 620 if (usage_is_set(_usage,USE_STATISTICS)) 621 *(_stat_bank_nb_inst [i]) += _rob[i].size(); 622 #endif 623 624 uint32_t x=0; 625 for (std::list<entry_t*>::iterator it=_rob[i].begin(); 626 it!=_rob[i].end(); 627 it++) 628 { 629 log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.1d, %.1d %.4d, %.1d %.4d, %s - %d", 630 x, 631 (*it)->front_end_id , 632 (*it)->context_id , 633 (*it)->rename_unit_id , 634 (*it)->depth , 635 (*it)->type , 636 (*it)->operation , 637 // (*it)->address , 638 // (*it)->address << 2 , 639 (*it)->is_delay_slot , 640 (*it)->use_store_queue , 641 (*it)->store_queue_ptr_write , 642 (*it)->use_load_queue , 643 (*it)->load_queue_ptr_write , 644 toString((*it)->state).c_str() , 645 (*it)->ptr ); 646 log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.2d %.6d, %.1d %.2d %.6d, %.1d %.1d %.6d, %.1d %.2d %.6d %.6d, %.1d %.1d %.6d %.6d ", 647 (*it)->read_ra , 648 (*it)->num_reg_ra_log , 649 (*it)->num_reg_ra_phy , 650 (*it)->read_rb , 651 (*it)->num_reg_rb_log , 652 (*it)->num_reg_rb_phy , 653 (*it)->read_rc , 654 (*it)->num_reg_rc_log , 655 (*it)->num_reg_rc_phy , 656 (*it)->write_rd , 657 (*it)->num_reg_rd_log , 658 (*it)->num_reg_rd_phy_old , 659 (*it)->num_reg_rd_phy_new , 660 (*it)->write_re , 661 (*it)->num_reg_re_log , 662 (*it)->num_reg_re_phy_old , 663 (*it)->num_reg_re_phy_new ); 664 665 log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x (%.8x)", 666 (*it)->exception_use , 667 (*it)->exception , 668 (*it)->flags , 669 (*it)->no_sequence , 670 (*it)->address_next , 671 (*it)->address_next<<2 672 ); 673 674 x++; 675 } 676 } 713 } 714 #endif 715 716 #ifdef DEBUG_TEST 717 { 718 uint32_t x=reg_NUM_BANK_HEAD; 719 if (not _rob[x].empty()) 720 { 721 entry_t * entry = _rob [x].front(); 722 723 if (false 724 // or (entry->state == ROB_EMPTY ) 725 // or (entry->state == ROB_BRANCH_WAIT_END ) 726 // or (entry->state == ROB_BRANCH_COMPLETE ) 727 // or (entry->state == ROB_STORE_WAIT_HEAD_OK ) 728 // //or (entry->state == ROB_STORE_WAIT_HEAD_KO ) 729 // or (entry->state == ROB_STORE_HEAD_OK ) 730 // or (entry->state == ROB_STORE_HEAD_KO ) 731 // or (entry->state == ROB_OTHER_WAIT_END ) 732 // or (entry->state == ROB_MISS_WAIT_END ) 733 // or (entry->state == ROB_END_OK_SPECULATIVE ) 734 or (entry->state == ROB_END_OK ) 735 // or (entry->state == ROB_END_KO_SPECULATIVE ) 736 // or (entry->state == ROB_END_KO ) 737 // or (entry->state == ROB_END_BRANCH_MISS_SPECULATIVE) 738 or (entry->state == ROB_END_BRANCH_MISS ) 739 // or (entry->state == ROB_END_LOAD_MISS_SPECULATIVE ) 740 // or (entry->state == ROB_END_LOAD_MISS_UPDATE ) 741 or (entry->state == ROB_END_LOAD_MISS ) 742 // or (entry->state == ROB_END_MISS ) 743 // or (entry->state == ROB_END_EXCEPTION_WAIT_HEAD ) 744 // or (entry->state == ROB_END_EXCEPTION_UPDATE ) 745 // or (entry->state == ROB_END_EXCEPTION ) 746 ) 747 if (entry->address != reg_PC_CURRENT[entry->front_end_id][entry->context_id]) 748 throw ERRORMORPHEO(FUNCTION,toString(_("Rob top address (%x) is different of reg_PC_CURRENT[%d][%d] (%x).\n"), 749 entry->address, 750 entry->front_end_id, 751 entry->context_id, 752 reg_PC_CURRENT[entry->front_end_id][entry->context_id])); 753 } 754 } 755 #endif 677 756 678 757 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
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