Changeset 109 for trunk/IPs/systemC
- Timestamp:
- Feb 16, 2009, 9:28:31 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo
- Files:
-
- 1 added
- 57 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_affectation.h
r88 r109 25 25 // Constant 26 26 public : const std::string _name ; 27 public : conststd::string _value;27 public : std::string _value; 28 28 public : bool _use ; 29 29 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp
r100 r109 42 42 debug_init (fromString<debug_verbosity_t>(_simulator->getParam("debug_level")), 43 43 fromString<double> (_simulator->getParam("debug_cycle_start")), 44 fromString<double> (_simulator->getParam("debug_cycle_stop"))); 44 fromString<double> (_simulator->getParam("debug_cycle_stop")), 45 fromString<double> (_simulator->getParam("debug_cycle_idle"))); 45 46 46 47 log_init(fromString<bool>(_simulator->getParam("debug_have_log_file")), -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp
r97 r109 220 220 221 221 for (uint32_t k=0; k<MAX_OPERATION; ++k) 222 if (is_type_valid(j) and (j != TYPE_MEMORY))// A functional unit can't execute memory instruction 223 { 224 _param->_timing [i][j][k]._latence = fromString<uint32_t> (getParam("latence", 225 "functionnal_unit",toString(i).c_str(), 226 "type" ,toString(j).c_str(), 227 "operation" ,toString(k).c_str(), 228 "")); 229 _param->_timing [i][j][k]._delay = fromString<uint32_t> (getParam("delay", 230 "functionnal_unit",toString(i).c_str(), 231 "type" ,toString(j).c_str(), 232 "operation" ,toString(k).c_str(), 233 "")); 234 } 235 else 236 { 237 _param->_timing [i][j][k]._latence = 0; 238 _param->_timing [i][j][k]._delay = 0; 239 } 222 { 223 if (is_type_valid(j) and (j != TYPE_MEMORY))// A functional unit can't execute memory instruction 224 { 225 _param->_timing [i][j][k]._latence = fromString<uint32_t> (getParam("latence", 226 "functionnal_unit",toString(i).c_str(), 227 "type" ,toString(j).c_str(), 228 "operation" ,toString(k).c_str(), 229 "")); 230 _param->_timing [i][j][k]._delay = fromString<uint32_t> (getParam("delay", 231 "functionnal_unit",toString(i).c_str(), 232 "type" ,toString(j).c_str(), 233 "operation" ,toString(k).c_str(), 234 "")); 235 } 236 else 237 { 238 _param->_timing [i][j][k]._latence = 0; 239 _param->_timing [i][j][k]._delay = 0; 240 } 241 } 240 242 } 241 243 } … … 247 249 //log_printf(INFO,Configuration,FUNCTION,_("ICACHE_PORT")); 248 250 249 _param->_nb_icache_port = fromString<uint32_t>(getParam("nb_icache_port" , ""));251 _param->_nb_icache_port = fromString<uint32_t >(getParam("nb_icache_port" , "")); 250 252 _param->_icache_port_priority = fromString<Tpriority_t >(getParam("icache_port_priority" , "")); 251 253 _param->_icache_port_load_balancing = fromString<Tload_balancing_t >(getParam("icache_port_load_balancing", "")); … … 512 514 getLink_2("link_execute_unit_with_functionnal_unit",toString(i).c_str(), ""); 513 515 _param->_link_execute_unit_with_functionnal_unit [i] = pair_dual(fromString<uint32_t>(dest[0]), 514 fromString<uint32_t>(dest[1]));516 fromString<uint32_t>(dest[1])); 515 517 } 516 518 … … 519 521 getLink_2("link_execute_unit_with_load_store_unit",toString(i).c_str(), ""); 520 522 _param->_link_execute_unit_with_load_store_unit [i] = pair_dual(fromString<uint32_t>(dest[0]), 521 fromString<uint32_t>(dest[1]));523 fromString<uint32_t>(dest[1])); 522 524 523 525 for (uint32_t j=0; j<_param->_nb_cache_port[i]; ++j) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromXMLLight.cpp
r88 r109 26 26 27 27 XMLLightVector<XML_t> vect = xml->getNodes(); 28 28 29 29 for (uint32_t i=0; i<vect.size(); ++i) 30 30 { … … 33 33 std::string child_name = child->getName(); 34 34 35 // log_printf(TRACE,Configuration,FUNCTION," * child_name : %s",child_name.c_str()); 36 35 37 //-------------------------------------------- 36 38 // Child : Parameter … … 44 46 attribute_t value_name = getAttribute(child,attributes,"name" ); 45 47 attribute_t value = getAttribute(child,attributes,"value"); 48 49 // log_printf(TRACE,Configuration,FUNCTION," * parameter \"%s\" = %s",value_name.c_str(), value.c_str()); 46 50 47 51 testAttributesEmpty(child,attributes); … … 70 74 attributes_t attributes = child->getAttributes(); 71 75 attribute_t value_name = getAttribute(child,attributes,"name"); 76 77 // log_printf(TRACE,Configuration,FUNCTION," * link \"%s\"",value_name.c_str()); 72 78 73 79 // Test, must have src or dest (or twice) … … 80 86 attribute_t value_src = (have_src )?getAttribute(child,attributes,"src" ):id; 81 87 attribute_t value_dest = (have_dest)?getAttribute(child,attributes,"dest"):id; 88 82 89 83 90 testAttributesEmpty(child,attributes); … … 111 118 if (child_name == "timing") 112 119 { 120 // log_printf(TRACE,Configuration,FUNCTION," * timing"); 121 113 122 // Notation : 114 123 // <timing type="5" operation="8" latence="2" delay="1" /> … … 183 192 } 184 193 //-------------------------------------------- 185 // Child : Other ( node)194 // Child : Other (component) 186 195 //-------------------------------------------- 187 196 else 188 197 { 198 // log_printf(TRACE,Configuration,FUNCTION," * component"); 199 189 200 testSingleton (child,false); 190 201 191 202 attributes_t attributes = child->getAttributes(); 192 attribute_t value_id 203 attribute_t value_ids = getAttribute(child,attributes,"id"); 193 204 attribute_t value_type = child->getName(); 194 195 testAttributesEmpty(child,attributes); 196 197 // Create a new component 205 206 testAttributesEmpty(child,attributes); 207 208 // Test if counter is an parameters 209 std::string name_counter = "nb_"+value_type; 210 198 211 { 199 Instance_component * param = new Instance_component(value_type, // type200 value_id);201 202 // log_printf(TRACE,Configuration,FUNCTION,"%s.%s",value_type.c_str(),value_id.c_str());203 // log_printf(TRACE,Configuration,FUNCTION," * %d",((*list_components)[value_type]).size());204 205 // Test if this id is previously used206 if (((*list_components)[value_type]).find(value_id) != ((*list_components)[value_type]).end())207 throw ERRORMORPHEO(FUNCTION,toString(_("A Component \"%s\" with id \"%s\" is previously declared.\n"),value_type.c_str(),value_id.c_str()));208 209 ((*list_components)[value_type])[value_id] = param;210 }211 212 // Test if counter is an parameters213 {214 std::string name_counter = "nb_"+value_type;215 // std::cout << name_counter << std::endl;216 217 212 if (list_parameters->find(name_counter) == list_parameters->end()) 218 213 { 219 // Scearch all occurante of this type220 uint32_t nb_counter = xml->getNodes(value_type).size();221 // std::cout << " * " << nb_counter << std::endl;222 223 214 // Insert in array 224 215 Parameter_affectation * param = new Parameter_affectation(name_counter, // type 225 toString(nb_counter)); 226 216 "0"); 227 217 // insert parameter 228 218 (*list_parameters)[name_counter] = param; … … 230 220 } 231 221 232 // Recursive function 233 fromXMLLight (child, 234 ((id=="")?value_id:(id+"."+value_id)), // construction of identificator 235 ((*list_components)[value_type])[value_id]->_list_parameters, 236 // ((*list_components)[value_type])[value_id]->_list_links, 237 list_links, 238 ((*list_components)[value_type])[value_id]->_list_components); 222 size_t index_begin = 0; 223 while (index_begin != std::string::npos) 224 { 225 size_t index_end = value_ids.find_first_of(",",index_begin+1); 226 227 size_t index_min = (index_begin==0)?index_begin:(index_begin+1); 228 size_t index_max = index_end-index_min; 229 attribute_t value_id = value_ids.substr(index_min, index_max); 230 231 // log_printf(TRACE,Configuration,FUNCTION," * component \"%s\" - %s",value_type.c_str(), value_id.c_str()); 232 233 index_begin = index_end; 234 235 // Create a new component 236 { 237 Instance_component * param = new Instance_component(value_type, // type 238 value_id); 239 240 // log_printf(TRACE,Configuration,FUNCTION,"%s.%s",value_type.c_str(),value_id.c_str()); 241 // log_printf(TRACE,Configuration,FUNCTION," * %d",((*list_components)[value_type]).size()); 242 243 // Test if this id is previously used 244 if (((*list_components)[value_type]).find(value_id) != ((*list_components)[value_type]).end()) 245 throw ERRORMORPHEO(FUNCTION,toString(_("A Component \"%s\" with id \"%s\" is previously declared.\n"),value_type.c_str(),value_id.c_str())); 246 247 ((*list_components)[value_type])[value_id] = param; 248 } 249 250 // Increase occurence counter 251 { 252 (*list_parameters)[name_counter]->_value = toString(fromString<uint32_t>((*list_parameters)[name_counter]->_value)+1); 253 } 254 255 // Recursive function 256 fromXMLLight (child, 257 ((id=="")?value_id:(id+"."+value_id)), // construction of identificator 258 ((*list_components)[value_type])[value_id]->_list_parameters, 259 // ((*list_components)[value_type])[value_id]->_list_links, 260 list_links, 261 ((*list_components)[value_type])[value_id]->_list_components); 262 } 239 263 } 240 264 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation.cpp
r88 r109 17 17 Parameter_affectation::Parameter_affectation (std::string name , 18 18 std::string value ): 19 _name (name ), 20 _value (value ) 19 _name (name ) 21 20 { 22 21 log_begin(Configuration,FUNCTION); 23 22 24 _use = false; 23 _value = value; 24 _use = false; 25 25 26 26 log_end(Configuration,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp
r88 r109 29 29 for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert[i][j]; ++k) 30 30 { 31 PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_VAL [num_ooo_engine][k])); 32 PORT_WRITE(out_INSERT_OOO_ENGINE_ACK [i][j] ,PORT_READ(in_INSERT_EXECUTE_LOOP_ACK [i][j][k])); 31 log_printf(TRACE,Core_Glue,FUNCTION," * INSERT_OOO_ENGINE [%d][%d] <-> INSERT_EXECUTE_LOOP [%d][%d][%d]",num_ooo_engine,k,i,j,k); 32 33 Tcontrol_t ooo_engine_val = PORT_READ(in_INSERT_OOO_ENGINE_VAL [num_ooo_engine][k]); 34 Tcontrol_t execute_loop_ack = PORT_READ(in_INSERT_EXECUTE_LOOP_ACK [i][j][k]); 35 36 Tcontrol_t execute_loop_val = ooo_engine_val ; 37 Tcontrol_t ooo_engine_ack = execute_loop_ack; 38 39 log_printf(TRACE,Core_Glue,FUNCTION," * ooo_engine_val (r) : %d",ooo_engine_val ); 40 log_printf(TRACE,Core_Glue,FUNCTION," * ooo_engine_ack (w) : %d",ooo_engine_ack ); 41 log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop_val (w) : %d",execute_loop_val); 42 log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop_ack (r) : %d",execute_loop_ack); 43 44 PORT_WRITE(out_INSERT_OOO_ENGINE_ACK [num_ooo_engine][k],ooo_engine_ack ); 45 PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],execute_loop_val); 33 46 PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_USE [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_USE [num_ooo_engine][k])); 34 47 PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_NUM_REG [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_NUM_REG [num_ooo_engine][k])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp
r88 r109 56 56 _table_execute_type = table_execute_type ; 57 57 _table_execute_thread = table_execute_thread; 58 59 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_routing [nb_read_unit][nb_execute_unit][nb_execute_unit_port]"); 60 for (uint32_t i=0; i<_nb_read_unit; ++i) 61 for (uint32_t j=0; j<_nb_execute_unit; ++j) 62 for (uint32_t k=0; k<_nb_execute_unit_port[j]; ++k) 63 if (_table_routing [i][j][k]) 64 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d][%d] -> true",i,j,k); 65 66 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_execute_type [nb_execute_unit][nb_type]"); 67 for (uint32_t i=0; i<_nb_execute_unit; ++i) 68 for (uint32_t j=0; j<_nb_type; ++j) 69 if (_table_execute_type [i][j]) 70 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d] -> true",i,j); 71 72 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_execute_thread [nb_execute_unit][nb_thread]"); 73 for (uint32_t i=0; i<_nb_execute_unit; ++i) 74 for (uint32_t j=0; j<_nb_thread; ++j) 75 if (_table_execute_thread [i][j]) 76 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d] -> true",i,j); 58 77 59 78 _max_nb_read_unit_port = max<uint32_t>(_nb_read_unit_port, _nb_read_unit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp
r97 r109 42 42 // TYPE_MEMORY | | | X | 43 43 44 bool type_valid [_nb_type];45 bool type_uniq [_nb_type]; // one thread can have multiple destination for this type ?46 bool type_optionnal [_nb_type]; // this type is optionnal ?47 bool type_exclusive [_nb_type]; // a unit that implement this type must be implement an another type ?48 49 for (Ttype_t i=0; i<_nb_type; i++)50 {51 type_valid [i] = false;52 type_uniq [i] = false;53 type_optionnal [i] = false;54 type_exclusive [i] = false;55 }56 57 type_valid [TYPE_ALU ] = true;58 type_valid [TYPE_SHIFT ] = true;59 type_valid [TYPE_MOVE ] = true;60 type_valid [TYPE_TEST ] = true;61 type_valid [TYPE_MUL ] = true;62 type_valid [TYPE_DIV ] = true;63 type_valid [TYPE_EXTEND ] = true;64 type_valid [TYPE_FIND ] = true;65 type_valid [TYPE_SPECIAL] = true;66 type_valid [TYPE_CUSTOM ] = true;67 type_valid [TYPE_BRANCH ] = true;68 type_valid [TYPE_MEMORY ] = true;69 70 type_uniq [TYPE_SPECIAL] = true;71 type_uniq [TYPE_CUSTOM ] = true;72 type_uniq [TYPE_MEMORY ] = true;73 74 type_optionnal [TYPE_DIV ] = true;75 type_optionnal [TYPE_EXTEND ] = true;76 type_optionnal [TYPE_FIND ] = true;77 type_optionnal [TYPE_CUSTOM ] = true;78 79 type_exclusive [TYPE_MEMORY ] = true;80 81 44 bool type_present [_nb_thread][_nb_type]; 82 45 for (uint32_t i=0; i<_nb_thread; i++) … … 94 57 95 58 // Test uniq type 96 if (type_present [j][k] and type_uniq[k])59 if (type_present [j][k] and is_type_uniq(k)) 97 60 test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString(k).c_str(),j)); 98 61 … … 101 64 102 65 for (Ttype_t j=0; j<_nb_type; j++) 103 if (not type_valid [j])66 if (not is_type_valid(j)) 104 67 for (uint32_t i=0; i<_nb_thread; i++) 105 68 if (type_present [i][j]) … … 107 70 108 71 for (Ttype_t j=0; j<_nb_type; j++) 109 if ( type_valid [j] and not type_optionnal[j])72 if (is_type_valid(j) and not is_type_optionnal(j)) 110 73 for (uint32_t i=0; i<_nb_thread; i++) 111 74 if (not type_present [i][j]) … … 115 78 for (uint32_t i=0; i<_nb_execute_unit; i++) 116 79 for (Ttype_t j=0; j<_nb_type; j++) 117 if ( type_exclusive [j]and _table_execute_type[i][j])80 if (is_type_exclusive(j) and _table_execute_type[i][j]) 118 81 for (Ttype_t k=0; k<_nb_type; k++) 119 82 if ((j != k) and (_table_execute_type[i][k] == true)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
r97 r109 156 156 if (timing[x][j][k]._latence > 0) 157 157 { 158 log_printf(TRACE,Execute_loop,FUNCTION," Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str());158 log_printf(TRACE,Execute_loop,FUNCTION," * Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str()); 159 159 _read_unit_to_execution_unit_table_execute_type [i][j] = true; 160 160 break; // find an operation 161 161 } 162 162 } 163 164 for (uint32_t i=0; i<_nb_load_store_unit; ++i) 165 log_printf(TRACE,Execute_loop,FUNCTION," * Load_store_unit [%d] - nb_inst : %d",i,_nb_inst_memory [i]); 166 for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 167 log_printf(TRACE,Execute_loop,FUNCTION," * Functionnal_unit [%d] - nb_inst : %d",i,_nb_inst_functionnal_unit [i]); 168 163 169 164 170 for (uint32_t i=0; i<_nb_execute_unit; i++) … … 170 176 else 171 177 _nb_execute_unit_port [i] = _nb_inst_functionnal_unit [x]; 178 179 log_printf(TRACE,Execute_loop,FUNCTION," * Execute unit [%d] (%d) - nb_inst : %d",i,x,_nb_execute_unit_port [i]); 172 180 } 173 181 … … 245 253 for (uint32_t k=0; k<_nb_write_unit; k++) 246 254 { 255 log_printf(TRACE,Execute_loop,FUNCTION," * Execution_unit_to_write_unit_table_routing [%d][%d][%d]",x,y,k); 256 247 257 // Test if this execute_unit can send operation at this write_unit 248 258 // Test if have not a previous link ! (a same read_unit can send operation à two execute_unit and each execute_unit send at the same write_unit) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Parameters.h
r88 r109 24 24 { 25 25 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _nb_context ; 27 public : uint32_t _nb_inst_decod ; 28 public : uint32_t _size_queue ; 29 //public : uint32_t _size_general_data ; 30 public : uint32_t * _nb_branch_speculated ; //[nb_context] 31 32 public : uint32_t _nb_bank ; 33 public : uint32_t _size_bank ; 26 public : uint32_t _nb_context ; 27 public : uint32_t _nb_inst_decod ; 28 public : uint32_t _size_queue ; 29 //public : uint32_t _size_general_data ; 30 public : uint32_t * _nb_branch_speculated ; //[nb_context] 31 public : uint32_t _nb_instruction_in_queue; 34 32 35 33 //-----[ methods ]----------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp
r108 r109 29 29 //-------------------------------------------------------------------- 30 30 { 31 Tcontrol_t ack = reg_QUEUE->size() < _param->_size_ bank;31 Tcontrol_t ack = reg_QUEUE->size() < _param->_size_queue; 32 32 33 33 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
r108 r109 145 145 it++) 146 146 { 147 log_printf(TRACE,Decod_queue,FUNCTION," * [%d] ",x);148 149 147 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 150 148 { 151 149 if ((*it)->_val [i]) 152 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d] %.1d, %.3d %.2d, %.2d %.3d %.1d %.1d, 0x%.8x (0x%.8x), %.1d 0x%.8x, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d" 153 ,i 150 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d][%.4d] %.1d, %.3d %.2d, %.2d %.3d %.1d %.1d, 0x%.8x (0x%.8x), %.1d 0x%.8x, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d" 151 ,x 152 ,i 154 153 ,(*it)->_val [i] 155 154 ,(*it)->_context_id [i] … … 177 176 ); 178 177 else 179 log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d" 180 ,i 178 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d][%.4d] %d" 179 ,x 180 ,i 181 181 ,(*it)->_val [i] 182 182 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp
r95 r109 29 29 log_begin(Decod_queue,FUNCTION); 30 30 31 _nb_context = nb_context ; 32 _nb_inst_decod = nb_inst_decod ; 33 _size_queue = size_queue ; 34 // _size_general_data = size_general_data ; 35 _nb_branch_speculated = nb_branch_speculated; 36 37 _nb_bank = _nb_inst_decod ; 38 _size_bank = _size_queue / _nb_bank; 31 _nb_context = nb_context ; 32 _nb_inst_decod = nb_inst_decod ; 33 _size_queue = size_queue/nb_inst_decod; 34 // _size_general_data = size_general_data ; 35 _nb_branch_speculated = nb_branch_speculated; 36 _nb_instruction_in_queue = size_queue; 39 37 40 38 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters_msg_error.cpp
r82 r109 27 27 Parameters_test test ("Decod_queue"); 28 28 29 if (not is_multiple (_size_queue,_nb_inst_decod))30 test.error( _("size_queue must be a multiple of nb_inst_decod.\n"));29 if (not is_multiple (_nb_instruction_in_queue,_nb_inst_decod)) 30 test.error("Size of decod queue must be a multiple of nb_instruction.\n"); 31 31 32 32 log_end(Decod_queue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration.cfg
r81 r109 1 1 Ifetch_queue 2 1 8*2 # _size_queue2 8 16 *2 # _size_queue 3 3 1 8 *2 # _nb_instruction 4 4 1 1 *2 # _size_branch_update_prediction -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h
r88 r109 28 28 //public : uint32_t _size_branch_update_prediction ; 29 29 //public : uint32_t _size_general_data ; 30 public : uint32_t _nb_instruction_in_queue ; 30 31 31 32 //public : uint32_t _size_queue_ptr ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp
r88 r109 27 27 log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); 28 28 29 _size_queue = size_queue ; 29 _nb_instruction_in_queue = size_queue ; 30 _size_queue = size_queue/nb_instruction ; 30 31 _nb_instruction = nb_instruction ; 31 32 // _size_branch_update_prediction = size_branch_update_prediction; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp
r88 r109 27 27 Parameters_test test ("Ifetch_queue"); 28 28 29 if (not is_multiple (_nb_instruction_in_queue,_nb_instruction)) 30 test.error("Size of ifetch queue must be a multiple of nb_instruction.\n"); 31 29 32 if (_size_queue == 1) 30 33 test.warning("To best perfomance, size_queue must be > 1.\n"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r106 r109 18 18 namespace prediction_unit { 19 19 namespace update_prediction_table { 20 21 typedef enum 22 { 23 EVENT_SOURCE_UFPT, 24 EVENT_SOURCE_UPT 25 } event_source_t; 20 26 21 27 typedef enum … … 115 121 }; // end namespace core 116 122 }; // end namespace behavioural 123 124 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_source_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_source_t& x) 125 { 126 switch (x) 127 { 128 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_SOURCE_UFPT : return "ufpt"; break; 129 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_SOURCE_UPT : return "upt" ; break; 130 default : return ""; break; 131 } 132 }; 133 134 117 135 118 136 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t& x) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r106 r109 183 183 184 184 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 185 private : event_source_t * reg_EVENT_SOURCE ; //[nb_context] 185 186 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] 186 187 private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r106 r109 209 209 ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); 210 210 211 ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); 212 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 213 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 214 ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); 215 ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); 211 ALLOC1(reg_EVENT_STATE ,event_state_t ,_param->_nb_context); 212 ALLOC1(reg_EVENT_SOURCE ,event_source_t,_param->_nb_context); 213 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 214 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 215 ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); 216 ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); 216 217 } 217 218 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r106 r109 163 163 164 164 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 165 DELETE1(reg_EVENT_SOURCE ,_param->_nb_context); 165 166 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); 166 167 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r108 r109 234 234 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; 235 235 } 236 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT; 236 237 237 238 // Flush UPFT … … 506 507 507 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 511 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 511 512 512 513 if (miss) … … 517 518 518 519 // Flush UPT 519 uint32_t top = reg_UPT_TOP [context]; 520 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 521 522 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 524 525 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 526 j!=top; 527 j=(j+1)%_param->_size_upt_queue[context]) 528 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 520 uint32_t top = reg_UPT_TOP [context]; 521 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 522 523 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 524 event_state_t event_state = reg_EVENT_STATE [context]; 525 bool previous_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 526 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 527 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 528 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or 529 ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and 530 (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT))); 531 // bool update_ras = (new_update != depth); 532 533 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 534 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 535 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_event : %d",previous_event); 537 538 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) 539 { 540 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 541 j!=top; 542 j=(j+1)%_param->_size_upt_queue[context]) 543 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 544 529 545 530 531 // reg_UPT_BOTTOM [context]; 532 reg_UPT_TOP [context] = depth; 533 reg_UPT_TOP_EVENT [context] = top; 534 535 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 536 reg_UPT_EMPTY [context] = true; 537 546 // reg_UPT_BOTTOM [context]; 547 reg_UPT_TOP [context] = depth; 548 // reg_UPT_TOP_EVENT [context] = top; 549 550 if (not previous_event) 551 { 552 reg_UPT_TOP_EVENT [context] = top; 553 reg_UPT_UPDATE [context] = new_update; 554 } 555 else 556 { 557 // Have event. Top index this slot 558 559 switch (reg_UPDATE_PREDICTION_TABLE [context][top]._state) 560 { 561 case UPDATE_PREDICTION_STATE_END_KO : 562 { 563 // Have already update predictor 564 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END; 565 break; 566 } 567 case UPDATE_PREDICTION_STATE_KO : 568 { 569 // Doesn't have update predictor 570 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT; 571 break; 572 } 573 default : 574 { 538 575 #ifdef DEBUG_TEST 539 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 540 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 541 #endif 542 543 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 544 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 545 546 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 547 event_state_t event_state = reg_EVENT_STATE [context]; 548 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 550 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 551 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 552 // bool update_ras = (new_update != depth); 553 554 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 555 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); 556 557 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 558 { 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 560 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 576 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 577 #endif 578 } 579 } 580 } 581 582 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 583 reg_UPT_EMPTY [context] = true; 584 585 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 586 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 587 588 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 589 { 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 591 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 592 } 593 else 594 { 595 // if (not previous_update_ras) 596 { 597 // have ras prediction ? 598 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 599 600 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 601 602 } 603 } 604 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; 605 606 // else no update 607 608 reg_EVENT_DEPTH [context] = depth; 609 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 610 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 611 reg_EVENT_ADDRESS_DEST [context] = good_addr; 561 612 } 562 else 563 { 564 // if (not previous_update_ras) 565 { 566 // have ras prediction ? 567 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 568 569 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 570 571 } 572 } 573 574 if (not previous_update_ras) 575 { 576 reg_UPT_UPDATE [context] = new_update; 577 } 578 // else no update 579 580 reg_EVENT_DEPTH [context] = depth; 581 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 582 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 583 reg_EVENT_ADDRESS_DEST [context] = good_addr; 584 } 613 } 585 614 else 586 615 { … … 901 930 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 902 931 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 932 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str()); 903 933 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 904 934 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r108 r109 222 222 223 223 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 224 private : double ** _nb_cycle_idle; 225 224 226 private : std::list<entry_t*> * _rob ;//[nb_bank] 225 227 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r108 r109 279 279 280 280 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 281 ALLOC2(_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]); 281 282 ALLOC1(_rob ,std::list<entry_t*>,_param->_nb_bank); 282 283 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r108 r109 187 187 188 188 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 189 DELETE2(_nb_cycle_idle ,_param->_nb_front_end,_param->_nb_context [it1]); 189 190 DELETE1(_rob ,_param->_nb_bank); 190 191 DELETE1(reg_BANK_PTR ,_param->_nb_bank); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
r100 r109 58 58 _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); 59 59 60 _stat->create_expr ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle"); 61 _stat->create_expr ("CPI", "/ 1 IPC" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction"); 60 _stat->create_expr ("IPC_ok" , "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok)"); 61 _stat->create_expr ("CPI_ok" , "/ 1 IPC_ok" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok)"); 62 63 _stat->create_expr ("IPC_ko" , "average_inst_retire_ko", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ko)"); 64 _stat->create_expr ("CPI_ko" , "/ 1 IPC_ko" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ko)"); 65 66 _stat->create_expr ("IPC_all", "average_inst_retire" , TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok and Ko)"); 67 _stat->create_expr ("CPI_all", "/ 1 IPC_all" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok and Ko)"); 62 68 } 63 69 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r108 r109 41 41 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 42 42 { 43 _nb_cycle_idle [i][j] = 0; 44 43 45 reg_NB_INST_COMMIT_ALL [i][j] = 0; 44 46 reg_NB_INST_COMMIT_MEM [i][j] = 0; … … 59 61 else 60 62 { 63 // Increase number idle cycle 64 for (uint32_t i=0; i<_param->_nb_front_end; i++) 65 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 66 _nb_cycle_idle [i][j] ++; 67 61 68 // Compute next priority 62 69 _priority_insert->transition(); … … 402 409 _rob [i].pop_front(); 403 410 delete entry; 411 412 // Transaction on retire interface : reset watch dog timer. 413 _nb_cycle_idle [front_end_id][context_id] = 0; 404 414 } 405 415 … … 759 769 #endif 760 770 771 // Stop Condition 772 for (uint32_t i=0; i<_param->_nb_front_end; i++) 773 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 774 if (_nb_cycle_idle [i][j] >= debug_cycle_idle) 775 throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] is idle since %.0f cycles.\n"),i,j,_nb_cycle_idle [i][j])); 776 761 777 log_end(Commit_unit,FUNCTION); 762 778 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
r88 r109 45 45 if (internal_BANK_IN_ACK [i]) 46 46 { 47 entry_t * entry = NULL;47 entry_t * entry = NULL; 48 48 49 49 if (internal_BANK_IN_IS_REEXECUTE [i]) … … 53 53 if (PORT_READ(in_REEXECUTE_VAL [y])) 54 54 { 55 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with REEXECUTE [%d]",i,y); 55 56 #ifdef STATISTICS 56 57 if (usage_is_set(_usage,USE_STATISTICS)) … … 62 63 (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [y]):0, 63 64 (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [y]):0, 64 PORT_READ(in_REEXECUTE_OPERATION [y]),65 PORT_READ(in_REEXECUTE_TYPE [y]),66 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]),65 PORT_READ(in_REEXECUTE_OPERATION [y]), 66 PORT_READ(in_REEXECUTE_TYPE [y]), 67 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]), 67 68 (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [y]):0, 68 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]),69 PORT_READ(in_REEXECUTE_IMMEDIAT [y]),70 PORT_READ(in_REEXECUTE_READ_RA [y]),71 PORT_READ(in_REEXECUTE_NUM_REG_RA [y]),72 PORT_READ(in_REEXECUTE_READ_RB [y]),73 PORT_READ(in_REEXECUTE_NUM_REG_RB [y]),74 PORT_READ(in_REEXECUTE_READ_RC [y]),75 PORT_READ(in_REEXECUTE_NUM_REG_RC [y]),76 PORT_READ(in_REEXECUTE_WRITE_RD [y]),77 PORT_READ(in_REEXECUTE_NUM_REG_RD [y]),78 PORT_READ(in_REEXECUTE_WRITE_RE [y]),79 PORT_READ(in_REEXECUTE_NUM_REG_RE [y])69 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]), 70 PORT_READ(in_REEXECUTE_IMMEDIAT [y]), 71 PORT_READ(in_REEXECUTE_READ_RA [y]), 72 PORT_READ(in_REEXECUTE_NUM_REG_RA [y]), 73 PORT_READ(in_REEXECUTE_READ_RB [y]), 74 PORT_READ(in_REEXECUTE_NUM_REG_RB [y]), 75 PORT_READ(in_REEXECUTE_READ_RC [y]), 76 PORT_READ(in_REEXECUTE_NUM_REG_RC [y]), 77 PORT_READ(in_REEXECUTE_WRITE_RD [y]), 78 PORT_READ(in_REEXECUTE_NUM_REG_RD [y]), 79 PORT_READ(in_REEXECUTE_WRITE_RE [y]), 80 PORT_READ(in_REEXECUTE_NUM_REG_RE [y]) 80 81 ); 81 82 } … … 88 89 if (PORT_READ(in_ISSUE_IN_VAL[x][y])) 89 90 { 91 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with ISSUE_IN [%d][%d]",i,x,y); 92 90 93 #ifdef STATISTICS 91 94 if (usage_is_set(_usage,USE_STATISTICS)) … … 97 100 (_param->_have_port_front_end_id )?PORT_READ(in_ISSUE_IN_FRONT_END_ID [x][y]):0, 98 101 (_param->_have_port_rob_ptr )?PORT_READ(in_ISSUE_IN_PACKET_ID [x][y]):0, 99 PORT_READ(in_ISSUE_IN_OPERATION [x][y]),100 PORT_READ(in_ISSUE_IN_TYPE [x][y]),101 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]),102 PORT_READ(in_ISSUE_IN_OPERATION [x][y]), 103 PORT_READ(in_ISSUE_IN_TYPE [x][y]), 104 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]), 102 105 (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE [x][y]):0, 103 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]),104 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]),105 PORT_READ(in_ISSUE_IN_READ_RA [x][y]),106 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]),107 PORT_READ(in_ISSUE_IN_READ_RB [x][y]),108 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]),109 PORT_READ(in_ISSUE_IN_READ_RC [x][y]),110 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]),111 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]),112 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]),113 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]),114 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y])106 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]), 107 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]), 108 PORT_READ(in_ISSUE_IN_READ_RA [x][y]), 109 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]), 110 PORT_READ(in_ISSUE_IN_READ_RB [x][y]), 111 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]), 112 PORT_READ(in_ISSUE_IN_READ_RC [x][y]), 113 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]), 114 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]), 115 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]), 116 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]), 117 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y]) 115 118 ); 116 119 } … … 140 143 if (PORT_READ(in_ISSUE_OUT_ACK [x])) 141 144 { 145 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - Transaction with ISSUE_OUT [%d]",i,x); 146 147 142 148 entry_t * entry = _issue_queue [i].front(); 143 149 _issue_queue [i].pop_front(); … … 148 154 } 149 155 150 log_printf(TRACE,Issue_queue,FUNCTION," * InfoIssue_queue");156 log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); 151 157 for (uint32_t i=0; i<_param->_nb_bank; i++) 152 158 { … … 155 161 *(_stat_bank_nb_inst [i]) += _issue_queue[i].size(); 156 162 #endif 157 log_printf(TRACE,Issue_queue,FUNCTION," * [%d] size : %d",i,(int)_issue_queue[i].size()); 163 log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d] size : %d",i,(int)_issue_queue[i].size()); 164 165 uint32_t j = 0; 166 for (std::list<entry_t*>::iterator it=_issue_queue[i].begin();it!=_issue_queue[i].end(); ++it) 167 { 168 log_printf(TRACE,Issue_queue,FUNCTION," [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d", 169 j, 170 171 (*it)->_context_id , 172 (*it)->_front_end_id , 173 (*it)->_packet_id , 174 175 (*it)->_type , 176 (*it)->_operation , 177 178 (*it)->_store_queue_ptr_write, 179 (*it)->_load_queue_ptr_write , 180 181 (*it)->_has_immediat , 182 (*it)->_immediat , 183 184 (*it)->_read_ra , 185 (*it)->_num_reg_ra , 186 187 (*it)->_read_rb , 188 (*it)->_num_reg_rb , 189 190 (*it)->_read_rc , 191 (*it)->_num_reg_rc , 192 193 (*it)->_write_rd , 194 (*it)->_num_reg_rd , 195 196 (*it)->_write_re , 197 (*it)->_num_reg_re ); 198 199 ++j; 200 } 201 158 202 } 159 203 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp
r88 r109 57 57 _table_issue_type = table_issue_type ; 58 58 59 log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 60 for (uint32_t i=0; i<_nb_rename_unit; ++i) 61 for (uint32_t j=0; j<_nb_inst_issue; ++j) 62 if (_table_routing [i][j]) 63 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 64 65 log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]"); 66 for (uint32_t i=0; i<_nb_inst_issue; ++i) 67 for (uint32_t j=0; j<_nb_type; ++j) 68 if (_table_issue_type [i][j]) 69 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 70 59 71 _max_nb_inst_rename = max<uint32_t>(_nb_inst_rename,_nb_rename_unit); 60 72 _nb_bank_select_out = _nb_bank/nb_inst_issue; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r108 r109 38 38 test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); 39 39 40 bool type_valid [_nb_type];41 42 for (uint32_t i=0; i<_nb_type; i++)43 type_valid [i] = false;44 45 type_valid [TYPE_ALU ] = true;46 type_valid [TYPE_SHIFT ] = true;47 type_valid [TYPE_MOVE ] = true;48 type_valid [TYPE_TEST ] = true;49 type_valid [TYPE_MUL ] = true;50 type_valid [TYPE_DIV ] = true;51 type_valid [TYPE_EXTEND ] = true;52 type_valid [TYPE_FIND ] = true;53 type_valid [TYPE_SPECIAL] = true;54 type_valid [TYPE_CUSTOM ] = true;55 type_valid [TYPE_BRANCH ] = true;56 type_valid [TYPE_MEMORY ] = true;57 58 40 for (uint32_t i=0; i<_nb_rename_unit; i++) 59 41 { … … 61 43 62 44 for (uint32_t j=0; j<_nb_type; j++) 63 type_present [j] = not type_valid [j];45 type_present [j] = not is_type_valid(j); 64 46 65 47 bool find = false; … … 77 59 else 78 60 for (uint32_t j=0; j<_nb_type; j++) 79 if (not type_present [j] )61 if (not type_present [j] and not is_type_optionnal(j)) 80 62 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); 81 63 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp
r88 r109 27 27 for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) 28 28 { 29 // Transaction must be in-order 30 // Tcontrol_t previous_transaction = true; 29 // Transaction must be in-order : make in Rename_unit 31 30 32 31 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) … … 38 37 Tcontrol_t issue_queue_ack = PORT_READ(in_INSERT_ISSUE_QUEUE_ACK [i][j]); 39 38 40 41 42 39 // if not execute -> don't route to issue_queue 43 40 44 41 Tcontrol_t val = ( 45 // previous_transaction and46 42 rename_unit_val and 47 43 commit_unit_ack and … … 49 45 issue_queue_ack)); 50 46 Tcontrol_t rename_unit_ack = ( 51 // previous_transaction and52 47 ack and 53 48 commit_unit_ack and … … 55 50 issue_queue_ack)); 56 51 Tcontrol_t commit_unit_val = ( 57 // previous_transaction and58 52 ack and 59 53 rename_unit_val and … … 61 55 issue_queue_ack)); 62 56 Tcontrol_t issue_queue_val = ( 63 // previous_transaction and64 57 ack and 65 58 rename_unit_val and … … 73 66 74 67 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * rename_unit [%d].inst_insert[%d] -> %d",i,j,x); 75 // log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * previous_transaction : %d",previous_transaction ); 76 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_val (w) : %d",val ); 77 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_ack (r) : %d",ack ); 68 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_val (RegisterFile) (w) : %d",val ); 69 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_ack (RegisterFile) (r) : %d",ack ); 78 70 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_val (r) : %d",rename_unit_val ); 79 71 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_ack (w) : %d",rename_unit_ack ); … … 84 76 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_issue_queue_ack (r) : %d",issue_queue_ack ); 85 77 86 87 // previous_transaction = VAL and ACK;88 78 x ++; 89 79 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp
r88 r109 53 53 _size_rename_id = log2(_nb_rename_unit) ; 54 54 _sum_inst_insert = 0; 55 // 55 // _sum_inst_retire = 0; 56 56 57 57 for (uint32_t i=0; i<_nb_rename_unit; ++i) 58 58 { 59 59 _sum_inst_insert += _nb_inst_insert[i]; 60 // 60 // _sum_inst_retire += _nb_inst_retire[i]; 61 61 } 62 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/Makefile.deps
r81 r109 14 14 endif 15 15 16 ifndef Priority 17 include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps 18 endif 19 16 20 #-----[ Directory ]---------------------------------------- 17 21 18 Free_List_unit_DIR 22 Free_List_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit 19 23 20 24 #-----[ Library ]------------------------------------------ 21 25 22 Free_List_unit_LIBRARY = -lFree_List_unit \ 26 Free_List_unit_LIBRARY = -lFree_List_unit \ 27 $(Priority_LIBRARY) \ 23 28 $(Behavioural_LIBRARY) 24 29 25 Free_List_unit_DIR_LIBRARY = -L$(Free_List_unit_DIR)/lib \ 30 Free_List_unit_DIR_LIBRARY = -L$(Free_List_unit_DIR)/lib \ 31 $(Priority_DIR_LIBRARY) \ 26 32 $(Behavioural_DIR_LIBRARY) 27 33 … … 31 37 @\ 32 38 $(MAKE) Behavioural_library; \ 39 $(MAKE) Priority_library; \ 33 40 $(MAKE) --directory=$(Free_List_unit_DIR) --makefile=Makefile; 34 41 … … 36 43 @\ 37 44 $(MAKE) Behavioural_library_clean; \ 45 $(MAKE) Priority_library_clean; \ 38 46 $(MAKE) --directory=$(Free_List_unit_DIR) --makefile=Makefile clean; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/test.cpp
r88 r109 7 7 */ 8 8 9 #define NB_ITERATION 1 9 #define NB_ITERATION 16 10 10 #define CYCLE_MAX (128*NB_ITERATION) 11 11 … … 190 190 TEST(bool, gpr_free[reg],true); 191 191 192 Tgeneral_address_t bank = reg >> _param->_bank_gpr_size_slot;193 TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true);192 // Tgeneral_address_t bank = reg >> _param->_bank_gpr_size_slot; 193 // TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true); 194 194 195 195 gpr_free[reg] = false; … … 202 202 TEST(bool,spr_free[reg],true); 203 203 204 Tspecial_address_t bank = reg >> _param->_bank_spr_size_slot;205 TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true);204 // Tspecial_address_t bank = reg >> _param->_bank_spr_size_slot; 205 // TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true); 206 206 207 207 spr_free[reg] = false; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h
r108 r109 28 28 #endif 29 29 #include "Behavioural/include/Usage.h" 30 31 #include "Behavioural/Generic/Priority/include/Priority.h" 30 32 31 33 namespace morpheo { … … 83 85 84 86 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 private : generic::priority::Priority * _priority_gpr; 88 private : generic::priority::Priority * _priority_spr; 85 89 86 90 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 89 93 90 94 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 private : uint32_t reg_BANK_PRIORITY;92 93 95 private : Tcontrol_t * internal_POP_ACK ; //[nb_pop] 94 96 private : uint32_t * internal_POP_GPR_BANK ; //[nb_pop] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Parameters.h
r88 r109 37 37 //public : uint32_t _size_special_register; 38 38 39 public : uint32_t _nb_bank_by_pop ;39 // public : uint32_t _nb_bank_by_pop ; 40 40 public : uint32_t _bank_gpr_nb_slot ; 41 41 public : uint32_t _bank_gpr_size_slot ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp
r88 r109 101 101 } 102 102 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 _priority_gpr = new generic::priority::Priority (_name+"_priority_gpr", 104 _param->_priority, 105 _param->_nb_bank, 106 _param->_nb_bank); 107 108 _priority_spr = new generic::priority::Priority (_name+"_priority_spr", 109 _param->_priority, 110 _param->_nb_bank, 111 _param->_nb_bank); 103 112 104 113 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp
r88 r109 58 58 59 59 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 61 delete _component; 62 60 delete _priority_gpr; 61 delete _priority_spr; 62 63 delete _component; 64 63 65 log_printf(FUNC,Free_List_unit,FUNCTION,"End"); 64 66 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp
r108 r109 26 26 log_function(Free_List_unit,FUNCTION,_name.c_str()); 27 27 28 std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select(); 29 std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin(); 30 31 std::list<generic::priority::select_t> * select_spr = _priority_spr->select(); 32 std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin(); 33 28 34 for (uint32_t i=0; i<_param->_nb_pop; i++) 29 35 { 30 36 log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 31 32 uint32_t offset = i*_param->_nb_bank_by_pop; 33 37 34 38 // GPR 35 39 bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 36 40 37 41 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 38 42 39 43 if (not gpr_ack) 40 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 41 { 42 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop 43 ); 44 45 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 46 47 if (not _gpr_list[bank].empty()) 48 { 49 // find 50 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 51 52 gpr_ack = true; 53 internal_POP_GPR_BANK [i] = bank; 54 PORT_WRITE(out_POP_GPR_NUM_REG [i], 55 //(bank << _param->_shift) | // only in VHDL 56 _gpr_list[bank].front()); 57 58 break; 59 } 60 } 44 { 45 // scan all bank 46 for (; 47 it_gpr!=select_gpr->end(); 48 ++it_gpr) 49 { 50 uint32_t num_bank = it_gpr->grp; 51 52 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 53 54 if (not _gpr_list[num_bank].empty()) 55 { 56 // find 57 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[num_bank].front()); 58 59 gpr_ack = true; 60 internal_POP_GPR_BANK [i] = num_bank; 61 PORT_WRITE(out_POP_GPR_NUM_REG [i], 62 //(num_bank << _param->_shift) | // only in VHDL 63 _gpr_list[num_bank].front()); 64 65 ++it_gpr; 66 break; 67 } 68 } 69 } 61 70 62 71 // SPR 63 72 bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 73 74 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 75 76 if (not spr_ack) 77 { 78 // scan all bank 79 for (; 80 it_spr!=select_spr->end(); 81 ++it_spr) 82 { 83 uint32_t num_bank = it_spr->grp; 84 85 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 86 87 if (not _spr_list[num_bank].empty()) 88 { 89 // find 90 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[num_bank].front()); 91 92 spr_ack = true; 93 internal_POP_SPR_BANK [i] = num_bank; 94 PORT_WRITE(out_POP_SPR_NUM_REG [i], 95 //(num_bank << _param->_shift) | // only in VHDL 96 _spr_list[num_bank].front()); 97 98 ++it_spr; 99 break; 100 } 101 } 102 } 64 103 65 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i]));66 67 if (not spr_ack)68 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++)69 {70 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop71 );72 73 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank);74 75 if (not _spr_list[bank].empty())76 {77 // find78 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front());79 80 spr_ack = true;81 internal_POP_SPR_BANK [i] = bank;82 PORT_WRITE(out_POP_SPR_NUM_REG [i],83 //(bank << _param->_shift) | // only in VHDL84 _spr_list[bank].front());85 86 break;87 }88 }89 104 90 105 internal_POP_ACK [i] = gpr_ack and spr_ack; 91 92 106 PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 93 107 } 108 109 // for (uint32_t i=0; i<_param->_nb_pop; i++) 110 // { 111 // log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 112 113 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 114 115 // // GPR 116 // bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 117 118 // log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 119 120 // if (not gpr_ack) 121 // { 122 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 123 // { 124 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 125 126 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 127 128 // if (not _gpr_list[bank].empty()) 129 // { 130 // // find 131 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 132 133 // gpr_ack = true; 134 // internal_POP_GPR_BANK [i] = bank; 135 // PORT_WRITE(out_POP_GPR_NUM_REG [i], 136 // //(bank << _param->_shift) | // only in VHDL 137 // _gpr_list[bank].front()); 138 139 // break; 140 // } 141 // } 142 // } 143 144 // // SPR 145 // bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 146 147 // log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 148 149 // if (not spr_ack) 150 // { 151 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 152 153 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 154 // { 155 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 156 157 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 158 159 // if (not _spr_list[bank].empty()) 160 // { 161 // // find 162 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); 163 164 // spr_ack = true; 165 // internal_POP_SPR_BANK [i] = bank; 166 // PORT_WRITE(out_POP_SPR_NUM_REG [i], 167 // //(bank << _param->_shift) | // only in VHDL 168 // _spr_list[bank].front()); 169 170 // break; 171 // } 172 // } 173 // } 174 175 // internal_POP_ACK [i] = gpr_ack and spr_ack; 176 177 // PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 178 // } 94 179 95 180 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r108 r109 28 28 if (PORT_READ(in_NRESET) == 0) 29 29 { 30 reg_BANK_PRIORITY = 0; 30 _priority_gpr->reset(); 31 _priority_spr->reset(); 32 31 33 for (uint32_t i=0; i<_param->_nb_bank; i++) 32 34 { … … 37 39 else 38 40 { 41 _priority_gpr->transition(); 42 _priority_spr->transition(); 43 39 44 // ================================================== 40 45 // =====[ POP ]====================================== … … 76 81 _spr_list [internal_PUSH_SPR_BANK[i]].push_back(PORT_READ(in_PUSH_SPR_NUM_REG [i])); 77 82 } 78 79 if (_param->_priority == PRIORITY_ROUND_ROBIN)80 reg_BANK_PRIORITY = (reg_BANK_PRIORITY+1)%_param->_nb_bank_by_pop;81 83 82 84 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp
r108 r109 45 45 uint32_t size_special_register = log2(nb_special_register); 46 46 47 _nb_bank_by_pop = _nb_bank / _nb_pop;47 // _nb_bank_by_pop = _nb_bank / _nb_pop; 48 48 49 49 uint32_t gpr_nb_slot = nb_general_register - nb_thread*_nb_general_register_logic; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r108 r109 1527 1527 dest,"insert_"+toString(i)); 1528 1528 #endif 1529 1530 1529 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_VAL" , 1531 1530 dest,"out_INSERT_"+toString(i)+"_VAL" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
r108 r109 734 734 } 735 735 736 // log_printf(TRACE,Core,FUNCTION,_(" * front_end_instruction_implemeted")); 737 // for (uint32_t i=0; i<_nb_front_end; ++i) 738 // for (uint32_t j=0; j<_nb_context[i]; ++j) 739 // for (uint32_t k=0; k<NB_INSTRUCTION; ++k) 740 // log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d] = %d - type : %d, operation : %d, size_data : %d, latence : %d") 741 // ,i,j,k,_front_end_instruction_implemeted[i][j][k] 742 // ,instruction_information(k)._type 743 // ,instruction_information(k)._operation 744 // ,instruction_size_data(k) 745 // ,_timing[0][instruction_information(k)._type][instruction_information(k)._operation]._latence); 746 736 747 // Reedit timing 737 748 { … … 976 987 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 977 988 { 989 log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_table_issue_type [%d]"),i); 990 991 978 992 // Init 979 993 for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) … … 996 1010 if (_table_dispatch[i][j][k]) 997 1011 { 998 pair_dual x = _link_read_unit_with_read_bloc[ i];1012 pair_dual x = _link_read_unit_with_read_bloc[k]; 999 1013 _network_table_dispatch [i][j][x.first][x.second] = true; 1000 1014 1001 1015 // Test functional unit connected with this read bloc 1002 1016 for (uint32_t l=0; l<_nb_functionnal_unit; ++l) 1003 // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l] 1004 if (_link_read_bloc_and_functionnal_unit [k][l]) 1005 { 1006 // Scan timing table, test if have an instruction 1007 for (uint32_t m=0; m<_nb_type; ++m) 1008 for (uint32_t n=0; n<_nb_operation; ++n) 1009 if (_timing[l][m][n]._latence > 0) 1010 { 1011 _ooo_engine_table_issue_type [i][j][m] = true; 1012 break; 1013 } 1014 1015 for (uint32_t m=0; m<_nb_thread; ++m) 1016 { 1017 list_thread_with_inst_issue [j].push_back(m); 1018 1019 uint32_t num_front_end = _link_context_with_thread [m].first; 1020 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1021 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1022 1023 _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1024 } 1025 } 1026 1017 { 1018 // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l] 1019 if (_link_read_bloc_and_functionnal_unit [k][l]) 1020 { 1021 // Scan timing table, test if have an instruction 1022 for (uint32_t m=0; m<_nb_type; ++m) 1023 for (uint32_t n=0; n<_nb_operation; ++n) 1024 if (_timing[l][m][n]._latence > 0) 1025 { 1026 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,m); 1027 1028 _ooo_engine_table_issue_type [i][j][m] = true; 1029 break; 1030 } 1031 1032 for (uint32_t m=0; m<_nb_thread; ++m) 1033 { 1034 list_thread_with_inst_issue [j].push_back(m); 1035 1036 uint32_t num_front_end = _link_context_with_thread [m].first; 1037 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1038 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1039 1040 _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1041 } 1042 } 1043 } 1044 1027 1045 // Test load store unit connected with this read bloc 1028 1046 for (uint32_t l=0; l<_nb_load_store_unit; ++l) 1029 1047 { 1030 _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; 1031 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); 1032 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); 1033 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); 1034 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0); 1035 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0); 1036 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0); 1037 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0); 1038 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); 1039 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); 1040 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); 1041 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); 1042 1048 // Test load store unit connected with this read bloc 1043 1049 if (_link_read_bloc_and_load_store_unit [k][l]) 1044 // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l] 1045 for (uint32_t m=0; m<_nb_thread; ++m) 1046 { 1047 list_thread_with_inst_issue [j].push_back(m); 1048 1049 1050 uint32_t num_front_end = _link_context_with_thread [m].first; 1051 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1052 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1053 1054 _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1055 } 1050 { 1051 _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; 1052 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); 1053 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); 1054 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); 1055 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0); 1056 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0); 1057 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0); 1058 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0); 1059 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); 1060 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); 1061 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); 1062 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); 1063 1064 // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l] 1065 for (uint32_t m=0; m<_nb_thread; ++m) 1066 { 1067 list_thread_with_inst_issue [j].push_back(m); 1068 1069 uint32_t num_front_end = _link_context_with_thread [m].first; 1070 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1071 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1072 1073 log_printf(TRACE,Core,FUNCTION,_(" * list_load_store_unit_with_rename_unit [%d][%d][%d] = %d"),i,num_rename_unit,_list_load_store_unit_with_rename_unit [i][num_rename_unit].size(),l); 1074 1075 _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1076 } 1077 } 1056 1078 } 1057 1079 } … … 1104 1126 } 1105 1127 1128 log_printf(TRACE,Core,FUNCTION,_(" * network_table_dispatch [nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit]")); 1129 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1130 for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) 1131 for (uint32_t k=0; k<_nb_execute_loop; ++k) 1132 for (uint32_t l=0; l<_nb_read_unit[k]; ++l) 1133 if (_network_table_dispatch [i][j][k][l] == true) 1134 log_printf(TRACE,Core,FUNCTION,_(" Issue Slot [%d][%d] is connected with Read_unit [%d][%d]"),i,j,k,l); 1135 1106 1136 ALLOC2(_ooo_engine_nb_load_store_unit ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); 1107 1137 1138 log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_nb_load_store_unit [nb_ooo_engine][nb_rename_unit]")); 1108 1139 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1109 1140 for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) 1110 _ooo_engine_nb_load_store_unit [i][j] = _list_load_store_unit_with_rename_unit [i][j].size(); 1141 { 1142 _ooo_engine_nb_load_store_unit [i][j] = _list_load_store_unit_with_rename_unit [i][j].size(); 1143 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] = %d"),i,j,_ooo_engine_nb_load_store_unit [i][j]); 1144 } 1111 1145 1112 1146 ALLOC3(_ooo_engine_size_store_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); … … 1390 1424 // update translation 1391 1425 _execute_loop_translate_num_execute_unit [i][j] = num_fu; 1392 num_fu ++;1393 1426 1394 1427 // timing information 1395 _execute_loop_nb_inst_functionnal_unit [i][ j] = _nb_inst_functionnal_unit [num_functionnal_unit];1428 _execute_loop_nb_inst_functionnal_unit [i][num_fu] = _nb_inst_functionnal_unit [num_functionnal_unit]; 1396 1429 1430 log_printf(TRACE,Core,FUNCTION," * _execute_loop_nb_inst_functionnal_unit [%d][%d] = _nb_inst_functionnal_unit [%d] = %d",i,num_fu,num_functionnal_unit,_nb_inst_functionnal_unit [num_functionnal_unit]); 1431 1397 1432 for (uint32_t k=0; k<_nb_type; ++k) 1398 1433 for (uint32_t l=0; l<_nb_operation; ++l) 1399 1434 { 1400 //log_printf(TRACE,Core,FUNCTION,_("execute_loop_timing [%d][%d][%d][%d] = timing [%d][%d][%d]"),i,j,k,l,num_functionnal_unit,k,l);1401 _execute_loop_timing [i][ j][k][l] = _timing [num_functionnal_unit][k][l];1435 // log_printf(TRACE,Core,FUNCTION,_("execute_loop_timing [%d][%d][%d][%d] = timing [%d][%d][%d]"),i,num_fu,k,l,num_functionnal_unit,k,l); 1436 _execute_loop_timing [i][num_fu][k][l] = _timing [num_functionnal_unit][k][l]; 1402 1437 } 1403 1438 … … 1405 1440 // for (uint32_t k=0; k<_nb_operation; ++k) 1406 1441 // _execute_loop_timing [i][j][TYPE_MEMORY][k]._delay = _execute_loop_timing [i][j][TYPE_MEMORY][k]._latence = 0; 1442 1443 num_fu ++; 1407 1444 } 1408 1445 } … … 1533 1570 link = _link_read_bloc_and_functionnal_unit [num_read_bloc][num_functionnal_unit]; 1534 1571 1535 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d][all ] -> %d"),i,l,j,link);1572 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d][all (%d)] -> %d"),i,l,j,_execute_loop_nb_execute_unit_port [i][j],link); 1536 1573 1537 1574 for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) … … 1562 1599 link = _link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]; 1563 1600 1564 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][all ][%d] -> %d"),i,j,l,link);1601 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][all (%d)][%d] -> %d"),i,j,_execute_loop_nb_execute_unit_port [i][j],l,link); 1565 1602 1566 1603 for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp
r88 r109 144 144 // initialisation 145 145 uint32_t nb_link_execute_unit [_nb_execute_loop][max<uint32_t>(_nb_execute_unit,_nb_execute_loop)]; 146 uint32_t nb_functionnal_unit [_nb_execute_loop]; 147 uint32_t nb_load_store_unit [_nb_execute_loop]; 148 149 for (uint32_t i=0; i<_nb_execute_loop; ++i) 150 { 151 nb_functionnal_unit [i] = 0; 152 nb_load_store_unit [i] = 0; 153 154 for (uint32_t j=0; j<_nb_execute_unit[i];++j) 155 nb_link_execute_unit [i][j] = 0; 156 } 146 // uint32_t nb_functionnal_unit [_nb_functionnal_unit]; 147 // uint32_t nb_load_store_unit [_nb_load_store_unit]; 148 149 // for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 150 // nb_functionnal_unit [i] = 0; 151 152 // for (uint32_t i=0; i<_nb_load_store_unit; ++i) 153 // nb_load_store_unit [i] = 0; 154 155 for (uint32_t i=0; i<_nb_execute_loop; ++i) 156 for (uint32_t j=0; j<_nb_execute_unit[i];++j) 157 nb_link_execute_unit [i][j] = 0; 157 158 158 159 // set link … … 162 163 uint32_t num_execute_unit = _link_execute_unit_with_functionnal_unit [i].second; 163 164 165 log_printf(TRACE,Core,FUNCTION," * _link_execute_unit_with_functionnal_unit [%d] = %d.%d",i,num_execute_loop,num_execute_unit); 166 164 167 nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; 165 nb_functionnal_unit [i] ++;168 // nb_functionnal_unit [i] ++; 166 169 } 167 170 for (uint32_t i=0; i<_nb_load_store_unit; ++i) … … 171 174 172 175 nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; 173 nb_load_store_unit [i] ++;176 // nb_load_store_unit [i] ++; 174 177 } 175 178 … … 184 187 } 185 188 186 for (uint32_t i=0; i<_nb_functionnal_unit; ++i)187 {188 if (nb_functionnal_unit[i] == 0)189 test.error(toString(_("Functionnal_Unit [%d] is not instanced.\n"),i));190 if (nb_functionnal_unit[i] > 1)191 test.error(toString(_("Functionnal_Unit [%d] is linked with 2 or more time.\n"),i));192 }193 194 for (uint32_t i=0; i<_nb_load_store_unit; ++i)195 {196 if (nb_load_store_unit[i] == 0)197 test.error(toString(_("Load_Store_Unit [%d] is not instanced.\n"),i));198 if (nb_load_store_unit[i] > 1)199 test.error(toString(_("Load_Store_Unit [%d] is linked with 2 or more time.\n"),i));200 }189 // for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 190 // { 191 // if (nb_functionnal_unit[i] == 0) 192 // test.error(toString(_("Functionnal_Unit [%d] is not instanced.\n"),i)); 193 // if (nb_functionnal_unit[i] > 1) 194 // test.error(toString(_("Functionnal_Unit [%d] is linked with 2 or more time.\n"),i)); 195 // } 196 197 // for (uint32_t i=0; i<_nb_load_store_unit; ++i) 198 // { 199 // if (nb_load_store_unit[i] == 0) 200 // test.error(toString(_("Load_Store_Unit [%d] is not instanced.\n"),i)); 201 // if (nb_load_store_unit[i] > 1) 202 // test.error(toString(_("Load_Store_Unit [%d] is linked with 2 or more time.\n"),i)); 203 // } 201 204 } 202 205 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp
r101 r109 67 67 // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 68 68 { 69 ALLOC1_INTERFACE("slot", OUT, EAST, _("Internal slot."),_param->_nb_port_slot);69 ALLOC1_INTERFACE("slot", OUT, NORTH, _("Internal slot."),_param->_nb_port_slot); 70 70 71 71 ALLOC1_VALACK_OUT(out_SLOT_VAL ,VAL); … … 76 76 if (_param->_have_port_ptr) 77 77 { 78 ALLOC0_INTERFACE("ptr", OUT, EAST, _("Internal pointer."));78 ALLOC0_INTERFACE("ptr", OUT, SOUTH, _("Internal pointer.")); 79 79 80 80 if (_param->_have_port_ptr_write) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
r88 r109 2 2 * $Id$ 3 3 * 4 * [ 4 * [ Description ] 5 5 * 6 6 */ … … 27 27 _interfaces = entity->set_interfaces(); 28 28 29 // ~~~~~[ 29 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 30 30 { 31 31 Interface * interface = _interfaces->set_interface("" … … 40 40 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 41 41 } 42 // ~~~~~[ 42 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 43 43 44 44 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; … … 65 65 } 66 66 67 // ~~~~~[ 67 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 68 68 69 69 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; … … 90 90 } 91 91 92 // ~~~~~[ 92 // ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 93 93 94 94 in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r105 r109 50 50 TYPE_CUSTOM = 0x9, // 00000 - unit uniq , type optionnal 51 51 TYPE_BRANCH = 0xa, // 00000 - unit multiple 52 TYPE_MEMORY = 0xb // 00000 - unit uniq 52 TYPE_MEMORY = 0xb // 00000 - unit uniq , type exclusive 53 53 } type_t; 54 54 … … 57 57 # define MAX_TYPE (1<<SIZE_TYPE) 58 58 59 // TYPE | multiple? | Optionnal? | Exclusive? | Comment 60 //--------------+-----------+------------+------------+--------- 61 // TYPE_ALU | X | | | 62 // TYPE_SHIFT | X | | | ror is optionnal 63 // TYPE_MOVE | X | | | cmov is optionnal 64 // TYPE_TEST | X | | | 65 // TYPE_MUL | X | | | 66 // TYPE_DIV | X | X | | 67 // TYPE_EXTEND | X | X | | 68 // TYPE_FIND | X | X | | 69 // TYPE_SPECIAL | | | | mac unit is optionnal 70 // TYPE_CUSTOM | | X | | 71 // TYPE_BRANCH | X | | | 72 // TYPE_MEMORY | | | X | 73 59 74 # define is_type_valid(x) \ 60 (( x == TYPE_ALU ) or \ 61 ( x == TYPE_SHIFT ) or \ 62 ( x == TYPE_MOVE ) or \ 63 ( x == TYPE_TEST ) or \ 64 ( x == TYPE_MUL ) or \ 65 ( x == TYPE_DIV ) or \ 66 ( x == TYPE_EXTEND ) or \ 67 ( x == TYPE_FIND ) or \ 68 ( x == TYPE_SPECIAL) or \ 69 ( x == TYPE_CUSTOM ) or \ 70 ( x == TYPE_BRANCH ) or \ 71 ( x == TYPE_MEMORY )) 75 ((x == TYPE_ALU ) or \ 76 (x == TYPE_SHIFT ) or \ 77 (x == TYPE_MOVE ) or \ 78 (x == TYPE_TEST ) or \ 79 (x == TYPE_MUL ) or \ 80 (x == TYPE_DIV ) or \ 81 (x == TYPE_EXTEND ) or \ 82 (x == TYPE_FIND ) or \ 83 (x == TYPE_SPECIAL) or \ 84 (x == TYPE_CUSTOM ) or \ 85 (x == TYPE_BRANCH ) or \ 86 (x == TYPE_MEMORY )) 87 88 # define is_type_uniq(x) \ 89 ((x == TYPE_SPECIAL) or \ 90 (x == TYPE_CUSTOM ) or \ 91 (x == TYPE_MEMORY )) 92 93 # define is_type_optionnal(x) \ 94 ((x == TYPE_DIV ) or \ 95 (x == TYPE_EXTEND ) or \ 96 (x == TYPE_FIND ) or \ 97 (x == TYPE_CUSTOM )) 98 99 # define is_type_exclusive(x) \ 100 ((x == TYPE_MEMORY )) 72 101 73 102 //====================================================[ Operation ]===== … … 211 240 # define OPERATION_FIND_L_FL1 0x2 // 000_0000 l.fl1 212 241 213 # define OPERATION_SPECIAL_L_NOP 0x ff // 000_0000 l.nop242 # define OPERATION_SPECIAL_L_NOP 0x7f // 000_0000 l.nop 214 243 # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr 215 244 # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr … … 223 252 # define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys 224 253 # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap 225 226 254 227 255 # define OPERATION_BRANCH_NONE 0x1 // 000_0000 l.j … … 668 696 { 669 697 // ORBIS 670 INSTRUCTION_L_ADD, 671 INSTRUCTION_L_ADDC, 672 INSTRUCTION_L_ADDI, 673 INSTRUCTION_L_ADDIC, 674 INSTRUCTION_L_AND, 675 INSTRUCTION_L_ANDI, 676 INSTRUCTION_L_BF, 677 INSTRUCTION_L_BNF, 678 INSTRUCTION_L_CMOV, 679 INSTRUCTION_L_CSYNC, 680 INSTRUCTION_L_CUST1, 681 INSTRUCTION_L_CUST2, 682 INSTRUCTION_L_CUST3, 683 INSTRUCTION_L_CUST4, 684 INSTRUCTION_L_CUST5, 685 INSTRUCTION_L_CUST6, 686 INSTRUCTION_L_CUST7, 687 INSTRUCTION_L_CUST8, 688 INSTRUCTION_L_DIV, 689 INSTRUCTION_L_DIVU, 690 INSTRUCTION_L_EXTBS, 691 INSTRUCTION_L_EXTBZ, 692 INSTRUCTION_L_EXTHS, 693 INSTRUCTION_L_EXTHZ, 694 INSTRUCTION_L_EXTWS, 695 INSTRUCTION_L_EXTWZ, 696 INSTRUCTION_L_FF1, 697 INSTRUCTION_L_FL1, 698 INSTRUCTION_L_J, 699 INSTRUCTION_L_JAL, 700 INSTRUCTION_L_JALR, 701 INSTRUCTION_L_JR, 702 INSTRUCTION_L_LBS, 703 INSTRUCTION_L_LBZ, 704 INSTRUCTION_L_LD, 705 INSTRUCTION_L_LHS, 706 INSTRUCTION_L_LHZ, 707 INSTRUCTION_L_LWS, 708 INSTRUCTION_L_LWZ, 709 INSTRUCTION_L_MAC, 710 INSTRUCTION_L_MACI, 711 INSTRUCTION_L_MACRC, 712 INSTRUCTION_L_MFSPR, 713 INSTRUCTION_L_MOVHI, 714 INSTRUCTION_L_MSB, 715 INSTRUCTION_L_MSYNC, 716 INSTRUCTION_L_MTSPR, 717 INSTRUCTION_L_MUL, 718 INSTRUCTION_L_MULI, 719 INSTRUCTION_L_MULU, 720 INSTRUCTION_L_NOP, 721 INSTRUCTION_L_OR, 722 INSTRUCTION_L_ORI, 723 INSTRUCTION_L_PSYNC, 724 INSTRUCTION_L_RFE, 725 INSTRUCTION_L_ROR, 726 INSTRUCTION_L_RORI, 727 INSTRUCTION_L_SB, 728 INSTRUCTION_L_SD, 729 INSTRUCTION_L_SFEQ, 730 INSTRUCTION_L_SFEQI, 731 INSTRUCTION_L_SFGES, 732 INSTRUCTION_L_SFGESI, 733 INSTRUCTION_L_SFGEU, 734 INSTRUCTION_L_SFGEUI, 735 INSTRUCTION_L_SFGTS, 736 INSTRUCTION_L_SFGTSI, 737 INSTRUCTION_L_SFGTU, 738 INSTRUCTION_L_SFGTUI, 739 INSTRUCTION_L_SFLES, 740 INSTRUCTION_L_SFLESI, 741 INSTRUCTION_L_SFLEU, 742 INSTRUCTION_L_SFLEUI, 743 INSTRUCTION_L_SFLTS, 744 INSTRUCTION_L_SFLTSI, 745 INSTRUCTION_L_SFLTU, 746 INSTRUCTION_L_SFLTUI, 747 INSTRUCTION_L_SFNE, 748 INSTRUCTION_L_SFNEI, 749 INSTRUCTION_L_SH, 750 INSTRUCTION_L_SLL, 751 INSTRUCTION_L_SLLI, 752 INSTRUCTION_L_SRA, 753 INSTRUCTION_L_SRAI, 754 INSTRUCTION_L_SRL, 755 INSTRUCTION_L_SRLI, 756 INSTRUCTION_L_SUB, 757 INSTRUCTION_L_SW, 758 INSTRUCTION_L_SYS, 759 INSTRUCTION_L_TRAP, 760 INSTRUCTION_L_XOR, 761 INSTRUCTION_L_XORI, 762 // ORFPX 763 INSTRUCTION_LF_ADD_D, 764 INSTRUCTION_LF_ADD_S, 765 INSTRUCTION_LF_CUST1_D, 766 INSTRUCTION_LF_CUST1_S, 767 INSTRUCTION_LF_DIV_D, 768 INSTRUCTION_LF_DIV_S, 769 INSTRUCTION_LF_FTOI_D, 770 INSTRUCTION_LF_FTOI_S, 771 INSTRUCTION_LF_ITOF_D, 772 INSTRUCTION_LF_ITOF_S, 773 INSTRUCTION_LF_MADD_D, 774 INSTRUCTION_LF_MADD_S, 775 INSTRUCTION_LF_MUL_D, 776 INSTRUCTION_LF_MUL_S, 777 INSTRUCTION_LF_REM_D, 778 INSTRUCTION_LF_REM_S, 779 INSTRUCTION_LF_SFEQ_D, 780 INSTRUCTION_LF_SFEQ_S, 781 INSTRUCTION_LF_SFGE_D, 782 INSTRUCTION_LF_SFGE_S, 783 INSTRUCTION_LF_SFGT_D, 784 INSTRUCTION_LF_SFGT_S, 785 INSTRUCTION_LF_SFLE_D, 786 INSTRUCTION_LF_SFLE_S, 787 INSTRUCTION_LF_SFLT_D, 788 INSTRUCTION_LF_SFLT_S, 789 INSTRUCTION_LF_SFNE_D, 790 INSTRUCTION_LF_SFNE_S, 791 INSTRUCTION_LF_SUB_D, 792 INSTRUCTION_LF_SUB_S, 793 // ORVDX 794 INSTRUCTION_LV_ADD_B, 795 INSTRUCTION_LV_ADD_H, 796 INSTRUCTION_LV_ADDS_B, 797 INSTRUCTION_LV_ADDS_H, 798 INSTRUCTION_LV_ADDU_B, 799 INSTRUCTION_LV_ADDU_H, 800 INSTRUCTION_LV_ADDUS_B, 801 INSTRUCTION_LV_ADDUS_H, 802 INSTRUCTION_LV_ALL_EQ_B, 803 INSTRUCTION_LV_ALL_EQ_H, 804 INSTRUCTION_LV_ALL_GE_B, 805 INSTRUCTION_LV_ALL_GE_H, 806 INSTRUCTION_LV_ALL_GT_B, 807 INSTRUCTION_LV_ALL_GT_H, 808 INSTRUCTION_LV_ALL_LE_B, 809 INSTRUCTION_LV_ALL_LE_H, 810 INSTRUCTION_LV_ALL_LT_B, 811 INSTRUCTION_LV_ALL_LT_H, 812 INSTRUCTION_LV_ALL_NE_B, 813 INSTRUCTION_LV_ALL_NE_H, 814 INSTRUCTION_LV_AND, 815 INSTRUCTION_LV_ANY_EQ_B, 816 INSTRUCTION_LV_ANY_EQ_H, 817 INSTRUCTION_LV_ANY_GE_B, 818 INSTRUCTION_LV_ANY_GE_H, 819 INSTRUCTION_LV_ANY_GT_B, 820 INSTRUCTION_LV_ANY_GT_H, 821 INSTRUCTION_LV_ANY_LE_B, 822 INSTRUCTION_LV_ANY_LE_H, 823 INSTRUCTION_LV_ANY_LT_B, 824 INSTRUCTION_LV_ANY_LT_H, 825 INSTRUCTION_LV_ANY_NE_B, 826 INSTRUCTION_LV_ANY_NE_H, 827 INSTRUCTION_LV_AVG_B, 828 INSTRUCTION_LV_AVG_H, 829 INSTRUCTION_LV_CMP_EQ_B, 830 INSTRUCTION_LV_CMP_EQ_H, 831 INSTRUCTION_LV_CMP_GE_B, 832 INSTRUCTION_LV_CMP_GE_H, 833 INSTRUCTION_LV_CMP_GT_B, 834 INSTRUCTION_LV_CMP_GT_H, 835 INSTRUCTION_LV_CMP_LE_B, 836 INSTRUCTION_LV_CMP_LE_H, 837 INSTRUCTION_LV_CMP_LT_B, 838 INSTRUCTION_LV_CMP_LT_H, 839 INSTRUCTION_LV_CMP_NE_B, 840 INSTRUCTION_LV_CMP_NE_H, 841 INSTRUCTION_LV_CUST1, 842 INSTRUCTION_LV_CUST2, 843 INSTRUCTION_LV_CUST3, 844 INSTRUCTION_LV_CUST4, 845 INSTRUCTION_LV_MADDS_H, 846 INSTRUCTION_LV_MAX_B, 847 INSTRUCTION_LV_MAX_H, 848 INSTRUCTION_LV_MERGE_B, 849 INSTRUCTION_LV_MERGE_H, 850 INSTRUCTION_LV_MIN_B, 851 INSTRUCTION_LV_MIN_H, 852 INSTRUCTION_LV_MSUBS_H, 853 INSTRUCTION_LV_MULS_H, 854 INSTRUCTION_LV_NAND, 855 INSTRUCTION_LV_NOR, 856 INSTRUCTION_LV_OR, 857 INSTRUCTION_LV_PACK_B, 858 INSTRUCTION_LV_PACK_H, 859 INSTRUCTION_LV_PACKS_B, 860 INSTRUCTION_LV_PACKS_H, 861 INSTRUCTION_LV_PACKUS_B, 862 INSTRUCTION_LV_PACKUS_H, 863 INSTRUCTION_LV_PERM_N, 864 INSTRUCTION_LV_RL_B, 865 INSTRUCTION_LV_RL_H, 866 INSTRUCTION_LV_SLL, 867 INSTRUCTION_LV_SLL_B, 868 INSTRUCTION_LV_SLL_H, 869 INSTRUCTION_LV_SRA_B, 870 INSTRUCTION_LV_SRA_H, 871 INSTRUCTION_LV_SRL, 872 INSTRUCTION_LV_SRL_B, 873 INSTRUCTION_LV_SRL_H, 874 INSTRUCTION_LV_SUB_B, 875 INSTRUCTION_LV_SUB_H, 876 INSTRUCTION_LV_SUBS_B, 877 INSTRUCTION_LV_SUBS_H, 878 INSTRUCTION_LV_SUBU_B, 879 INSTRUCTION_LV_SUBU_H, 880 INSTRUCTION_LV_SUBUS_B, 881 INSTRUCTION_LV_SUBUS_H, 882 INSTRUCTION_LV_UNPACK_B, 883 INSTRUCTION_LV_UNPACK_H, 884 INSTRUCTION_LV_XOR 698 INSTRUCTION_L_ADD, //0 699 INSTRUCTION_L_ADDC, //1 700 INSTRUCTION_L_ADDI, //2 701 INSTRUCTION_L_ADDIC, //3 702 INSTRUCTION_L_AND, //4 703 INSTRUCTION_L_ANDI, //5 704 INSTRUCTION_L_BF, //6 705 INSTRUCTION_L_BNF, //7 706 INSTRUCTION_L_CMOV, //8 707 INSTRUCTION_L_CSYNC, //9 708 INSTRUCTION_L_CUST1, //10 709 INSTRUCTION_L_CUST2, //11 710 INSTRUCTION_L_CUST3, //12 711 INSTRUCTION_L_CUST4, //13 712 INSTRUCTION_L_CUST5, //14 713 INSTRUCTION_L_CUST6, //15 714 INSTRUCTION_L_CUST7, //16 715 INSTRUCTION_L_CUST8, //17 716 INSTRUCTION_L_DIV, //18 717 INSTRUCTION_L_DIVU, //19 718 INSTRUCTION_L_EXTBS, //20 719 INSTRUCTION_L_EXTBZ, //21 720 INSTRUCTION_L_EXTHS, //22 721 INSTRUCTION_L_EXTHZ, //23 722 INSTRUCTION_L_EXTWS, //24 723 INSTRUCTION_L_EXTWZ, //25 724 INSTRUCTION_L_FF1, //26 725 INSTRUCTION_L_FL1, //27 726 INSTRUCTION_L_J, //28 727 INSTRUCTION_L_JAL, //29 728 INSTRUCTION_L_JALR, //30 729 INSTRUCTION_L_JR, //31 730 INSTRUCTION_L_LBS, //32 731 INSTRUCTION_L_LBZ, //33 732 INSTRUCTION_L_LD, //34 733 INSTRUCTION_L_LHS, //35 734 INSTRUCTION_L_LHZ, //36 735 INSTRUCTION_L_LWS, //37 736 INSTRUCTION_L_LWZ, //38 737 INSTRUCTION_L_MAC, //39 738 INSTRUCTION_L_MACI, //40 739 INSTRUCTION_L_MACRC, //41 740 INSTRUCTION_L_MFSPR, //42 741 INSTRUCTION_L_MOVHI, //43 742 INSTRUCTION_L_MSB, //44 743 INSTRUCTION_L_MSYNC, //45 744 INSTRUCTION_L_MTSPR, //46 745 INSTRUCTION_L_MUL, //47 746 INSTRUCTION_L_MULI, //48 747 INSTRUCTION_L_MULU, //49 748 INSTRUCTION_L_NOP, //50 749 INSTRUCTION_L_OR, //51 750 INSTRUCTION_L_ORI, //52 751 INSTRUCTION_L_PSYNC, //53 752 INSTRUCTION_L_RFE, //54 753 INSTRUCTION_L_ROR, //55 754 INSTRUCTION_L_RORI, //56 755 INSTRUCTION_L_SB, //57 756 INSTRUCTION_L_SD, //58 757 INSTRUCTION_L_SFEQ, //59 758 INSTRUCTION_L_SFEQI, //60 759 INSTRUCTION_L_SFGES, //61 760 INSTRUCTION_L_SFGESI, //62 761 INSTRUCTION_L_SFGEU, //63 762 INSTRUCTION_L_SFGEUI, //64 763 INSTRUCTION_L_SFGTS, //65 764 INSTRUCTION_L_SFGTSI, //66 765 INSTRUCTION_L_SFGTU, //67 766 INSTRUCTION_L_SFGTUI, //68 767 INSTRUCTION_L_SFLES, //69 768 INSTRUCTION_L_SFLESI, //70 769 INSTRUCTION_L_SFLEU, //71 770 INSTRUCTION_L_SFLEUI, //72 771 INSTRUCTION_L_SFLTS, //73 772 INSTRUCTION_L_SFLTSI, //74 773 INSTRUCTION_L_SFLTU, //75 774 INSTRUCTION_L_SFLTUI, //76 775 INSTRUCTION_L_SFNE, //77 776 INSTRUCTION_L_SFNEI, //78 777 INSTRUCTION_L_SH, //79 778 INSTRUCTION_L_SLL, //80 779 INSTRUCTION_L_SLLI, //81 780 INSTRUCTION_L_SRA, //82 781 INSTRUCTION_L_SRAI, //83 782 INSTRUCTION_L_SRL, //84 783 INSTRUCTION_L_SRLI, //85 784 INSTRUCTION_L_SUB, //86 785 INSTRUCTION_L_SW, //87 786 INSTRUCTION_L_SYS, //88 787 INSTRUCTION_L_TRAP, //89 788 INSTRUCTION_L_XOR, //90 789 INSTRUCTION_L_XORI, //91 790 // ORFPX 791 INSTRUCTION_LF_ADD_D, //92 792 INSTRUCTION_LF_ADD_S, //93 793 INSTRUCTION_LF_CUST1_D, //94 794 INSTRUCTION_LF_CUST1_S, //95 795 INSTRUCTION_LF_DIV_D, //96 796 INSTRUCTION_LF_DIV_S, //97 797 INSTRUCTION_LF_FTOI_D, //98 798 INSTRUCTION_LF_FTOI_S, //99 799 INSTRUCTION_LF_ITOF_D, //100 800 INSTRUCTION_LF_ITOF_S, //101 801 INSTRUCTION_LF_MADD_D, //102 802 INSTRUCTION_LF_MADD_S, //103 803 INSTRUCTION_LF_MUL_D, //104 804 INSTRUCTION_LF_MUL_S, //105 805 INSTRUCTION_LF_REM_D, //106 806 INSTRUCTION_LF_REM_S, //107 807 INSTRUCTION_LF_SFEQ_D, //108 808 INSTRUCTION_LF_SFEQ_S, //109 809 INSTRUCTION_LF_SFGE_D, //110 810 INSTRUCTION_LF_SFGE_S, //111 811 INSTRUCTION_LF_SFGT_D, //112 812 INSTRUCTION_LF_SFGT_S, //113 813 INSTRUCTION_LF_SFLE_D, //114 814 INSTRUCTION_LF_SFLE_S, //115 815 INSTRUCTION_LF_SFLT_D, //116 816 INSTRUCTION_LF_SFLT_S, //117 817 INSTRUCTION_LF_SFNE_D, //118 818 INSTRUCTION_LF_SFNE_S, //119 819 INSTRUCTION_LF_SUB_D, //120 820 INSTRUCTION_LF_SUB_S, //121 821 // ORVDX 822 INSTRUCTION_LV_ADD_B, //122 823 INSTRUCTION_LV_ADD_H, //123 824 INSTRUCTION_LV_ADDS_B, //124 825 INSTRUCTION_LV_ADDS_H, //125 826 INSTRUCTION_LV_ADDU_B, //126 827 INSTRUCTION_LV_ADDU_H, //127 828 INSTRUCTION_LV_ADDUS_B, //128 829 INSTRUCTION_LV_ADDUS_H, //129 830 INSTRUCTION_LV_ALL_EQ_B, //130 831 INSTRUCTION_LV_ALL_EQ_H, //131 832 INSTRUCTION_LV_ALL_GE_B, //132 833 INSTRUCTION_LV_ALL_GE_H, //133 834 INSTRUCTION_LV_ALL_GT_B, //134 835 INSTRUCTION_LV_ALL_GT_H, //135 836 INSTRUCTION_LV_ALL_LE_B, //136 837 INSTRUCTION_LV_ALL_LE_H, //137 838 INSTRUCTION_LV_ALL_LT_B, //138 839 INSTRUCTION_LV_ALL_LT_H, //139 840 INSTRUCTION_LV_ALL_NE_B, //140 841 INSTRUCTION_LV_ALL_NE_H, //141 842 INSTRUCTION_LV_AND, //142 843 INSTRUCTION_LV_ANY_EQ_B, //143 844 INSTRUCTION_LV_ANY_EQ_H, //144 845 INSTRUCTION_LV_ANY_GE_B, //145 846 INSTRUCTION_LV_ANY_GE_H, //146 847 INSTRUCTION_LV_ANY_GT_B, //147 848 INSTRUCTION_LV_ANY_GT_H, //148 849 INSTRUCTION_LV_ANY_LE_B, //149 850 INSTRUCTION_LV_ANY_LE_H, //150 851 INSTRUCTION_LV_ANY_LT_B, //151 852 INSTRUCTION_LV_ANY_LT_H, //152 853 INSTRUCTION_LV_ANY_NE_B, //153 854 INSTRUCTION_LV_ANY_NE_H, //154 855 INSTRUCTION_LV_AVG_B, //155 856 INSTRUCTION_LV_AVG_H, //156 857 INSTRUCTION_LV_CMP_EQ_B, //157 858 INSTRUCTION_LV_CMP_EQ_H, //158 859 INSTRUCTION_LV_CMP_GE_B, //159 860 INSTRUCTION_LV_CMP_GE_H, //160 861 INSTRUCTION_LV_CMP_GT_B, //161 862 INSTRUCTION_LV_CMP_GT_H, //162 863 INSTRUCTION_LV_CMP_LE_B, //163 864 INSTRUCTION_LV_CMP_LE_H, //164 865 INSTRUCTION_LV_CMP_LT_B, //165 866 INSTRUCTION_LV_CMP_LT_H, //166 867 INSTRUCTION_LV_CMP_NE_B, //167 868 INSTRUCTION_LV_CMP_NE_H, //168 869 INSTRUCTION_LV_CUST1, //169 870 INSTRUCTION_LV_CUST2, //170 871 INSTRUCTION_LV_CUST3, //171 872 INSTRUCTION_LV_CUST4, //172 873 INSTRUCTION_LV_MADDS_H, //173 874 INSTRUCTION_LV_MAX_B, //174 875 INSTRUCTION_LV_MAX_H, //175 876 INSTRUCTION_LV_MERGE_B, //176 877 INSTRUCTION_LV_MERGE_H, //177 878 INSTRUCTION_LV_MIN_B, //178 879 INSTRUCTION_LV_MIN_H, //179 880 INSTRUCTION_LV_MSUBS_H, //180 881 INSTRUCTION_LV_MULS_H, //181 882 INSTRUCTION_LV_NAND, //182 883 INSTRUCTION_LV_NOR, //183 884 INSTRUCTION_LV_OR, //184 885 INSTRUCTION_LV_PACK_B, //185 886 INSTRUCTION_LV_PACK_H, //186 887 INSTRUCTION_LV_PACKS_B, //187 888 INSTRUCTION_LV_PACKS_H, //188 889 INSTRUCTION_LV_PACKUS_B, //189 890 INSTRUCTION_LV_PACKUS_H, //290 891 INSTRUCTION_LV_PERM_N, //291 892 INSTRUCTION_LV_RL_B, //292 893 INSTRUCTION_LV_RL_H, //293 894 INSTRUCTION_LV_SLL, //294 895 INSTRUCTION_LV_SLL_B, //295 896 INSTRUCTION_LV_SLL_H, //296 897 INSTRUCTION_LV_SRA_B, //297 898 INSTRUCTION_LV_SRA_H, //298 899 INSTRUCTION_LV_SRL, //299 900 INSTRUCTION_LV_SRL_B, //200 901 INSTRUCTION_LV_SRL_H, //201 902 INSTRUCTION_LV_SUB_B, //202 903 INSTRUCTION_LV_SUB_H, //203 904 INSTRUCTION_LV_SUBS_B, //204 905 INSTRUCTION_LV_SUBS_H, //205 906 INSTRUCTION_LV_SUBU_B, //206 907 INSTRUCTION_LV_SUBU_H, //207 908 INSTRUCTION_LV_SUBUS_B, //208 909 INSTRUCTION_LV_SUBUS_H, //209 910 INSTRUCTION_LV_UNPACK_B, //210 911 INSTRUCTION_LV_UNPACK_H, //211 912 INSTRUCTION_LV_XOR //212 885 913 }; 886 914 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h
r108 r109 8 8 #include "Common/include/ToString.h" 9 9 10 #define MORPHEO_MAJOR_VERSION 011 #define MORPHEO_MINOR_VERSION 212 #define MORPHEO_REVISION "10 8"10 #define MORPHEO_MAJOR_VERSION "0" 11 #define MORPHEO_MINOR_VERSION "2" 12 #define MORPHEO_REVISION "109" 13 13 #define MORPHEO_CODENAME "Castor" 14 14 15 #define MORPHEO_DATE_DAY "1 2"15 #define MORPHEO_DATE_DAY "16" 16 16 #define MORPHEO_DATE_MONTH "02" 17 17 #define MORPHEO_DATE_YEAR "2009" -
trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed
r90 r109 8 8 #include "Common/include/ToString.h" 9 9 10 #define MORPHEO_MAJOR_VERSION 011 #define MORPHEO_MINOR_VERSION 210 #define MORPHEO_MAJOR_VERSION "0" 11 #define MORPHEO_MINOR_VERSION "2" 12 12 #define MORPHEO_REVISION "@REVISION" 13 13 #define MORPHEO_CODENAME "Castor" -
trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h
r100 r109 50 50 extern double debug_cycle_start; 51 51 extern double debug_cycle_stop ; 52 extern double debug_cycle_idle; 52 53 53 54 void debug_init (void); 54 55 void debug_init (debug_verbosity_t level, 55 56 double cycle_start, 56 double cycle_stop ); 57 double cycle_stop , 58 double cycle_idle); 57 59 58 60 #ifdef SYSTEMC -
trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp
r100 r109 11 11 namespace morpheo { 12 12 13 #ifdef DEBUG14 13 static bool debug_initialized; 15 #endif16 14 debug_verbosity_t debug; 17 15 bool debug_cycle_test; 18 16 double debug_cycle_start; 19 17 double debug_cycle_stop ; 18 double debug_cycle_idle; 20 19 21 20 #undef FUNCTION … … 37 36 void debug_init (debug_verbosity_t level, 38 37 double cycle_start, 39 double cycle_stop ) 38 double cycle_stop , 39 double cycle_idle) 40 40 { 41 #ifdef DEBUG42 41 if (not debug_initialized) 43 42 { 43 #ifdef DEBUG 44 44 // Take min 45 45 debug = (level < DEBUG)?level:DEBUG; 46 46 47 # ifdef SYSTEMC48 debug_cycle_test 49 debug_cycle_start 50 debug_cycle_stop 51 # else47 # ifdef SYSTEMC 48 debug_cycle_test = (cycle_stop > cycle_start) or (cycle_stop == -1); 49 debug_cycle_start= cycle_start; 50 debug_cycle_stop = cycle_stop; 51 # else 52 52 debug_cycle_test = false; 53 # endif 53 54 #endif 55 debug_cycle_idle = cycle_idle; 54 56 55 57 debug_initialized = true; 56 58 } 57 #endif58 59 } 59 60 -
trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.cfg
r91 r109 84 84 <parameter name="dir_predictor_scheme" value="1" /> 85 85 86 <predictor id="0"> 87 <parameter name="dir_have_bht" value="1" /> 88 <parameter name="dir_bht_size_shifter" value="1" /> 89 <parameter name="dir_bht_nb_shifter" value="1" /> 90 <parameter name="dir_have_pht" value="1" /> 91 <parameter name="dir_pht_size_counter" value="1" /> 92 <parameter name="dir_pht_nb_counter" value="1" /> 93 <parameter name="dir_pht_size_address_share" value="1" /> 94 </predictor> 95 96 <predictor id="1"> 97 <parameter name="dir_have_bht" value="1" /> 98 <parameter name="dir_bht_size_shifter" value="1" /> 99 <parameter name="dir_bht_nb_shifter" value="1" /> 100 <parameter name="dir_have_pht" value="1" /> 101 <parameter name="dir_pht_size_counter" value="1" /> 102 <parameter name="dir_pht_nb_counter" value="1" /> 103 <parameter name="dir_pht_size_address_share" value="1" /> 104 </predictor> 105 106 <predictor id="2"> 86 <predictor id="0,1,2"> 107 87 <parameter name="dir_have_bht" value="1" /> 108 88 <parameter name="dir_bht_size_shifter" value="1" /> -
trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/instance_configuration_file-fr.tex
r91 r109 30 30 \item[balise component :] {\it (Nombre quelconque d'occurrences)} {\it component} est le nom générique de la balise. En réalité il regroupe tous les blocs internes du processeur. Le nom de la balise prend alors le nom du composant. 31 31 \begin{description} 32 \item[attribut id : ] {\it (Obligatoire)} Identifiant du paramètre. 32 \item[attribut id : ] {\it (Obligatoire)} Identifiant du paramètre. Si plusieurs instance du composant ont les même paramètres, alors ils peuvent être factorisé en placant dans le champs id tous les identifiants séparés par une virgule. 33 33 \item[balise component :] {\it (Nombre quelconque d'occurrences)} Entités internes au bloc courant. 34 34 \item[balise parameter :] {\it (Nombre quelconque d'occurrences)} Un paramètre du composant courant. -
trunk/IPs/systemC/processor/Morpheo/Files/Instance_debug.cfg
r108 r109 4 4 5 5 <thread id="0"> 6 <parameter name="size_ifetch_queue" value=" 4" />6 <parameter name="size_ifetch_queue" value="16" /> 7 7 <parameter name="nb_inst_fetch" value="4" /> 8 8 <parameter name="ras_size_queue" value="8" /> 9 <parameter name="upt_size_queue" value=" 4" />9 <parameter name="upt_size_queue" value="8" /> 10 10 <parameter name="ufpt_size_queue" value="4" /> 11 11 … … 24 24 25 25 <rename_bloc id="0"> 26 <parameter name="nb_inst_insert" value=" 2" />26 <parameter name="nb_inst_insert" value="4" /> 27 27 <parameter name="nb_inst_retire" value="1" /> 28 28 <parameter name="rename_select_priority" value="1" /> … … 36 36 </rename_bloc> 37 37 38 <read_bloc id="0 ">38 <read_bloc id="0,1,2,3"> 39 39 <parameter name="size_read_queue" value="4" /> 40 40 <parameter name="size_reservation_station" value="4" /> … … 42 42 </read_bloc> 43 43 44 <read_bloc id="1"> 45 <parameter name="size_read_queue" value="4" /> 46 <parameter name="size_reservation_station" value="4" /> 47 <parameter name="nb_inst_retire_reservation_station" value="1" /> 48 </read_bloc> 49 50 <write_bloc id="0"> 51 <parameter name="size_write_queue" value="4" /> 52 <parameter name="size_execute_queue" value="4" /> 53 <parameter name="nb_bypass_write" value="0" /> 54 </write_bloc> 55 56 <write_bloc id="1"> 57 <parameter name="size_write_queue" value="4" /> 58 <parameter name="size_execute_queue" value="4" /> 59 <parameter name="nb_bypass_write" value="0" /> 60 </write_bloc> 61 62 <write_bloc id="2"> 63 <parameter name="size_write_queue" value="4" /> 64 <parameter name="size_execute_queue" value="4" /> 65 <parameter name="nb_bypass_write" value="0" /> 66 </write_bloc> 67 68 <write_bloc id="3"> 44 <write_bloc id="0,1,2,3"> 69 45 <parameter name="size_write_queue" value="4" /> 70 46 <parameter name="size_execute_queue" value="4" /> … … 83 59 </load_store_unit> 84 60 85 <functionnal_unit id="0 ">61 <functionnal_unit id="0,1" > 86 62 <parameter name="nb_inst_functionnal_unit" value="1" /> 87 63 88 <timing type="0" latence="1" delay="1" /> 64 <timing type="0" latence="1" delay="1" /> 65 <timing type="1" latence="1" delay="1" /> 66 <timing type="2" latence="1" delay="1" /> 67 <timing type="3" latence="1" delay="1" /> 68 <timing type="4" latence="1" delay="1" /> 69 <timing type="6" latence="1" delay="1" /> 70 <timing type="7" latence="1" delay="1" /> 71 </functionnal_unit> 72 73 <functionnal_unit id="2"> 74 <parameter name="nb_inst_functionnal_unit" value="1" /> 75 76 <timing type="8" latence="1" delay="1" /> 77 <timing type="10" latence="1" delay="1" /> 89 78 </functionnal_unit> 90 79 … … 94 83 <parameter name="nb_inst_branch_decod" value="1" /> 95 84 <parameter name="nb_inst_branch_update" value="1" /> 96 <parameter name="btb_size_queue" value=" 64" />97 <parameter name="btb_associativity" value=" 4" />85 <parameter name="btb_size_queue" value="256" /> 86 <parameter name="btb_associativity" value="8" /> 98 87 <parameter name="btb_size_counter" value="2" /> 99 88 <parameter name="btb_victim_scheme" value="3" /> 100 89 <parameter name="dir_predictor_scheme" value="2" /> 101 90 102 <predictor id="0 ">91 <predictor id="0,1,2"> 103 92 <parameter name="dir_have_bht" value="1" /> 104 93 <parameter name="dir_bht_size_shifter" value="1" /> … … 109 98 <parameter name="dir_pht_size_address_share" value="1" /> 110 99 </predictor> 111 112 <predictor id="1">113 <parameter name="dir_have_bht" value="1" />114 <parameter name="dir_bht_size_shifter" value="1" />115 <parameter name="dir_bht_nb_shifter" value="1" />116 <parameter name="dir_have_pht" value="1" />117 <parameter name="dir_pht_size_counter" value="1" />118 <parameter name="dir_pht_nb_counter" value="1" />119 <parameter name="dir_pht_size_address_share" value="1" />120 </predictor>121 122 <predictor id="2">123 <parameter name="dir_have_bht" value="1" />124 <parameter name="dir_bht_size_shifter" value="1" />125 <parameter name="dir_bht_nb_shifter" value="1" />126 <parameter name="dir_have_pht" value="1" />127 <parameter name="dir_pht_size_counter" value="1" />128 <parameter name="dir_pht_nb_counter" value="1" />129 <parameter name="dir_pht_size_address_share" value="1" />130 </predictor>131 100 </front_end> 132 101 133 102 <ooo_engine id="0"> 134 103 <parameter name="nb_rename_unit" value="1" /> 135 <parameter name="nb_inst_issue" value=" 2" />104 <parameter name="nb_inst_issue" value="4" /> 136 105 <parameter name="nb_inst_reexecute" value="1" /> 137 106 <parameter name="nb_inst_commit" value="1" /> … … 153 122 154 123 <execute_loop id="0"> 155 <parameter name="nb_read_unit" value=" 2" />124 <parameter name="nb_read_unit" value="4" /> 156 125 <parameter name="nb_write_unit" value="4" /> 126 <parameter name="nb_execute_unit" value="4" /> 157 127 <parameter name="nb_gpr_bank" value="1" /> 158 <parameter name="nb_gpr_port_read_by_bank" value=" 4" />159 <parameter name="nb_gpr_port_write_by_bank" value=" 2" />128 <parameter name="nb_gpr_port_read_by_bank" value="8" /> 129 <parameter name="nb_gpr_port_write_by_bank" value="4" /> 160 130 <parameter name="nb_spr_bank" value="1" /> 161 <parameter name="nb_spr_port_read_by_bank" value=" 2" />162 <parameter name="nb_spr_port_write_by_bank" value=" 2" />131 <parameter name="nb_spr_port_read_by_bank" value="4" /> 132 <parameter name="nb_spr_port_write_by_bank" value="4" /> 163 133 <parameter name="execution_unit_to_write_unit_priority" value="1" /> 164 134 <parameter name="read_unit_to_execution_unit_priority" value="1" /> 165 166 <execute_unit id="1">167 <link name="link_execute_unit_with_load_store_unit" src="0"/>168 </execute_unit>169 <execute_unit id="0">170 <link name="link_execute_unit_with_functionnal_unit" src="0"/>171 </execute_unit>172 173 135 </execute_loop> 174 136 … … 190 152 <link name="link_read_unit_with_read_bloc" src="0" dest="0.0" /> 191 153 <link name="link_read_unit_with_read_bloc" src="1" dest="0.1" /> 154 <link name="link_read_unit_with_read_bloc" src="2" dest="0.2" /> 155 <link name="link_read_unit_with_read_bloc" src="3" dest="0.3" /> 192 156 <link name="link_write_unit_with_write_bloc" src="0" dest="0.0" /> 193 157 <link name="link_write_unit_with_write_bloc" src="1" dest="0.1" /> … … 198 162 <link name="link_load_store_unit_with_thread" src="0" dest="0" /> 199 163 164 <link name="link_execute_unit_with_load_store_unit" src="0" dest="0.0"/> 165 <link name="link_execute_unit_with_functionnal_unit" src="0" dest="0.1"/> 166 <link name="link_execute_unit_with_functionnal_unit" src="1" dest="0.2"/> 167 <link name="link_execute_unit_with_functionnal_unit" src="2" dest="0.3"/> 168 200 169 <link name="link_icache_port_with_thread" src="0" dest="0" /> 201 170 <link name="link_dcache_port_with_load_store_unit" src="0.0" dest="0" /> 202 171 203 172 <link name="table_dispatch" src="0.0.0" dest="1" /> 204 <link name="table_dispatch" src="0.1.0" dest="1" /> 205 <link name="table_dispatch" src="0.0.1" dest="1" /> 173 <link name="table_dispatch" src="0.1.0" dest="0" /> 174 <link name="table_dispatch" src="0.2.0" dest="0" /> 175 <link name="table_dispatch" src="0.3.0" dest="0" /> 176 177 <link name="table_dispatch" src="0.0.1" dest="0" /> 206 178 <link name="table_dispatch" src="0.1.1" dest="1" /> 179 <link name="table_dispatch" src="0.2.1" dest="0" /> 180 <link name="table_dispatch" src="0.3.1" dest="0" /> 181 182 <link name="table_dispatch" src="0.0.2" dest="0" /> 183 <link name="table_dispatch" src="0.1.2" dest="0" /> 184 <link name="table_dispatch" src="0.2.2" dest="1" /> 185 <link name="table_dispatch" src="0.3.2" dest="0" /> 186 187 <link name="table_dispatch" src="0.0.3" dest="0" /> 188 <link name="table_dispatch" src="0.1.3" dest="0" /> 189 <link name="table_dispatch" src="0.2.3" dest="0" /> 190 <link name="table_dispatch" src="0.3.3" dest="1" /> 191 207 192 <link name="link_read_bloc_and_load_store_unit" src="0.0" dest="1" /> 208 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="1" /> 209 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="1" /> 193 <link name="link_read_bloc_and_load_store_unit" src="1.0" dest="0" /> 194 <link name="link_read_bloc_and_load_store_unit" src="2.0" dest="0" /> 195 <link name="link_read_bloc_and_load_store_unit" src="3.0" dest="0" /> 196 <link name="link_read_bloc_and_functionnal_unit" src="0.0" dest="0" /> 210 197 <link name="link_read_bloc_and_functionnal_unit" src="1.0" dest="1" /> 198 <link name="link_read_bloc_and_functionnal_unit" src="2.0" dest="1" /> 199 <link name="link_read_bloc_and_functionnal_unit" src="3.0" dest="0" /> 200 <link name="link_read_bloc_and_functionnal_unit" src="0.1" dest="0" /> 201 <link name="link_read_bloc_and_functionnal_unit" src="1.1" dest="1" /> 202 <link name="link_read_bloc_and_functionnal_unit" src="2.1" dest="1" /> 203 <link name="link_read_bloc_and_functionnal_unit" src="3.1" dest="0" /> 204 <link name="link_read_bloc_and_functionnal_unit" src="0.2" dest="0" /> 205 <link name="link_read_bloc_and_functionnal_unit" src="1.2" dest="0" /> 206 <link name="link_read_bloc_and_functionnal_unit" src="2.2" dest="0" /> 207 <link name="link_read_bloc_and_functionnal_unit" src="3.2" dest="1" /> 211 208 <link name="link_write_bloc_and_load_store_unit" src="0.0" dest="1" /> 212 209 <link name="link_write_bloc_and_load_store_unit" src="1.0" dest="1" /> … … 217 214 <link name="link_write_bloc_and_functionnal_unit" src="2.0" dest="1" /> 218 215 <link name="link_write_bloc_and_functionnal_unit" src="3.0" dest="1" /> 216 <link name="link_write_bloc_and_functionnal_unit" src="0.1" dest="1" /> 217 <link name="link_write_bloc_and_functionnal_unit" src="1.1" dest="1" /> 218 <link name="link_write_bloc_and_functionnal_unit" src="2.1" dest="1" /> 219 <link name="link_write_bloc_and_functionnal_unit" src="3.1" dest="1" /> 220 <link name="link_write_bloc_and_functionnal_unit" src="0.2" dest="1" /> 221 <link name="link_write_bloc_and_functionnal_unit" src="1.2" dest="1" /> 222 <link name="link_write_bloc_and_functionnal_unit" src="2.2" dest="1" /> 223 <link name="link_write_bloc_and_functionnal_unit" src="3.2" dest="1" /> 219 224 <link name="link_thread_and_functionnal_unit" src="0.0" dest="1" /> 225 <link name="link_thread_and_functionnal_unit" src="0.1" dest="1" /> 226 <link name="link_thread_and_functionnal_unit" src="0.2" dest="1" /> 220 227 221 228 </core> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen
r101 r109 15 15 16 16 <parameter name="nb_thread" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 17 <parameter name="size_ifetch_queue" min="1" max=" 8"step="* 2" default="2" level="..." description="..." />17 <parameter name="size_ifetch_queue" min="1" max="16" step="* 2" default="2" level="..." description="..." /> 18 18 <parameter name="nb_inst_fetch" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 19 19 <parameter name="implement_group" default="0" level="..." description="..." /> … … 105 105 <parameter name="nb_execute_loop" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 106 106 <parameter name="nb_read_unit" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 107 <parameter name="nb_execute_unit" min="1" max="8" step=" * 2" default="1" level="..." description="..." />107 <parameter name="nb_execute_unit" min="1" max="8" step="+ 1" default="1" level="..." description="..." /> 108 108 <parameter name="nb_write_unit" min="1" max="8" step="* 2" default="1" level="..." description="..." /> 109 109 <parameter name="nb_gpr_bank" min="1" max="8" step="* 2" default="1" level="..." description="..." /> … … 136 136 <link name="link_thread_and_functionnal_unit" src="..." description="..." /> 137 137 138 <parameter name="latence" min=" 1" max="64" step="+ 1" default="1" level="..." description="..." />139 <parameter name="delay" min=" 1" max="64" step="+ 1" default="1" level="..." description="..." />138 <parameter name="latence" min="0" max="64" step="+ 1" default="0" level="..." description="..." /> 139 <parameter name="delay" min="0" max="64" step="+ 1" default="0" level="..." description="..." /> 140 140 141 141 </parameters> -
trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim
r108 r109 24 24 25 25 <parameter name="debug_level" value="0"/> 26 <parameter name="debug_cycle_start" value="0" /> 27 <parameter name="debug_cycle_stop" value="400" /> 26 <parameter name="debug_cycle_start" value="1000" /> 27 <parameter name="debug_cycle_stop" value="1200" /> 28 <parameter name="debug_cycle_idle" value="100" /> 28 29 <parameter name="debug_have_log_file" value="0" /> 29 30
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