Changeset 109 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core
- Timestamp:
- Feb 16, 2009, 9:28:31 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core
- Files:
-
- 1 added
- 40 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp
r88 r109 29 29 for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert[i][j]; ++k) 30 30 { 31 PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_VAL [num_ooo_engine][k])); 32 PORT_WRITE(out_INSERT_OOO_ENGINE_ACK [i][j] ,PORT_READ(in_INSERT_EXECUTE_LOOP_ACK [i][j][k])); 31 log_printf(TRACE,Core_Glue,FUNCTION," * INSERT_OOO_ENGINE [%d][%d] <-> INSERT_EXECUTE_LOOP [%d][%d][%d]",num_ooo_engine,k,i,j,k); 32 33 Tcontrol_t ooo_engine_val = PORT_READ(in_INSERT_OOO_ENGINE_VAL [num_ooo_engine][k]); 34 Tcontrol_t execute_loop_ack = PORT_READ(in_INSERT_EXECUTE_LOOP_ACK [i][j][k]); 35 36 Tcontrol_t execute_loop_val = ooo_engine_val ; 37 Tcontrol_t ooo_engine_ack = execute_loop_ack; 38 39 log_printf(TRACE,Core_Glue,FUNCTION," * ooo_engine_val (r) : %d",ooo_engine_val ); 40 log_printf(TRACE,Core_Glue,FUNCTION," * ooo_engine_ack (w) : %d",ooo_engine_ack ); 41 log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop_val (w) : %d",execute_loop_val); 42 log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop_ack (r) : %d",execute_loop_ack); 43 44 PORT_WRITE(out_INSERT_OOO_ENGINE_ACK [num_ooo_engine][k],ooo_engine_ack ); 45 PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],execute_loop_val); 33 46 PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_USE [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_USE [num_ooo_engine][k])); 34 47 PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_NUM_REG [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_NUM_REG [num_ooo_engine][k])); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp
r88 r109 56 56 _table_execute_type = table_execute_type ; 57 57 _table_execute_thread = table_execute_thread; 58 59 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_routing [nb_read_unit][nb_execute_unit][nb_execute_unit_port]"); 60 for (uint32_t i=0; i<_nb_read_unit; ++i) 61 for (uint32_t j=0; j<_nb_execute_unit; ++j) 62 for (uint32_t k=0; k<_nb_execute_unit_port[j]; ++k) 63 if (_table_routing [i][j][k]) 64 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d][%d] -> true",i,j,k); 65 66 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_execute_type [nb_execute_unit][nb_type]"); 67 for (uint32_t i=0; i<_nb_execute_unit; ++i) 68 for (uint32_t j=0; j<_nb_type; ++j) 69 if (_table_execute_type [i][j]) 70 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d] -> true",i,j); 71 72 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * table_execute_thread [nb_execute_unit][nb_thread]"); 73 for (uint32_t i=0; i<_nb_execute_unit; ++i) 74 for (uint32_t j=0; j<_nb_thread; ++j) 75 if (_table_execute_thread [i][j]) 76 log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," [%d][%d] -> true",i,j); 58 77 59 78 _max_nb_read_unit_port = max<uint32_t>(_nb_read_unit_port, _nb_read_unit); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp
r97 r109 42 42 // TYPE_MEMORY | | | X | 43 43 44 bool type_valid [_nb_type];45 bool type_uniq [_nb_type]; // one thread can have multiple destination for this type ?46 bool type_optionnal [_nb_type]; // this type is optionnal ?47 bool type_exclusive [_nb_type]; // a unit that implement this type must be implement an another type ?48 49 for (Ttype_t i=0; i<_nb_type; i++)50 {51 type_valid [i] = false;52 type_uniq [i] = false;53 type_optionnal [i] = false;54 type_exclusive [i] = false;55 }56 57 type_valid [TYPE_ALU ] = true;58 type_valid [TYPE_SHIFT ] = true;59 type_valid [TYPE_MOVE ] = true;60 type_valid [TYPE_TEST ] = true;61 type_valid [TYPE_MUL ] = true;62 type_valid [TYPE_DIV ] = true;63 type_valid [TYPE_EXTEND ] = true;64 type_valid [TYPE_FIND ] = true;65 type_valid [TYPE_SPECIAL] = true;66 type_valid [TYPE_CUSTOM ] = true;67 type_valid [TYPE_BRANCH ] = true;68 type_valid [TYPE_MEMORY ] = true;69 70 type_uniq [TYPE_SPECIAL] = true;71 type_uniq [TYPE_CUSTOM ] = true;72 type_uniq [TYPE_MEMORY ] = true;73 74 type_optionnal [TYPE_DIV ] = true;75 type_optionnal [TYPE_EXTEND ] = true;76 type_optionnal [TYPE_FIND ] = true;77 type_optionnal [TYPE_CUSTOM ] = true;78 79 type_exclusive [TYPE_MEMORY ] = true;80 81 44 bool type_present [_nb_thread][_nb_type]; 82 45 for (uint32_t i=0; i<_nb_thread; i++) … … 94 57 95 58 // Test uniq type 96 if (type_present [j][k] and type_uniq[k])59 if (type_present [j][k] and is_type_uniq(k)) 97 60 test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString(k).c_str(),j)); 98 61 … … 101 64 102 65 for (Ttype_t j=0; j<_nb_type; j++) 103 if (not type_valid [j])66 if (not is_type_valid(j)) 104 67 for (uint32_t i=0; i<_nb_thread; i++) 105 68 if (type_present [i][j]) … … 107 70 108 71 for (Ttype_t j=0; j<_nb_type; j++) 109 if ( type_valid [j] and not type_optionnal[j])72 if (is_type_valid(j) and not is_type_optionnal(j)) 110 73 for (uint32_t i=0; i<_nb_thread; i++) 111 74 if (not type_present [i][j]) … … 115 78 for (uint32_t i=0; i<_nb_execute_unit; i++) 116 79 for (Ttype_t j=0; j<_nb_type; j++) 117 if ( type_exclusive [j]and _table_execute_type[i][j])80 if (is_type_exclusive(j) and _table_execute_type[i][j]) 118 81 for (Ttype_t k=0; k<_nb_type; k++) 119 82 if ((j != k) and (_table_execute_type[i][k] == true)) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp
r97 r109 156 156 if (timing[x][j][k]._latence > 0) 157 157 { 158 log_printf(TRACE,Execute_loop,FUNCTION," Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str());158 log_printf(TRACE,Execute_loop,FUNCTION," * Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str()); 159 159 _read_unit_to_execution_unit_table_execute_type [i][j] = true; 160 160 break; // find an operation 161 161 } 162 162 } 163 164 for (uint32_t i=0; i<_nb_load_store_unit; ++i) 165 log_printf(TRACE,Execute_loop,FUNCTION," * Load_store_unit [%d] - nb_inst : %d",i,_nb_inst_memory [i]); 166 for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 167 log_printf(TRACE,Execute_loop,FUNCTION," * Functionnal_unit [%d] - nb_inst : %d",i,_nb_inst_functionnal_unit [i]); 168 163 169 164 170 for (uint32_t i=0; i<_nb_execute_unit; i++) … … 170 176 else 171 177 _nb_execute_unit_port [i] = _nb_inst_functionnal_unit [x]; 178 179 log_printf(TRACE,Execute_loop,FUNCTION," * Execute unit [%d] (%d) - nb_inst : %d",i,x,_nb_execute_unit_port [i]); 172 180 } 173 181 … … 245 253 for (uint32_t k=0; k<_nb_write_unit; k++) 246 254 { 255 log_printf(TRACE,Execute_loop,FUNCTION," * Execution_unit_to_write_unit_table_routing [%d][%d][%d]",x,y,k); 256 247 257 // Test if this execute_unit can send operation at this write_unit 248 258 // Test if have not a previous link ! (a same read_unit can send operation à two execute_unit and each execute_unit send at the same write_unit) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Parameters.h
r88 r109 24 24 { 25 25 //-----[ fields ]------------------------------------------------------------ 26 public : uint32_t _nb_context ; 27 public : uint32_t _nb_inst_decod ; 28 public : uint32_t _size_queue ; 29 //public : uint32_t _size_general_data ; 30 public : uint32_t * _nb_branch_speculated ; //[nb_context] 31 32 public : uint32_t _nb_bank ; 33 public : uint32_t _size_bank ; 26 public : uint32_t _nb_context ; 27 public : uint32_t _nb_inst_decod ; 28 public : uint32_t _size_queue ; 29 //public : uint32_t _size_general_data ; 30 public : uint32_t * _nb_branch_speculated ; //[nb_context] 31 public : uint32_t _nb_instruction_in_queue; 34 32 35 33 //-----[ methods ]----------------------------------------------------------- -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp
r108 r109 29 29 //-------------------------------------------------------------------- 30 30 { 31 Tcontrol_t ack = reg_QUEUE->size() < _param->_size_ bank;31 Tcontrol_t ack = reg_QUEUE->size() < _param->_size_queue; 32 32 33 33 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp
r108 r109 145 145 it++) 146 146 { 147 log_printf(TRACE,Decod_queue,FUNCTION," * [%d] ",x);148 149 147 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 150 148 { 151 149 if ((*it)->_val [i]) 152 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d] %.1d, %.3d %.2d, %.2d %.3d %.1d %.1d, 0x%.8x (0x%.8x), %.1d 0x%.8x, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d" 153 ,i 150 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d][%.4d] %.1d, %.3d %.2d, %.2d %.3d %.1d %.1d, 0x%.8x (0x%.8x), %.1d 0x%.8x, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d, %.1d %.2d" 151 ,x 152 ,i 154 153 ,(*it)->_val [i] 155 154 ,(*it)->_context_id [i] … … 177 176 ); 178 177 else 179 log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d" 180 ,i 178 log_printf(TRACE,Decod_queue,FUNCTION," * [%.4d][%.4d] %d" 179 ,x 180 ,i 181 181 ,(*it)->_val [i] 182 182 ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp
r95 r109 29 29 log_begin(Decod_queue,FUNCTION); 30 30 31 _nb_context = nb_context ; 32 _nb_inst_decod = nb_inst_decod ; 33 _size_queue = size_queue ; 34 // _size_general_data = size_general_data ; 35 _nb_branch_speculated = nb_branch_speculated; 36 37 _nb_bank = _nb_inst_decod ; 38 _size_bank = _size_queue / _nb_bank; 31 _nb_context = nb_context ; 32 _nb_inst_decod = nb_inst_decod ; 33 _size_queue = size_queue/nb_inst_decod; 34 // _size_general_data = size_general_data ; 35 _nb_branch_speculated = nb_branch_speculated; 36 _nb_instruction_in_queue = size_queue; 39 37 40 38 test(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters_msg_error.cpp
r82 r109 27 27 Parameters_test test ("Decod_queue"); 28 28 29 if (not is_multiple (_size_queue,_nb_inst_decod))30 test.error( _("size_queue must be a multiple of nb_inst_decod.\n"));29 if (not is_multiple (_nb_instruction_in_queue,_nb_inst_decod)) 30 test.error("Size of decod queue must be a multiple of nb_instruction.\n"); 31 31 32 32 log_end(Decod_queue,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/configuration.cfg
r81 r109 1 1 Ifetch_queue 2 1 8*2 # _size_queue2 8 16 *2 # _size_queue 3 3 1 8 *2 # _nb_instruction 4 4 1 1 *2 # _size_branch_update_prediction -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h
r88 r109 28 28 //public : uint32_t _size_branch_update_prediction ; 29 29 //public : uint32_t _size_general_data ; 30 public : uint32_t _nb_instruction_in_queue ; 30 31 31 32 //public : uint32_t _size_queue_ptr ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp
r88 r109 27 27 log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); 28 28 29 _size_queue = size_queue ; 29 _nb_instruction_in_queue = size_queue ; 30 _size_queue = size_queue/nb_instruction ; 30 31 _nb_instruction = nb_instruction ; 31 32 // _size_branch_update_prediction = size_branch_update_prediction; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp
r88 r109 27 27 Parameters_test test ("Ifetch_queue"); 28 28 29 if (not is_multiple (_nb_instruction_in_queue,_nb_instruction)) 30 test.error("Size of ifetch queue must be a multiple of nb_instruction.\n"); 31 29 32 if (_size_queue == 1) 30 33 test.warning("To best perfomance, size_queue must be > 1.\n"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r106 r109 18 18 namespace prediction_unit { 19 19 namespace update_prediction_table { 20 21 typedef enum 22 { 23 EVENT_SOURCE_UFPT, 24 EVENT_SOURCE_UPT 25 } event_source_t; 20 26 21 27 typedef enum … … 115 121 }; // end namespace core 116 122 }; // end namespace behavioural 123 124 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_source_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_source_t& x) 125 { 126 switch (x) 127 { 128 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_SOURCE_UFPT : return "ufpt"; break; 129 case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_SOURCE_UPT : return "upt" ; break; 130 default : return ""; break; 131 } 132 }; 133 134 117 135 118 136 template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t& x) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r106 r109 183 183 184 184 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 185 private : event_source_t * reg_EVENT_SOURCE ; //[nb_context] 185 186 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] 186 187 private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r106 r109 209 209 ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); 210 210 211 ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); 212 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 213 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 214 ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); 215 ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); 211 ALLOC1(reg_EVENT_STATE ,event_state_t ,_param->_nb_context); 212 ALLOC1(reg_EVENT_SOURCE ,event_source_t,_param->_nb_context); 213 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 214 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 215 ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); 216 ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); 216 217 } 217 218 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r106 r109 163 163 164 164 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 165 DELETE1(reg_EVENT_SOURCE ,_param->_nb_context); 165 166 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); 166 167 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r108 r109 234 234 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; 235 235 } 236 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT; 236 237 237 238 // Flush UPFT … … 506 507 507 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 508 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);509 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 510 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 511 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 511 512 512 513 if (miss) … … 517 518 518 519 // Flush UPT 519 uint32_t top = reg_UPT_TOP [context]; 520 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 521 522 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 524 525 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 526 j!=top; 527 j=(j+1)%_param->_size_upt_queue[context]) 528 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 520 uint32_t top = reg_UPT_TOP [context]; 521 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 522 523 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 524 event_state_t event_state = reg_EVENT_STATE [context]; 525 bool previous_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 526 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 527 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 528 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or 529 ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and 530 (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT))); 531 // bool update_ras = (new_update != depth); 532 533 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 534 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 535 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_event : %d",previous_event); 537 538 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) 539 { 540 for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; 541 j!=top; 542 j=(j+1)%_param->_size_upt_queue[context]) 543 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 544 529 545 530 531 // reg_UPT_BOTTOM [context]; 532 reg_UPT_TOP [context] = depth; 533 reg_UPT_TOP_EVENT [context] = top; 534 535 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 536 reg_UPT_EMPTY [context] = true; 537 546 // reg_UPT_BOTTOM [context]; 547 reg_UPT_TOP [context] = depth; 548 // reg_UPT_TOP_EVENT [context] = top; 549 550 if (not previous_event) 551 { 552 reg_UPT_TOP_EVENT [context] = top; 553 reg_UPT_UPDATE [context] = new_update; 554 } 555 else 556 { 557 // Have event. Top index this slot 558 559 switch (reg_UPDATE_PREDICTION_TABLE [context][top]._state) 560 { 561 case UPDATE_PREDICTION_STATE_END_KO : 562 { 563 // Have already update predictor 564 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END; 565 break; 566 } 567 case UPDATE_PREDICTION_STATE_KO : 568 { 569 // Doesn't have update predictor 570 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT; 571 break; 572 } 573 default : 574 { 538 575 #ifdef DEBUG_TEST 539 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 540 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 541 #endif 542 543 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 544 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 545 546 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 547 event_state_t event_state = reg_EVENT_STATE [context]; 548 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 550 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 551 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 552 // bool update_ras = (new_update != depth); 553 554 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 555 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_update_ras : %d",previous_update_ras); 556 557 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 558 { 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 560 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 576 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 577 #endif 578 } 579 } 580 } 581 582 if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context]) 583 reg_UPT_EMPTY [context] = true; 584 585 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 586 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 587 588 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 589 { 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); 591 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT; 592 } 593 else 594 { 595 // if (not previous_update_ras) 596 { 597 // have ras prediction ? 598 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 599 600 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 601 602 } 603 } 604 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; 605 606 // else no update 607 608 reg_EVENT_DEPTH [context] = depth; 609 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 610 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 611 reg_EVENT_ADDRESS_DEST [context] = good_addr; 561 612 } 562 else 563 { 564 // if (not previous_update_ras) 565 { 566 // have ras prediction ? 567 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context); 568 569 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT; 570 571 } 572 } 573 574 if (not previous_update_ras) 575 { 576 reg_UPT_UPDATE [context] = new_update; 577 } 578 // else no update 579 580 reg_EVENT_DEPTH [context] = depth; 581 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State 582 reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; 583 reg_EVENT_ADDRESS_DEST [context] = good_addr; 584 } 613 } 585 614 else 586 615 { … … 901 930 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 902 931 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 932 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str()); 903 933 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 904 934 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
r108 r109 222 222 223 223 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 224 private : double ** _nb_cycle_idle; 225 224 226 private : std::list<entry_t*> * _rob ;//[nb_bank] 225 227 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
r108 r109 279 279 280 280 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 281 ALLOC2(_nb_cycle_idle ,double ,_param->_nb_front_end,_param->_nb_context [it1]); 281 282 ALLOC1(_rob ,std::list<entry_t*>,_param->_nb_bank); 282 283 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
r108 r109 187 187 188 188 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 189 DELETE2(_nb_cycle_idle ,_param->_nb_front_end,_param->_nb_context [it1]); 189 190 DELETE1(_rob ,_param->_nb_bank); 190 191 DELETE1(reg_BANK_PTR ,_param->_nb_bank); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
r100 r109 58 58 _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); 59 59 60 _stat->create_expr ("IPC", "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle"); 61 _stat->create_expr ("CPI", "/ 1 IPC" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction"); 60 _stat->create_expr ("IPC_ok" , "average_inst_retire_ok", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok)"); 61 _stat->create_expr ("CPI_ok" , "/ 1 IPC_ok" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok)"); 62 63 _stat->create_expr ("IPC_ko" , "average_inst_retire_ko", TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ko)"); 64 _stat->create_expr ("CPI_ko" , "/ 1 IPC_ko" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ko)"); 65 66 _stat->create_expr ("IPC_all", "average_inst_retire" , TYPE_COUNTER, "inst/cycle", "Instruction Per Cycle (Instruction Ok and Ko)"); 67 _stat->create_expr ("CPI_all", "/ 1 IPC_all" , TYPE_COUNTER, "cycle/inst", "Cycle Per Instruction (Instruction Ok and Ko)"); 62 68 } 63 69 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
r108 r109 41 41 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 42 42 { 43 _nb_cycle_idle [i][j] = 0; 44 43 45 reg_NB_INST_COMMIT_ALL [i][j] = 0; 44 46 reg_NB_INST_COMMIT_MEM [i][j] = 0; … … 59 61 else 60 62 { 63 // Increase number idle cycle 64 for (uint32_t i=0; i<_param->_nb_front_end; i++) 65 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 66 _nb_cycle_idle [i][j] ++; 67 61 68 // Compute next priority 62 69 _priority_insert->transition(); … … 402 409 _rob [i].pop_front(); 403 410 delete entry; 411 412 // Transaction on retire interface : reset watch dog timer. 413 _nb_cycle_idle [front_end_id][context_id] = 0; 404 414 } 405 415 … … 759 769 #endif 760 770 771 // Stop Condition 772 for (uint32_t i=0; i<_param->_nb_front_end; i++) 773 for (uint32_t j=0; j<_param->_nb_context [i]; j++) 774 if (_nb_cycle_idle [i][j] >= debug_cycle_idle) 775 throw ERRORMORPHEO(FUNCTION,toString(_("Context [%d][%d] is idle since %.0f cycles.\n"),i,j,_nb_cycle_idle [i][j])); 776 761 777 log_end(Commit_unit,FUNCTION); 762 778 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp
r88 r109 45 45 if (internal_BANK_IN_ACK [i]) 46 46 { 47 entry_t * entry = NULL;47 entry_t * entry = NULL; 48 48 49 49 if (internal_BANK_IN_IS_REEXECUTE [i]) … … 53 53 if (PORT_READ(in_REEXECUTE_VAL [y])) 54 54 { 55 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with REEXECUTE [%d]",i,y); 55 56 #ifdef STATISTICS 56 57 if (usage_is_set(_usage,USE_STATISTICS)) … … 62 63 (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [y]):0, 63 64 (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [y]):0, 64 PORT_READ(in_REEXECUTE_OPERATION [y]),65 PORT_READ(in_REEXECUTE_TYPE [y]),66 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]),65 PORT_READ(in_REEXECUTE_OPERATION [y]), 66 PORT_READ(in_REEXECUTE_TYPE [y]), 67 PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]), 67 68 (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [y]):0, 68 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]),69 PORT_READ(in_REEXECUTE_IMMEDIAT [y]),70 PORT_READ(in_REEXECUTE_READ_RA [y]),71 PORT_READ(in_REEXECUTE_NUM_REG_RA [y]),72 PORT_READ(in_REEXECUTE_READ_RB [y]),73 PORT_READ(in_REEXECUTE_NUM_REG_RB [y]),74 PORT_READ(in_REEXECUTE_READ_RC [y]),75 PORT_READ(in_REEXECUTE_NUM_REG_RC [y]),76 PORT_READ(in_REEXECUTE_WRITE_RD [y]),77 PORT_READ(in_REEXECUTE_NUM_REG_RD [y]),78 PORT_READ(in_REEXECUTE_WRITE_RE [y]),79 PORT_READ(in_REEXECUTE_NUM_REG_RE [y])69 PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]), 70 PORT_READ(in_REEXECUTE_IMMEDIAT [y]), 71 PORT_READ(in_REEXECUTE_READ_RA [y]), 72 PORT_READ(in_REEXECUTE_NUM_REG_RA [y]), 73 PORT_READ(in_REEXECUTE_READ_RB [y]), 74 PORT_READ(in_REEXECUTE_NUM_REG_RB [y]), 75 PORT_READ(in_REEXECUTE_READ_RC [y]), 76 PORT_READ(in_REEXECUTE_NUM_REG_RC [y]), 77 PORT_READ(in_REEXECUTE_WRITE_RD [y]), 78 PORT_READ(in_REEXECUTE_NUM_REG_RD [y]), 79 PORT_READ(in_REEXECUTE_WRITE_RE [y]), 80 PORT_READ(in_REEXECUTE_NUM_REG_RE [y]) 80 81 ); 81 82 } … … 88 89 if (PORT_READ(in_ISSUE_IN_VAL[x][y])) 89 90 { 91 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_IN [%d] - Transaction with ISSUE_IN [%d][%d]",i,x,y); 92 90 93 #ifdef STATISTICS 91 94 if (usage_is_set(_usage,USE_STATISTICS)) … … 97 100 (_param->_have_port_front_end_id )?PORT_READ(in_ISSUE_IN_FRONT_END_ID [x][y]):0, 98 101 (_param->_have_port_rob_ptr )?PORT_READ(in_ISSUE_IN_PACKET_ID [x][y]):0, 99 PORT_READ(in_ISSUE_IN_OPERATION [x][y]),100 PORT_READ(in_ISSUE_IN_TYPE [x][y]),101 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]),102 PORT_READ(in_ISSUE_IN_OPERATION [x][y]), 103 PORT_READ(in_ISSUE_IN_TYPE [x][y]), 104 PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]), 102 105 (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE [x][y]):0, 103 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]),104 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]),105 PORT_READ(in_ISSUE_IN_READ_RA [x][y]),106 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]),107 PORT_READ(in_ISSUE_IN_READ_RB [x][y]),108 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]),109 PORT_READ(in_ISSUE_IN_READ_RC [x][y]),110 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]),111 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]),112 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]),113 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]),114 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y])106 PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]), 107 PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]), 108 PORT_READ(in_ISSUE_IN_READ_RA [x][y]), 109 PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]), 110 PORT_READ(in_ISSUE_IN_READ_RB [x][y]), 111 PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]), 112 PORT_READ(in_ISSUE_IN_READ_RC [x][y]), 113 PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]), 114 PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]), 115 PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]), 116 PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]), 117 PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y]) 115 118 ); 116 119 } … … 140 143 if (PORT_READ(in_ISSUE_OUT_ACK [x])) 141 144 { 145 log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d] - Transaction with ISSUE_OUT [%d]",i,x); 146 147 142 148 entry_t * entry = _issue_queue [i].front(); 143 149 _issue_queue [i].pop_front(); … … 148 154 } 149 155 150 log_printf(TRACE,Issue_queue,FUNCTION," * InfoIssue_queue");156 log_printf(TRACE,Issue_queue,FUNCTION," * Dump Issue_queue"); 151 157 for (uint32_t i=0; i<_param->_nb_bank; i++) 152 158 { … … 155 161 *(_stat_bank_nb_inst [i]) += _issue_queue[i].size(); 156 162 #endif 157 log_printf(TRACE,Issue_queue,FUNCTION," * [%d] size : %d",i,(int)_issue_queue[i].size()); 163 log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d] size : %d",i,(int)_issue_queue[i].size()); 164 165 uint32_t j = 0; 166 for (std::list<entry_t*>::iterator it=_issue_queue[i].begin();it!=_issue_queue[i].end(); ++it) 167 { 168 log_printf(TRACE,Issue_queue,FUNCTION," [%.4d] %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d, %.1d %.4d", 169 j, 170 171 (*it)->_context_id , 172 (*it)->_front_end_id , 173 (*it)->_packet_id , 174 175 (*it)->_type , 176 (*it)->_operation , 177 178 (*it)->_store_queue_ptr_write, 179 (*it)->_load_queue_ptr_write , 180 181 (*it)->_has_immediat , 182 (*it)->_immediat , 183 184 (*it)->_read_ra , 185 (*it)->_num_reg_ra , 186 187 (*it)->_read_rb , 188 (*it)->_num_reg_rb , 189 190 (*it)->_read_rc , 191 (*it)->_num_reg_rc , 192 193 (*it)->_write_rd , 194 (*it)->_num_reg_rd , 195 196 (*it)->_write_re , 197 (*it)->_num_reg_re ); 198 199 ++j; 200 } 201 158 202 } 159 203 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp
r88 r109 57 57 _table_issue_type = table_issue_type ; 58 58 59 log_printf(TRACE,Issue_queue,FUNCTION," * table_routing [nb_rename_unit][nb_inst_issue]"); 60 for (uint32_t i=0; i<_nb_rename_unit; ++i) 61 for (uint32_t j=0; j<_nb_inst_issue; ++j) 62 if (_table_routing [i][j]) 63 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 64 65 log_printf(TRACE,Issue_queue,FUNCTION," * table_issue_type [nb_inst_issue][nb_type]"); 66 for (uint32_t i=0; i<_nb_inst_issue; ++i) 67 for (uint32_t j=0; j<_nb_type; ++j) 68 if (_table_issue_type [i][j]) 69 log_printf(TRACE,Issue_queue,FUNCTION," [%d][%d] -> true",i,j); 70 59 71 _max_nb_inst_rename = max<uint32_t>(_nb_inst_rename,_nb_rename_unit); 60 72 _nb_bank_select_out = _nb_bank/nb_inst_issue; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp
r108 r109 38 38 test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); 39 39 40 bool type_valid [_nb_type];41 42 for (uint32_t i=0; i<_nb_type; i++)43 type_valid [i] = false;44 45 type_valid [TYPE_ALU ] = true;46 type_valid [TYPE_SHIFT ] = true;47 type_valid [TYPE_MOVE ] = true;48 type_valid [TYPE_TEST ] = true;49 type_valid [TYPE_MUL ] = true;50 type_valid [TYPE_DIV ] = true;51 type_valid [TYPE_EXTEND ] = true;52 type_valid [TYPE_FIND ] = true;53 type_valid [TYPE_SPECIAL] = true;54 type_valid [TYPE_CUSTOM ] = true;55 type_valid [TYPE_BRANCH ] = true;56 type_valid [TYPE_MEMORY ] = true;57 58 40 for (uint32_t i=0; i<_nb_rename_unit; i++) 59 41 { … … 61 43 62 44 for (uint32_t j=0; j<_nb_type; j++) 63 type_present [j] = not type_valid [j];45 type_present [j] = not is_type_valid(j); 64 46 65 47 bool find = false; … … 77 59 else 78 60 for (uint32_t j=0; j<_nb_type; j++) 79 if (not type_present [j] )61 if (not type_present [j] and not is_type_optionnal(j)) 80 62 test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); 81 63 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp
r88 r109 27 27 for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) 28 28 { 29 // Transaction must be in-order 30 // Tcontrol_t previous_transaction = true; 29 // Transaction must be in-order : make in Rename_unit 31 30 32 31 for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) … … 38 37 Tcontrol_t issue_queue_ack = PORT_READ(in_INSERT_ISSUE_QUEUE_ACK [i][j]); 39 38 40 41 42 39 // if not execute -> don't route to issue_queue 43 40 44 41 Tcontrol_t val = ( 45 // previous_transaction and46 42 rename_unit_val and 47 43 commit_unit_ack and … … 49 45 issue_queue_ack)); 50 46 Tcontrol_t rename_unit_ack = ( 51 // previous_transaction and52 47 ack and 53 48 commit_unit_ack and … … 55 50 issue_queue_ack)); 56 51 Tcontrol_t commit_unit_val = ( 57 // previous_transaction and58 52 ack and 59 53 rename_unit_val and … … 61 55 issue_queue_ack)); 62 56 Tcontrol_t issue_queue_val = ( 63 // previous_transaction and64 57 ack and 65 58 rename_unit_val and … … 73 66 74 67 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * rename_unit [%d].inst_insert[%d] -> %d",i,j,x); 75 // log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * previous_transaction : %d",previous_transaction ); 76 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_val (w) : %d",val ); 77 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_ack (r) : %d",ack ); 68 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_val (RegisterFile) (w) : %d",val ); 69 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_ack (RegisterFile) (r) : %d",ack ); 78 70 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_val (r) : %d",rename_unit_val ); 79 71 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_ack (w) : %d",rename_unit_ack ); … … 84 76 log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_issue_queue_ack (r) : %d",issue_queue_ack ); 85 77 86 87 // previous_transaction = VAL and ACK;88 78 x ++; 89 79 } -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp
r88 r109 53 53 _size_rename_id = log2(_nb_rename_unit) ; 54 54 _sum_inst_insert = 0; 55 // 55 // _sum_inst_retire = 0; 56 56 57 57 for (uint32_t i=0; i<_nb_rename_unit; ++i) 58 58 { 59 59 _sum_inst_insert += _nb_inst_insert[i]; 60 // 60 // _sum_inst_retire += _nb_inst_retire[i]; 61 61 } 62 62 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/Makefile.deps
r81 r109 14 14 endif 15 15 16 ifndef Priority 17 include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps 18 endif 19 16 20 #-----[ Directory ]---------------------------------------- 17 21 18 Free_List_unit_DIR 22 Free_List_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit 19 23 20 24 #-----[ Library ]------------------------------------------ 21 25 22 Free_List_unit_LIBRARY = -lFree_List_unit \ 26 Free_List_unit_LIBRARY = -lFree_List_unit \ 27 $(Priority_LIBRARY) \ 23 28 $(Behavioural_LIBRARY) 24 29 25 Free_List_unit_DIR_LIBRARY = -L$(Free_List_unit_DIR)/lib \ 30 Free_List_unit_DIR_LIBRARY = -L$(Free_List_unit_DIR)/lib \ 31 $(Priority_DIR_LIBRARY) \ 26 32 $(Behavioural_DIR_LIBRARY) 27 33 … … 31 37 @\ 32 38 $(MAKE) Behavioural_library; \ 39 $(MAKE) Priority_library; \ 33 40 $(MAKE) --directory=$(Free_List_unit_DIR) --makefile=Makefile; 34 41 … … 36 43 @\ 37 44 $(MAKE) Behavioural_library_clean; \ 45 $(MAKE) Priority_library_clean; \ 38 46 $(MAKE) --directory=$(Free_List_unit_DIR) --makefile=Makefile clean; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/test.cpp
r88 r109 7 7 */ 8 8 9 #define NB_ITERATION 1 9 #define NB_ITERATION 16 10 10 #define CYCLE_MAX (128*NB_ITERATION) 11 11 … … 190 190 TEST(bool, gpr_free[reg],true); 191 191 192 Tgeneral_address_t bank = reg >> _param->_bank_gpr_size_slot;193 TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true);192 // Tgeneral_address_t bank = reg >> _param->_bank_gpr_size_slot; 193 // TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true); 194 194 195 195 gpr_free[reg] = false; … … 202 202 TEST(bool,spr_free[reg],true); 203 203 204 Tspecial_address_t bank = reg >> _param->_bank_spr_size_slot;205 TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true);204 // Tspecial_address_t bank = reg >> _param->_bank_spr_size_slot; 205 // TEST(bool, (bank >= (i*_param->_nb_bank_by_pop)) and (bank < ((i+1)*_param->_nb_bank_by_pop)), true); 206 206 207 207 spr_free[reg] = false; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Free_List_unit.h
r108 r109 28 28 #endif 29 29 #include "Behavioural/include/Usage.h" 30 31 #include "Behavioural/Generic/Priority/include/Priority.h" 30 32 31 33 namespace morpheo { … … 83 85 84 86 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 private : generic::priority::Priority * _priority_gpr; 88 private : generic::priority::Priority * _priority_spr; 85 89 86 90 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 89 93 90 94 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 91 private : uint32_t reg_BANK_PRIORITY;92 93 95 private : Tcontrol_t * internal_POP_ACK ; //[nb_pop] 94 96 private : uint32_t * internal_POP_GPR_BANK ; //[nb_pop] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Parameters.h
r88 r109 37 37 //public : uint32_t _size_special_register; 38 38 39 public : uint32_t _nb_bank_by_pop ;39 // public : uint32_t _nb_bank_by_pop ; 40 40 public : uint32_t _bank_gpr_nb_slot ; 41 41 public : uint32_t _bank_gpr_size_slot ; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp
r88 r109 101 101 } 102 102 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 103 _priority_gpr = new generic::priority::Priority (_name+"_priority_gpr", 104 _param->_priority, 105 _param->_nb_bank, 106 _param->_nb_bank); 107 108 _priority_spr = new generic::priority::Priority (_name+"_priority_spr", 109 _param->_priority, 110 _param->_nb_bank, 111 _param->_nb_bank); 103 112 104 113 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp
r88 r109 58 58 59 59 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 60 61 delete _component; 62 60 delete _priority_gpr; 61 delete _priority_spr; 62 63 delete _component; 64 63 65 log_printf(FUNC,Free_List_unit,FUNCTION,"End"); 64 66 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp
r108 r109 26 26 log_function(Free_List_unit,FUNCTION,_name.c_str()); 27 27 28 std::list<generic::priority::select_t> * select_gpr = _priority_gpr->select(); 29 std::list<generic::priority::select_t>::iterator it_gpr=select_gpr->begin(); 30 31 std::list<generic::priority::select_t> * select_spr = _priority_spr->select(); 32 std::list<generic::priority::select_t>::iterator it_spr=select_spr->begin(); 33 28 34 for (uint32_t i=0; i<_param->_nb_pop; i++) 29 35 { 30 36 log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 31 32 uint32_t offset = i*_param->_nb_bank_by_pop; 33 37 34 38 // GPR 35 39 bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 36 40 37 41 log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 38 42 39 43 if (not gpr_ack) 40 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 41 { 42 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop 43 ); 44 45 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 46 47 if (not _gpr_list[bank].empty()) 48 { 49 // find 50 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 51 52 gpr_ack = true; 53 internal_POP_GPR_BANK [i] = bank; 54 PORT_WRITE(out_POP_GPR_NUM_REG [i], 55 //(bank << _param->_shift) | // only in VHDL 56 _gpr_list[bank].front()); 57 58 break; 59 } 60 } 44 { 45 // scan all bank 46 for (; 47 it_gpr!=select_gpr->end(); 48 ++it_gpr) 49 { 50 uint32_t num_bank = it_gpr->grp; 51 52 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 53 54 if (not _gpr_list[num_bank].empty()) 55 { 56 // find 57 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[num_bank].front()); 58 59 gpr_ack = true; 60 internal_POP_GPR_BANK [i] = num_bank; 61 PORT_WRITE(out_POP_GPR_NUM_REG [i], 62 //(num_bank << _param->_shift) | // only in VHDL 63 _gpr_list[num_bank].front()); 64 65 ++it_gpr; 66 break; 67 } 68 } 69 } 61 70 62 71 // SPR 63 72 bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 73 74 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 75 76 if (not spr_ack) 77 { 78 // scan all bank 79 for (; 80 it_spr!=select_spr->end(); 81 ++it_spr) 82 { 83 uint32_t num_bank = it_spr->grp; 84 85 log_printf(TRACE,Free_List_unit,FUNCTION," * num_bank: %d",num_bank); 86 87 if (not _spr_list[num_bank].empty()) 88 { 89 // find 90 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[num_bank].front()); 91 92 spr_ack = true; 93 internal_POP_SPR_BANK [i] = num_bank; 94 PORT_WRITE(out_POP_SPR_NUM_REG [i], 95 //(num_bank << _param->_shift) | // only in VHDL 96 _spr_list[num_bank].front()); 97 98 ++it_spr; 99 break; 100 } 101 } 102 } 64 103 65 log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i]));66 67 if (not spr_ack)68 for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++)69 {70 uint32_t bank = offset+((j+reg_BANK_PRIORITY)%_param->_nb_bank_by_pop71 );72 73 log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank);74 75 if (not _spr_list[bank].empty())76 {77 // find78 log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front());79 80 spr_ack = true;81 internal_POP_SPR_BANK [i] = bank;82 PORT_WRITE(out_POP_SPR_NUM_REG [i],83 //(bank << _param->_shift) | // only in VHDL84 _spr_list[bank].front());85 86 break;87 }88 }89 104 90 105 internal_POP_ACK [i] = gpr_ack and spr_ack; 91 92 106 PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 93 107 } 108 109 // for (uint32_t i=0; i<_param->_nb_pop; i++) 110 // { 111 // log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); 112 113 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 114 115 // // GPR 116 // bool gpr_ack = not PORT_READ(in_POP_GPR_VAL[i]); 117 118 // log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_VAL : %d",PORT_READ(in_POP_GPR_VAL[i])); 119 120 // if (not gpr_ack) 121 // { 122 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 123 // { 124 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 125 126 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 127 128 // if (not _gpr_list[bank].empty()) 129 // { 130 // // find 131 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_gpr_list[bank].front()); 132 133 // gpr_ack = true; 134 // internal_POP_GPR_BANK [i] = bank; 135 // PORT_WRITE(out_POP_GPR_NUM_REG [i], 136 // //(bank << _param->_shift) | // only in VHDL 137 // _gpr_list[bank].front()); 138 139 // break; 140 // } 141 // } 142 // } 143 144 // // SPR 145 // bool spr_ack = not PORT_READ(in_POP_SPR_VAL[i]); 146 147 // log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_VAL : %d",PORT_READ(in_POP_SPR_VAL[i])); 148 149 // if (not spr_ack) 150 // { 151 // uint32_t offset = (i*_param->_nb_bank_by_pop) + reg_BANK_PRIORITY; 152 153 // for (uint32_t j=0; j<_param->_nb_bank_by_pop; j++) 154 // { 155 // uint32_t bank = (offset+((j+reg_BANK_BY_POP_PRIORITY)%_param->_nb_bank_by_pop))%_param->_nb_bank; 156 157 // log_printf(TRACE,Free_List_unit,FUNCTION," * bank : %d",bank); 158 159 // if (not _spr_list[bank].empty()) 160 // { 161 // // find 162 // log_printf(TRACE,Free_List_unit,FUNCTION," * find : %d",_spr_list[bank].front()); 163 164 // spr_ack = true; 165 // internal_POP_SPR_BANK [i] = bank; 166 // PORT_WRITE(out_POP_SPR_NUM_REG [i], 167 // //(bank << _param->_shift) | // only in VHDL 168 // _spr_list[bank].front()); 169 170 // break; 171 // } 172 // } 173 // } 174 175 // internal_POP_ACK [i] = gpr_ack and spr_ack; 176 177 // PORT_WRITE(out_POP_ACK [i], internal_POP_ACK [i]); 178 // } 94 179 95 180 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp
r108 r109 28 28 if (PORT_READ(in_NRESET) == 0) 29 29 { 30 reg_BANK_PRIORITY = 0; 30 _priority_gpr->reset(); 31 _priority_spr->reset(); 32 31 33 for (uint32_t i=0; i<_param->_nb_bank; i++) 32 34 { … … 37 39 else 38 40 { 41 _priority_gpr->transition(); 42 _priority_spr->transition(); 43 39 44 // ================================================== 40 45 // =====[ POP ]====================================== … … 76 81 _spr_list [internal_PUSH_SPR_BANK[i]].push_back(PORT_READ(in_PUSH_SPR_NUM_REG [i])); 77 82 } 78 79 if (_param->_priority == PRIORITY_ROUND_ROBIN)80 reg_BANK_PRIORITY = (reg_BANK_PRIORITY+1)%_param->_nb_bank_by_pop;81 83 82 84 #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp
r108 r109 45 45 uint32_t size_special_register = log2(nb_special_register); 46 46 47 _nb_bank_by_pop = _nb_bank / _nb_pop;47 // _nb_bank_by_pop = _nb_bank / _nb_pop; 48 48 49 49 uint32_t gpr_nb_slot = nb_general_register - nb_thread*_nb_general_register_logic; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
r108 r109 1527 1527 dest,"insert_"+toString(i)); 1528 1528 #endif 1529 1530 1529 PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_VAL" , 1531 1530 dest,"out_INSERT_"+toString(i)+"_VAL" ); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp
r108 r109 734 734 } 735 735 736 // log_printf(TRACE,Core,FUNCTION,_(" * front_end_instruction_implemeted")); 737 // for (uint32_t i=0; i<_nb_front_end; ++i) 738 // for (uint32_t j=0; j<_nb_context[i]; ++j) 739 // for (uint32_t k=0; k<NB_INSTRUCTION; ++k) 740 // log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d] = %d - type : %d, operation : %d, size_data : %d, latence : %d") 741 // ,i,j,k,_front_end_instruction_implemeted[i][j][k] 742 // ,instruction_information(k)._type 743 // ,instruction_information(k)._operation 744 // ,instruction_size_data(k) 745 // ,_timing[0][instruction_information(k)._type][instruction_information(k)._operation]._latence); 746 736 747 // Reedit timing 737 748 { … … 976 987 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 977 988 { 989 log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_table_issue_type [%d]"),i); 990 991 978 992 // Init 979 993 for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) … … 996 1010 if (_table_dispatch[i][j][k]) 997 1011 { 998 pair_dual x = _link_read_unit_with_read_bloc[ i];1012 pair_dual x = _link_read_unit_with_read_bloc[k]; 999 1013 _network_table_dispatch [i][j][x.first][x.second] = true; 1000 1014 1001 1015 // Test functional unit connected with this read bloc 1002 1016 for (uint32_t l=0; l<_nb_functionnal_unit; ++l) 1003 // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l] 1004 if (_link_read_bloc_and_functionnal_unit [k][l]) 1005 { 1006 // Scan timing table, test if have an instruction 1007 for (uint32_t m=0; m<_nb_type; ++m) 1008 for (uint32_t n=0; n<_nb_operation; ++n) 1009 if (_timing[l][m][n]._latence > 0) 1010 { 1011 _ooo_engine_table_issue_type [i][j][m] = true; 1012 break; 1013 } 1014 1015 for (uint32_t m=0; m<_nb_thread; ++m) 1016 { 1017 list_thread_with_inst_issue [j].push_back(m); 1018 1019 uint32_t num_front_end = _link_context_with_thread [m].first; 1020 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1021 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1022 1023 _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1024 } 1025 } 1026 1017 { 1018 // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l] 1019 if (_link_read_bloc_and_functionnal_unit [k][l]) 1020 { 1021 // Scan timing table, test if have an instruction 1022 for (uint32_t m=0; m<_nb_type; ++m) 1023 for (uint32_t n=0; n<_nb_operation; ++n) 1024 if (_timing[l][m][n]._latence > 0) 1025 { 1026 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,m); 1027 1028 _ooo_engine_table_issue_type [i][j][m] = true; 1029 break; 1030 } 1031 1032 for (uint32_t m=0; m<_nb_thread; ++m) 1033 { 1034 list_thread_with_inst_issue [j].push_back(m); 1035 1036 uint32_t num_front_end = _link_context_with_thread [m].first; 1037 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1038 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1039 1040 _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1041 } 1042 } 1043 } 1044 1027 1045 // Test load store unit connected with this read bloc 1028 1046 for (uint32_t l=0; l<_nb_load_store_unit; ++l) 1029 1047 { 1030 _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; 1031 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); 1032 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); 1033 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); 1034 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0); 1035 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0); 1036 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0); 1037 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0); 1038 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); 1039 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); 1040 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); 1041 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); 1042 1048 // Test load store unit connected with this read bloc 1043 1049 if (_link_read_bloc_and_load_store_unit [k][l]) 1044 // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l] 1045 for (uint32_t m=0; m<_nb_thread; ++m) 1046 { 1047 list_thread_with_inst_issue [j].push_back(m); 1048 1049 1050 uint32_t num_front_end = _link_context_with_thread [m].first; 1051 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1052 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1053 1054 _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1055 } 1050 { 1051 _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; 1052 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); 1053 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); 1054 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); 1055 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0); 1056 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0); 1057 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0); 1058 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0); 1059 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); 1060 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); 1061 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); 1062 // _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); 1063 1064 // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l] 1065 for (uint32_t m=0; m<_nb_thread; ++m) 1066 { 1067 list_thread_with_inst_issue [j].push_back(m); 1068 1069 uint32_t num_front_end = _link_context_with_thread [m].first; 1070 uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; 1071 uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; 1072 1073 log_printf(TRACE,Core,FUNCTION,_(" * list_load_store_unit_with_rename_unit [%d][%d][%d] = %d"),i,num_rename_unit,_list_load_store_unit_with_rename_unit [i][num_rename_unit].size(),l); 1074 1075 _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l); 1076 } 1077 } 1056 1078 } 1057 1079 } … … 1104 1126 } 1105 1127 1128 log_printf(TRACE,Core,FUNCTION,_(" * network_table_dispatch [nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit]")); 1129 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1130 for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) 1131 for (uint32_t k=0; k<_nb_execute_loop; ++k) 1132 for (uint32_t l=0; l<_nb_read_unit[k]; ++l) 1133 if (_network_table_dispatch [i][j][k][l] == true) 1134 log_printf(TRACE,Core,FUNCTION,_(" Issue Slot [%d][%d] is connected with Read_unit [%d][%d]"),i,j,k,l); 1135 1106 1136 ALLOC2(_ooo_engine_nb_load_store_unit ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); 1107 1137 1138 log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_nb_load_store_unit [nb_ooo_engine][nb_rename_unit]")); 1108 1139 for (uint32_t i=0; i<_nb_ooo_engine; ++i) 1109 1140 for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) 1110 _ooo_engine_nb_load_store_unit [i][j] = _list_load_store_unit_with_rename_unit [i][j].size(); 1141 { 1142 _ooo_engine_nb_load_store_unit [i][j] = _list_load_store_unit_with_rename_unit [i][j].size(); 1143 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] = %d"),i,j,_ooo_engine_nb_load_store_unit [i][j]); 1144 } 1111 1145 1112 1146 ALLOC3(_ooo_engine_size_store_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); … … 1390 1424 // update translation 1391 1425 _execute_loop_translate_num_execute_unit [i][j] = num_fu; 1392 num_fu ++;1393 1426 1394 1427 // timing information 1395 _execute_loop_nb_inst_functionnal_unit [i][ j] = _nb_inst_functionnal_unit [num_functionnal_unit];1428 _execute_loop_nb_inst_functionnal_unit [i][num_fu] = _nb_inst_functionnal_unit [num_functionnal_unit]; 1396 1429 1430 log_printf(TRACE,Core,FUNCTION," * _execute_loop_nb_inst_functionnal_unit [%d][%d] = _nb_inst_functionnal_unit [%d] = %d",i,num_fu,num_functionnal_unit,_nb_inst_functionnal_unit [num_functionnal_unit]); 1431 1397 1432 for (uint32_t k=0; k<_nb_type; ++k) 1398 1433 for (uint32_t l=0; l<_nb_operation; ++l) 1399 1434 { 1400 //log_printf(TRACE,Core,FUNCTION,_("execute_loop_timing [%d][%d][%d][%d] = timing [%d][%d][%d]"),i,j,k,l,num_functionnal_unit,k,l);1401 _execute_loop_timing [i][ j][k][l] = _timing [num_functionnal_unit][k][l];1435 // log_printf(TRACE,Core,FUNCTION,_("execute_loop_timing [%d][%d][%d][%d] = timing [%d][%d][%d]"),i,num_fu,k,l,num_functionnal_unit,k,l); 1436 _execute_loop_timing [i][num_fu][k][l] = _timing [num_functionnal_unit][k][l]; 1402 1437 } 1403 1438 … … 1405 1440 // for (uint32_t k=0; k<_nb_operation; ++k) 1406 1441 // _execute_loop_timing [i][j][TYPE_MEMORY][k]._delay = _execute_loop_timing [i][j][TYPE_MEMORY][k]._latence = 0; 1442 1443 num_fu ++; 1407 1444 } 1408 1445 } … … 1533 1570 link = _link_read_bloc_and_functionnal_unit [num_read_bloc][num_functionnal_unit]; 1534 1571 1535 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d][all ] -> %d"),i,l,j,link);1572 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d][all (%d)] -> %d"),i,l,j,_execute_loop_nb_execute_unit_port [i][j],link); 1536 1573 1537 1574 for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) … … 1562 1599 link = _link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]; 1563 1600 1564 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][all ][%d] -> %d"),i,j,l,link);1601 log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][all (%d)][%d] -> %d"),i,j,_execute_loop_nb_execute_unit_port [i][j],l,link); 1565 1602 1566 1603 for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp
r88 r109 144 144 // initialisation 145 145 uint32_t nb_link_execute_unit [_nb_execute_loop][max<uint32_t>(_nb_execute_unit,_nb_execute_loop)]; 146 uint32_t nb_functionnal_unit [_nb_execute_loop]; 147 uint32_t nb_load_store_unit [_nb_execute_loop]; 148 149 for (uint32_t i=0; i<_nb_execute_loop; ++i) 150 { 151 nb_functionnal_unit [i] = 0; 152 nb_load_store_unit [i] = 0; 153 154 for (uint32_t j=0; j<_nb_execute_unit[i];++j) 155 nb_link_execute_unit [i][j] = 0; 156 } 146 // uint32_t nb_functionnal_unit [_nb_functionnal_unit]; 147 // uint32_t nb_load_store_unit [_nb_load_store_unit]; 148 149 // for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 150 // nb_functionnal_unit [i] = 0; 151 152 // for (uint32_t i=0; i<_nb_load_store_unit; ++i) 153 // nb_load_store_unit [i] = 0; 154 155 for (uint32_t i=0; i<_nb_execute_loop; ++i) 156 for (uint32_t j=0; j<_nb_execute_unit[i];++j) 157 nb_link_execute_unit [i][j] = 0; 157 158 158 159 // set link … … 162 163 uint32_t num_execute_unit = _link_execute_unit_with_functionnal_unit [i].second; 163 164 165 log_printf(TRACE,Core,FUNCTION," * _link_execute_unit_with_functionnal_unit [%d] = %d.%d",i,num_execute_loop,num_execute_unit); 166 164 167 nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; 165 nb_functionnal_unit [i] ++;168 // nb_functionnal_unit [i] ++; 166 169 } 167 170 for (uint32_t i=0; i<_nb_load_store_unit; ++i) … … 171 174 172 175 nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; 173 nb_load_store_unit [i] ++;176 // nb_load_store_unit [i] ++; 174 177 } 175 178 … … 184 187 } 185 188 186 for (uint32_t i=0; i<_nb_functionnal_unit; ++i)187 {188 if (nb_functionnal_unit[i] == 0)189 test.error(toString(_("Functionnal_Unit [%d] is not instanced.\n"),i));190 if (nb_functionnal_unit[i] > 1)191 test.error(toString(_("Functionnal_Unit [%d] is linked with 2 or more time.\n"),i));192 }193 194 for (uint32_t i=0; i<_nb_load_store_unit; ++i)195 {196 if (nb_load_store_unit[i] == 0)197 test.error(toString(_("Load_Store_Unit [%d] is not instanced.\n"),i));198 if (nb_load_store_unit[i] > 1)199 test.error(toString(_("Load_Store_Unit [%d] is linked with 2 or more time.\n"),i));200 }189 // for (uint32_t i=0; i<_nb_functionnal_unit; ++i) 190 // { 191 // if (nb_functionnal_unit[i] == 0) 192 // test.error(toString(_("Functionnal_Unit [%d] is not instanced.\n"),i)); 193 // if (nb_functionnal_unit[i] > 1) 194 // test.error(toString(_("Functionnal_Unit [%d] is linked with 2 or more time.\n"),i)); 195 // } 196 197 // for (uint32_t i=0; i<_nb_load_store_unit; ++i) 198 // { 199 // if (nb_load_store_unit[i] == 0) 200 // test.error(toString(_("Load_Store_Unit [%d] is not instanced.\n"),i)); 201 // if (nb_load_store_unit[i] > 1) 202 // test.error(toString(_("Load_Store_Unit [%d] is linked with 2 or more time.\n"),i)); 203 // } 201 204 } 202 205
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