Ignore:
Timestamp:
Feb 27, 2009, 7:37:40 PM (15 years ago)
Author:
rosiere
Message:

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp

    r105 r111  
    110110      ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH              ,"depth"          ,Tdepth_t           ,_param->_size_depth);
    111111      ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION    ,"miss_prediction",Tcontrol_t         ,1);
    112       ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_TAKE               ,"take"           ,Tcontrol_t         ,1);
    113       ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC        ,"address_src"    ,Taddress_t         ,_param->_size_instruction_address);
    114       ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST       ,"address_dest"   ,Taddress_t         ,_param->_size_instruction_address);
     112//    ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_TAKE               ,"take"           ,Tcontrol_t         ,1);
     113//    ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC        ,"address_src"    ,Taddress_t         ,_param->_size_instruction_address);
     114//    ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST       ,"address_dest"   ,Taddress_t         ,_param->_size_instruction_address);
    115115    }
    116116
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