Changeset 111 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
- Timestamp:
- Feb 27, 2009, 7:37:40 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r109 r111 102 102 if (end) 103 103 { 104 #if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true) 105 if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok) 106 { 107 uint32_t num_thread = _param->_translate_num_context_to_num_thread [i]; 108 branchement_log_file [num_thread] 109 << std::hex 110 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " " 111 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " " 112 << std::dec 113 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " " 114 << std::endl; 115 } 116 #endif 104 117 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); 105 118 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); … … 180 193 // reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; 181 194 if (need_update(condition)) 182 reg_UFPT_NB_NEED_UPDATE [context] ++; 195 { 196 reg_UFPT_NB_NEED_UPDATE [context] ++; 197 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]); 198 199 } 183 200 } 184 201 … … 293 310 { 294 311 reg_UFPT_NB_NEED_UPDATE [context] --; 312 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]); 313 295 314 } 296 315 } … … 305 324 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write); 306 325 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END; 307 326 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false; 327 308 328 // Write new accurate 309 329 #ifdef DEBUG_TEST … … 377 397 // Free a register that need update ? 378 398 if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) 379 reg_UFPT_NB_NEED_UPDATE [context] --; 399 { 400 reg_UFPT_NB_NEED_UPDATE [context] --; 401 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]); 402 } 380 403 } 381 404 else … … 402 425 #ifdef STATISTICS 403 426 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 427 #endif 404 428 bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK); 405 #endif406 429 bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); 430 431 if (ok or ko) 432 reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; 407 433 408 434 // Have an update, test the state to transiste to the good state … … 513 539 if (miss) 514 540 { 541 // Flush UPT 542 uint32_t top = reg_UPT_TOP [context]; 543 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 544 545 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; 546 event_state_t event_state = reg_EVENT_STATE [context]; 547 upt_state_t event_top = reg_UPDATE_PREDICTION_TABLE [context][top]._state; 548 bool previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 (event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or 550 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 551 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT )); 552 553 bool previous_upt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 554 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 555 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 556 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or 557 (event_top == UPDATE_PREDICTION_STATE_END_KO ) or 558 (event_top == UPDATE_PREDICTION_STATE_KO ) 559 // (event_state == EVENT_STATE_WAIT_END_EVENT ) or 560 // ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and 561 // (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) 562 ); 563 // bool update_ras = (new_update != depth); 564 565 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 566 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 567 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 568 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event); 569 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event); 570 515 571 // Have a miss !!! 516 572 // Flush UPFT 517 flush_UFPT [context] = true;573 flush_UFPT [context] = not previous_ufpt_event; 518 574 519 // Flush UPT520 uint32_t top = reg_UPT_TOP [context];521 uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;522 523 Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;524 event_state_t event_state = reg_EVENT_STATE [context];525 bool previous_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or526 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or527 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or528 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or529 ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and530 (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)));531 // bool update_ras = (new_update != depth);532 533 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);534 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);535 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras);536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_event : %d",previous_event);537 538 575 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) 539 576 { … … 541 578 j!=top; 542 579 j=(j+1)%_param->_size_upt_queue[context]) 543 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 580 { 581 reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; 582 reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; 583 } 544 584 545 585 … … 548 588 // reg_UPT_TOP_EVENT [context] = top; 549 589 550 if (not previous_ event)590 if (not previous_upt_event) 551 591 { 552 592 reg_UPT_TOP_EVENT [context] = top; … … 556 596 { 557 597 // Have event. Top index this slot 558 559 switch (reg_UPDATE_PREDICTION_TABLE [context][top]._state) 598 reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false; 599 600 switch (event_top) 560 601 { 561 602 case UPDATE_PREDICTION_STATE_END_KO : … … 573 614 default : 574 615 { 616 // reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT; 617 // break; 618 575 619 #ifdef DEBUG_TEST 576 620 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); … … 585 629 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth); 586 630 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; 587 588 if (reg_UFPT_NB_NEED_UPDATE [context] > 0) 631 632 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]); 633 634 if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or 635 (reg_UFPT_NB_UPDATE [context] > 0)) 589 636 { 590 637 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context); … … 736 783 uint32_t bottom = reg_UPT_BOTTOM [i]; 737 784 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 738 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]);739 785 // bool empty = reg_UPT_EMPTY [i]; 740 786 … … 749 795 (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 750 796 751 bool find = false; // have slot to update ??? 797 bool find = false; // have slot to update ??? 798 Tdepth_t depth_new = depth; 752 799 753 800 // flush all slot after the event … … 760 807 find = true; 761 808 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 762 } 809 reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false; 810 } 811 else 812 if (not find) // while state == end or empty 813 depth_new ++; 763 814 764 815 if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and … … 767 818 find = true; 768 819 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 820 reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false; 821 769 822 } 823 else 824 // while state == end or empty 825 depth = (depth_new+1)%_param->_size_upt_queue[i]; 770 826 771 827 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 828 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new); 772 829 773 830 // Test if have update slot 774 831 if (find) 775 832 { 776 // flush all slot after the event777 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];778 j!=top;779 j=(j+1)%_param->_size_upt_queue[i])780 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;781 782 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;833 // // flush all slot after the event 834 // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 835 // j!=top; 836 // j=(j+1)%_param->_size_upt_queue[i]) 837 // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 838 839 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 783 840 784 841 // reg_UPT_BOTTOM [i]; … … 791 848 } 792 849 793 bool update_ras = find and ((top != depth) or full); 850 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 851 bool update_ras = find and ((top != depth) or full); 794 852 795 853 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); … … 807 865 reg_EVENT_UPT_PTR [i] = depth; 808 866 809 if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 867 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 868 // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 869 if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or 870 (reg_UFPT_NB_UPDATE [i] > 0)) 810 871 { 811 872 if (update_ras) … … 871 932 if (reg_UFPT_NB_NEED_UPDATE [i] == 0) 872 933 { 873 874 934 // No entry need prediction, flush all entry -> Reset 875 935 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) … … 881 941 else 882 942 { 943 uint32_t bottom = reg_UFPT_BOTTOM [i]; 883 944 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 884 // EMPTY : no event 885 // END : already update 886 // EVENT : previous event 887 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) 888 { 889 reg_UFPT_NB_UPDATE [i] ++; 890 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 891 } 892 893 // TOP is next write slot : last slot is TOP-1 894 uint32_t top = reg_UFPT_TOP [i]; 895 reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; 945 { 946 uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i]; 947 // EMPTY : no event 948 // END : already update 949 // EVENT : previous event 950 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) 951 { 952 reg_UFPT_UPDATE [i] = index; 953 reg_UFPT_NB_UPDATE [i] ++; 954 reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT; 955 } 956 } 957 958 // // TOP is next write slot : last slot is TOP-1 959 // uint32_t top = reg_UFPT_TOP [i]; 960 // reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1; 896 961 897 962 // reg_UFPT_BOTTOM [i];
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