Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp

Timestamp:

Mar 18, 2009, 11:36:26 PM (15 years ago)

Author:

rosiere

Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp (modified) (6 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp

@@ -56 +56 @@
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
       
       ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL         ,VAL);
@@ -65 +65 @@
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA       ,"wdata"    ,Tdcache_data_t       ,_param->_size_data);
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE        ,"type"     ,Tdcache_type_t       ,_param->_size_dcache_type);
+
+      ALLOC1_INTERFACE_END(param->_nb_dcache_port);
     }
                                                                             
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
     {
-      ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
 
       ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL         ,VAL);
@@ -77 +79 @@
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA       ,"rdata"    ,Tdcache_data_t       ,_param->_size_data);
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR       ,"error"    ,Tdcache_error_t      ,_param->_size_dcache_error);
+
+      ALLOC1_INTERFACE_END(_param->_nb_dcache_port);
     }
 
     // ~~~~~[ Interface "lsq_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC3_INTERFACE("lsq_req", IN, SOUTH, _("Request from load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
+      ALLOC3_INTERFACE_BEGIN("lsq_req", IN, SOUTH, _("Request from load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
 
       _ALLOC3_VALACK_IN ( in_LSQ_REQ_VAL            ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
@@ -90 +94 @@
       _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_WDATA          ,"wdata"    ,Tdcache_data_t       ,_param->_size_data                , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
       _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_TYPE           ,"type"     ,Tdcache_type_t       ,_param->_size_dcache_type         , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
+
+      ALLOC3_INTERFACE_END(_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
     }
 
     // ~~~~~[ Interface "lsq_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC3_INTERFACE("lsq_rsp",OUT, SOUTH, _("Respons to load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
+      ALLOC3_INTERFACE_BEGIN("lsq_rsp",OUT, SOUTH, _("Respons to load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
       
       _ALLOC3_VALACK_OUT(out_LSQ_RSP_VAL            ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
@@ -102 +108 @@
       _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_RDATA          ,"rdata"    ,Tdcache_data_t       ,_param->_size_data                , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
       _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_ERROR          ,"error"    ,Tdcache_error_t      ,_param->_size_dcache_error       , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
+
+      ALLOC3_INTERFACE_END(_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]);
     }
 
@@ -108 +116 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-        _internal_DCACHE_REQ_NB_ACCESS         = new uint32_t [_param->_nb_dcache_port];
-        _internal_DCACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_dcache_port];
+        ALLOC1(_internal_DCACHE_REQ_NB_ACCESS        ,uint32_t,_param->_nb_dcache_port);
+        ALLOC1(_internal_DCACHE_REQ_NB_ACCESS_CONFLIT,uint32_t,_param->_nb_dcache_port);
       }
 #endif