Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp

Timestamp:

Mar 18, 2009, 11:36:26 PM (15 years ago)

Author:

rosiere

Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (modified) (7 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp

@@ -55 +55 @@
     // ~~~~~[ Interface "execute_loop_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      {
-       ALLOC1_INTERFACE("execute_loop_in", IN, EAST, "Operation's Input", _param->_nb_read_unit);
+       ALLOC1_INTERFACE_BEGIN("execute_loop_in", IN, EAST, "Operation's Input", _param->_nb_read_unit);
 
        ALLOC1_VALACK_IN ( in_EXECUTE_LOOP_IN_VAL,VAL);
@@ -66 +66 @@
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type);         
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr);
-       if (_param->_have_port_load_queue_ptr)
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr);
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1);
@@ -80 +79 @@
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1);
        ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RE           ,"num_reg_re"           ,Tspecial_address_t,_param->_size_special_register);
+
+       ALLOC1_INTERFACE_END(param->_nb_read_unit);
      }
     // ~~~~~[ Interface "execute_loop_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      {
-       ALLOC1_INTERFACE("execute_loop_out",OUT, EAST, "Operation's Output", _param->_nb_write_unit);
+       ALLOC1_INTERFACE_BEGIN("execute_loop_out",OUT, EAST, "Operation's Output", _param->_nb_write_unit);
 
        ALLOC1_VALACK_OUT(out_EXECUTE_LOOP_OUT_VAL,VAL);
@@ -98 +99 @@
        ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS      ,"address"      ,Taddress_t     ,_param->_size_instruction_address);
        ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_DATA         ,"data"         ,Tgeneral_data_t,_param->_size_general_data);
+
+       ALLOC1_INTERFACE_END(_param->_nb_write_unit);
      }
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      {
-       ALLOC2_INTERFACE("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
+       ALLOC2_INTERFACE_BEGIN("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
        
        _ALLOC2_VALACK_OUT(out_DCACHE_REQ_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
@@ -110 +113 @@
        _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_TYPE      ,"type"      ,Tdcache_type_t   ,_param->_size_dcache_type          , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
        _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_WDATA     ,"wdata"     ,Tdcache_data_t   ,_param->_size_general_data         , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
+
+       ALLOC2_INTERFACE_END(_param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
      }
+
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      {
-       ALLOC2_INTERFACE("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
+       ALLOC2_INTERFACE_BEGIN("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
 
        _ALLOC2_VALACK_IN ( in_DCACHE_RSP_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
@@ -121 +127 @@
        _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_RDATA     ,"rdata"     ,Tdcache_data_t ,_param->_size_general_data         , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
        _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_ERROR     ,"error"     ,Tdcache_error_t,_param->_size_dcache_error         , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
+
+       ALLOC2_INTERFACE_END(_param->_nb_load_store_unit, _param->_nb_cache_port[it1]);
      }
+
     // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      {
-       ALLOC2_INTERFACE("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
+       ALLOC2_INTERFACE_BEGIN("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
        
        _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
@@ -133 +142 @@
        _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE    ,"re_use"    ,Tcontrol_t        ,1                             ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
        _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
+
+       ALLOC2_INTERFACE_END(_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]);
      }
+
 //     // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 //      {