Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
r88 r112 47 47 ,IN 48 48 ,SOUTH, 49 "Generalist interface"49 _("Generalist interface") 50 50 #endif 51 51 ); … … 57 57 // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 58 { 59 ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request.")); 60 61 ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); 62 ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); 63 //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); 64 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); 65 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); 66 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); 59 ALLOC0_INTERFACE_BEGIN("icache_req",OUT, WEST, _("Instruction cache request.")); 60 61 ALLOC0_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); 62 ALLOC0_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); 63 //ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); 64 ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); 65 ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); 66 ALLOC0_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); 67 68 ALLOC0_INTERFACE_END(); 67 69 } 68 70 69 71 // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 72 { 71 ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons.")); 72 73 ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); 74 ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); 75 //ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); 76 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); 77 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); 78 } 79 { 80 ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); 73 ALLOC0_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons.")); 74 75 ALLOC0_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); 76 ALLOC0_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); 77 //ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); 78 ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); 79 ALLOC0_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); 80 81 ALLOC0_INTERFACE_END(); 82 } 83 { 84 ALLOC1_INTERFACE_BEGIN("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); 81 85 82 86 ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); 87 88 ALLOC1_INTERFACE_END(_param->_nb_instruction); 83 89 } 84 90 85 91 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 92 { 87 ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc.")); 88 89 ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); 90 ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); 91 ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); 92 ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); 93 ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); 94 ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); 95 ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); 96 ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 97 ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 98 ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 99 } 100 { 101 ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); 93 ALLOC0_INTERFACE_BEGIN("predict",OUT, NORTH, _("Predict the next pc.")); 94 95 ALLOC0_VALACK_OUT (out_PREDICT_VAL ,VAL); 96 ALLOC0_VALACK_IN ( in_PREDICT_ACK ,ACK); 97 ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); 98 ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); 99 ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); 100 ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); 101 ALLOC0_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); 102 ALLOC0_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 103 ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 104 ALLOC0_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 105 106 ALLOC0_INTERFACE_END(); 107 } 108 { 109 ALLOC1_INTERFACE_BEGIN("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); 102 110 103 111 ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); 112 113 ALLOC1_INTERFACE_END(_param->_nb_instruction); 104 114 } 105 115 106 116 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 107 117 { 108 ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit.")); 109 110 //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 111 ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 112 ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 113 ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 114 ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 115 ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 116 } 117 { 118 ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); 118 ALLOC0_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit.")); 119 120 //ALLOC0_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 121 ALLOC0_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 122 ALLOC0_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 123 ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 124 ALLOC0_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 125 ALLOC0_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 126 127 ALLOC0_INTERFACE_END(); 128 } 129 { 130 ALLOC1_INTERFACE_BEGIN("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); 119 131 120 132 ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); 121 133 ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK); 122 134 ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction); 135 136 ALLOC1_INTERFACE_END(_param->_nb_instruction); 123 137 } 124 138 125 139 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 126 140 { 127 ALLOC_INTERFACE("event",IN , NORTH, _("Event interface.")); 128 129 ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); 130 ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); 131 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 132 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); 133 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); 134 ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); 141 ALLOC0_INTERFACE_BEGIN("event",IN , NORTH, _("Event interface.")); 142 143 ALLOC0_VALACK_IN ( in_EVENT_VAL ,VAL); 144 ALLOC0_VALACK_OUT(out_EVENT_ACK ,ACK); 145 ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 146 ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); 147 ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); 148 ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); 149 150 ALLOC0_INTERFACE_END(); 135 151 } 136 152 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 27 28 delete in_NRESET; 28 29 29 delete out_ICACHE_REQ_VAL ; 30 delete in_ICACHE_REQ_ACK ; 31 //delete out_ICACHE_REQ_THREAD_ID ; 32 if (_param->_have_port_ifetch_queue_ptr) 33 delete out_ICACHE_REQ_PACKET_ID ; 34 delete out_ICACHE_REQ_ADDRESS ; 35 delete out_ICACHE_REQ_TYPE ; 30 DELETE0_SIGNAL(out_ICACHE_REQ_VAL ,1); 31 DELETE0_SIGNAL( in_ICACHE_REQ_ACK ,1); 32 // DELETE0_SIGNAL(out_ICACHE_REQ_THREAD_ID,_param->_size_context_id ); 33 DELETE0_SIGNAL(out_ICACHE_REQ_PACKET_ID,_param->_size_ifetch_queue_ptr ); 34 DELETE0_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_size_instruction_address ); 35 DELETE0_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_size_icache_type); 36 36 37 delete in_ICACHE_RSP_VAL ; 38 delete out_ICACHE_RSP_ACK ; 39 //delete in_ICACHE_RSP_THREAD_ID ; 40 if (_param->_have_port_ifetch_queue_ptr) 41 delete in_ICACHE_RSP_PACKET_ID ; 42 delete [] in_ICACHE_RSP_INSTRUCTION ; 43 delete in_ICACHE_RSP_ERROR ; 37 DELETE0_SIGNAL( in_ICACHE_RSP_VAL ,1); 38 DELETE0_SIGNAL(out_ICACHE_RSP_ACK ,1); 39 // DELETE0_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_size_context_id ); 40 DELETE0_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_size_ifetch_queue_ptr ); 41 DELETE0_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_size_icache_error); 42 DELETE1_SIGNAL( in_ICACHE_RSP_INSTRUCTION,_param->_size_instruction,_param->_nb_instruction); 44 43 45 delete out_PREDICT_VAL ; 46 delete in_PREDICT_ACK ; 47 delete out_PREDICT_PC_PREVIOUS ; 48 delete out_PREDICT_PC_CURRENT ; 49 delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; 50 delete in_PREDICT_PC_NEXT ; 51 delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; 52 delete [] in_PREDICT_INSTRUCTION_ENABLE ; 53 if (_param->_have_port_inst_ifetch_ptr) 54 delete in_PREDICT_INST_IFETCH_PTR ; 55 delete in_PREDICT_BRANCH_STATE ; 56 if (_param->_have_port_depth) 57 delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; 44 DELETE0_SIGNAL(out_PREDICT_VAL ,1); 45 DELETE0_SIGNAL( in_PREDICT_ACK ,1); 46 DELETE0_SIGNAL(out_PREDICT_PC_PREVIOUS ,_param->_size_instruction_address); 47 DELETE0_SIGNAL(out_PREDICT_PC_CURRENT ,_param->_size_instruction_address); 48 DELETE0_SIGNAL(out_PREDICT_PC_CURRENT_IS_DS_TAKE ,1); 49 DELETE0_SIGNAL( in_PREDICT_PC_NEXT ,_param->_size_instruction_address); 50 DELETE0_SIGNAL( in_PREDICT_PC_NEXT_IS_DS_TAKE ,1); 51 DELETE0_SIGNAL( in_PREDICT_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); 52 DELETE0_SIGNAL( in_PREDICT_BRANCH_STATE ,_param->_size_branch_state); 53 DELETE0_SIGNAL( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); 54 DELETE1_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ,1,_param->_nb_instruction); 58 55 59 delete [] out_DECOD_VAL ; 60 delete [] in_DECOD_ACK ; 61 delete [] out_DECOD_INSTRUCTION ; 62 //delete out_DECOD_CONTEXT_ID ; 63 delete out_DECOD_ADDRESS ; 64 if (_param->_have_port_inst_ifetch_ptr) 65 delete out_DECOD_INST_IFETCH_PTR ; 66 delete out_DECOD_BRANCH_STATE ; 67 if (_param->_have_port_depth) 68 delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; 69 delete out_DECOD_EXCEPTION ; 56 // DELETE0_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_size_context_id); 57 DELETE0_SIGNAL(out_DECOD_ADDRESS ,_param->_size_instruction_address); 58 DELETE0_SIGNAL(out_DECOD_INST_IFETCH_PTR ,_param->_size_inst_ifetch_ptr); 59 DELETE0_SIGNAL(out_DECOD_BRANCH_STATE ,_param->_size_branch_state); 60 DELETE0_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_size_depth); 61 DELETE0_SIGNAL(out_DECOD_EXCEPTION ,_param->_size_exception_ifetch); 62 DELETE1_SIGNAL(out_DECOD_VAL ,1,_param->_nb_instruction); 63 DELETE1_SIGNAL( in_DECOD_ACK ,1,_param->_nb_instruction); 64 DELETE1_SIGNAL(out_DECOD_INSTRUCTION ,_param->_size_instruction,_param->_nb_instruction); 70 65 71 delete in_EVENT_VAL;72 delete out_EVENT_ACK;73 delete in_EVENT_ADDRESS;74 delete in_EVENT_ADDRESS_NEXT;75 delete in_EVENT_ADDRESS_NEXT_VAL;76 delete in_EVENT_IS_DS_TAKE;66 DELETE0_SIGNAL( in_EVENT_VAL ,1); 67 DELETE0_SIGNAL(out_EVENT_ACK ,1); 68 DELETE0_SIGNAL( in_EVENT_ADDRESS ,_param->_size_instruction_address); 69 DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_size_instruction_address); 70 DELETE0_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,1); 71 DELETE0_SIGNAL( in_EVENT_IS_DS_TAKE ,1); 77 72 } 73 78 74 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 79 75 delete _component_address_management;
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