Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table
- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
r111 r112 126 126 ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update); 127 127 ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update); 128 ALLOC1_SC_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,"out_UPDATE_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); 128 129 ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update); 129 130 ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update); … … 137 138 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update); 138 139 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); 139 ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);140 140 141 141 ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); … … 223 223 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update); 224 224 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update); 225 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update); 225 226 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update); 226 227 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update); … … 235 236 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update); 236 237 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); 237 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);238 238 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); 239 239 INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); … … 575 575 TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); 576 576 TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); 577 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 577 578 TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); 578 579 if (update_btb(it_upt->condition)) … … 593 594 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 594 595 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 595 TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);596 596 } 597 597 ++ it_upt; … … 906 906 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 907 907 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 908 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);908 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 909 909 } 910 910 ++ it_upt; … … 1281 1281 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1282 1282 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1283 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);1283 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1284 1284 } 1285 1285 } … … 1353 1353 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1354 1354 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1355 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);1355 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1356 1356 } 1357 1357 ++ it_upt; … … 1888 1888 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 1889 1889 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 1890 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);1890 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 1891 1891 } 1892 1892 } … … 1976 1976 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 1977 1977 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 1978 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);1978 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 1979 1979 } 1980 1980 … … 2103 2103 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2104 2104 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2105 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2105 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2106 2106 } 2107 2107 … … 2544 2544 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address); 2545 2545 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index); 2546 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_ufpt->miss_ifetch);2546 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch); 2547 2547 } 2548 2548 } … … 2637 2637 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2638 2638 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2639 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2639 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2640 2640 } 2641 2641 // -- it_upt; … … 2763 2763 TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address); 2764 2764 TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index); 2765 TEST(Tcontrol_t ,out_UPDATE_ RAS_PREDICTION_IFETCH[port]->read(),not it_upt->miss_ifetch);2765 TEST(Tcontrol_t ,out_UPDATE_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch); 2766 2766 } 2767 2767 … … 2870 2870 delete [] out_UPDATE_MISS_PREDICTION ; 2871 2871 delete [] out_UPDATE_DIRECTION_GOOD ; 2872 delete [] out_UPDATE_PREDICTION_IFETCH ; 2872 2873 delete [] out_UPDATE_BTB_VAL ; 2873 2874 delete [] out_UPDATE_BTB_ADDRESS_SRC ; … … 2881 2882 delete [] out_UPDATE_RAS_ADDRESS ; 2882 2883 delete [] out_UPDATE_RAS_INDEX ; 2883 delete [] out_UPDATE_RAS_PREDICTION_IFETCH;2884 2884 2885 2885 DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h
r111 r112 88 88 public : Tcontrol_t _ifetch_prediction; // not in ufpt 89 89 90 // to branchement_log_file 90 91 public : bool _retire_ok ; 92 public : bool _miss_prediction ; 91 93 }; 92 94 … … 115 117 #define pop_ras(cond) ((cond == BRANCH_CONDITION_READ_STACK )) 116 118 117 #define need_update(cond) update_ras(cond)119 #define need_update(cond) (update_ras(cond) or update_dir(cond)) 118 120 119 121 }; // end namespace update_prediction_table -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
r111 r112 130 130 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_MISS_PREDICTION ; //[nb_inst_update] 131 131 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIRECTION_GOOD ; //[nb_inst_update] 132 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_PREDICTION_IFETCH ; //[nb_inst_update] 132 133 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_BTB_VAL ; //[nb_inst_update] 133 134 public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_SRC ; //[nb_inst_update] … … 141 142 public : SC_OUT(Taddress_t ) ** out_UPDATE_RAS_ADDRESS ; //[nb_inst_update] 142 143 public : SC_OUT(Tptr_t ) ** out_UPDATE_RAS_INDEX ; //[nb_inst_update] 143 public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PREDICTION_IFETCH ; //[nb_inst_update]144 144 145 145 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 183 183 private : bool * reg_EVENT_VAL ; //[nb_context] 184 184 private : uint32_t * reg_EVENT_UPT_PTR ; //[nb_context] 185 private : bool * reg_EVENT_UPT_FULL ; //[nb_context] 185 186 186 187 private : event_state_t * reg_EVENT_STATE ; //[nb_context] 187 private : event_source_t * reg_EVENT_SOURCE; //[nb_context]188 private : bool * reg_EVENT_IS_BRANCH ; //[nb_context] 188 189 private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] 189 190 private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r111 r112 48 48 ,IN 49 49 ,SOUTH, 50 "Generalist interface"50 _("Generalist interface") 51 51 #endif 52 52 ); … … 58 58 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 59 { 60 ALLOC1_INTERFACE ("predict", IN,SOUTH, "predict", _param->_nb_inst_predict);60 ALLOC1_INTERFACE_BEGIN("predict", IN,SOUTH, _("predict"), _param->_nb_inst_predict); 61 61 62 62 ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); … … 72 72 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 73 73 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 74 75 ALLOC1_INTERFACE_END(_param->_nb_inst_predict); 74 76 } 75 77 76 78 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 79 { 78 ALLOC1_INTERFACE ("decod", IN,SOUTH, "decod", _param->_nb_inst_decod);80 ALLOC1_INTERFACE_BEGIN("decod", IN,SOUTH, _("decod"), _param->_nb_inst_decod); 79 81 80 82 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); … … 93 95 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 94 96 ALLOC1_SIGNAL_OUT(out_DECOD_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1); 97 98 ALLOC1_INTERFACE_END(_param->_nb_inst_decod); 95 99 } 96 100 97 101 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 98 102 { 99 ALLOC1_INTERFACE ("branch_complete", IN,SOUTH, "branch_complete", _param->_nb_inst_branch_complete);103 ALLOC1_INTERFACE_BEGIN("branch_complete", IN,SOUTH, _("branch_complete"), _param->_nb_inst_branch_complete); 100 104 101 105 ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL ,VAL); … … 109 113 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); 110 114 // ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 115 116 ALLOC1_INTERFACE_END(_param->_nb_inst_branch_complete); 111 117 } 112 118 113 119 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 120 { 115 ALLOC1_INTERFACE ("branch_event", IN,SOUTH, "branch_event", _param->_nb_context);121 ALLOC1_INTERFACE_BEGIN("branch_event", IN,SOUTH, _("branch_event"), _param->_nb_context); 116 122 117 123 ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); … … 123 129 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); 124 130 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 131 132 ALLOC1_INTERFACE_END(_param->_nb_context); 125 133 } 126 134 127 135 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 128 136 { 129 ALLOC1_INTERFACE ("update",OUT,SOUTH, "update", _param->_nb_inst_update);137 ALLOC1_INTERFACE_BEGIN("update",OUT,SOUTH, "update", _param->_nb_inst_update); 130 138 131 139 ALLOC1_VALACK_OUT(out_UPDATE_VAL ,VAL); … … 134 142 ALLOC1_SIGNAL_OUT(out_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); 135 143 ALLOC1_SIGNAL_OUT(out_UPDATE_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); 144 ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTION_IFETCH ,"prediction_ifetch" ,Tcontrol_t ,1); 136 145 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); 137 146 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); … … 145 154 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 146 155 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 147 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); 156 157 ALLOC1_INTERFACE_END(_param->_nb_inst_update); 148 158 } 149 159 150 160 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 151 161 { 152 ALLOC1_INTERFACE ("event", IN,SOUTH,"event", _param->_nb_context);162 ALLOC1_INTERFACE_BEGIN("event", IN,SOUTH,_("event"), _param->_nb_context); 153 163 154 164 ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); … … 156 166 ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); 157 167 ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); 168 169 ALLOC1_INTERFACE_END(_param->_nb_context); 158 170 } 159 171 160 172 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 161 173 { 162 ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); 174 ALLOC1_INTERFACE_BEGIN("depth",OUT,SOUTH, _("depth"), _param->_nb_context); 175 163 176 ALLOC1_SIGNAL_OUT(out_DEPTH_VAL ,"VAL" ,Tcontrol_t,1); 164 177 ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t ,_param->_size_depth); … … 166 179 ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth); 167 180 ALLOC1_SIGNAL_OUT(out_DEPTH_FULL ,"FULL" ,Tcontrol_t,1); 181 182 ALLOC1_INTERFACE_END(_param->_nb_context); 168 183 } 169 184 … … 209 224 ALLOC1(reg_EVENT_VAL ,bool ,_param->_nb_context); 210 225 ALLOC1(reg_EVENT_UPT_PTR ,uint32_t ,_param->_nb_context); 226 ALLOC1(reg_EVENT_UPT_FULL ,bool ,_param->_nb_context); 211 227 212 228 ALLOC1(reg_EVENT_STATE ,event_state_t ,_param->_nb_context); 213 ALLOC1(reg_EVENT_ SOURCE ,event_source_t,_param->_nb_context);229 ALLOC1(reg_EVENT_IS_BRANCH ,bool ,_param->_nb_context); 214 230 ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 215 231 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r111 r112 29 29 delete in_NRESET; 30 30 31 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 delete [] in_PREDICT_VAL ; 33 delete [] out_PREDICT_ACK ; 34 if (_param->_have_port_context_id) 35 delete [] in_PREDICT_CONTEXT_ID ; 36 delete [] in_PREDICT_BTB_ADDRESS_SRC ; 37 delete [] in_PREDICT_BTB_ADDRESS_DEST ; 38 delete [] in_PREDICT_BTB_CONDITION ; 39 delete [] in_PREDICT_BTB_LAST_TAKE ; 40 delete [] in_PREDICT_BTB_IS_ACCURATE ; 41 if (_param->_have_port_history) 42 delete [] in_PREDICT_DIR_HISTORY ; 43 delete [] in_PREDICT_RAS_ADDRESS ; 44 delete [] in_PREDICT_RAS_INDEX ; 45 if (_param->_have_port_depth) 46 delete [] out_PREDICT_UPDATE_PREDICTION_ID; 47 48 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 49 delete [] in_DECOD_VAL ; 50 delete [] out_DECOD_ACK ; 51 if (_param->_have_port_context_id) 52 delete [] in_DECOD_CONTEXT_ID ; 53 delete [] in_DECOD_BTB_ADDRESS_SRC ; 54 delete [] in_DECOD_BTB_ADDRESS_DEST ; 55 delete [] in_DECOD_BTB_CONDITION ; 56 delete [] in_DECOD_BTB_LAST_TAKE ; 57 delete [] in_DECOD_RAS_ADDRESS ; 58 delete [] in_DECOD_RAS_INDEX ; 59 delete [] in_DECOD_MISS_IFETCH ; 60 delete [] in_DECOD_MISS_DECOD ; 61 if (_param->_have_port_depth) 62 delete [] in_DECOD_UPDATE_PREDICTION_ID ; 63 // if (_param->_have_port_depth) 64 // delete [] out_DECOD_DEPTH ; 65 delete [] in_DECOD_IS_ACCURATE ; 66 delete [] out_DECOD_CAN_CONTINUE ; 67 68 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 69 delete [] in_BRANCH_COMPLETE_VAL ; 70 delete [] out_BRANCH_COMPLETE_ACK ; 71 if (_param->_have_port_context_id) 72 delete [] in_BRANCH_COMPLETE_CONTEXT_ID ; 73 if (_param->_have_port_depth) 74 delete [] in_BRANCH_COMPLETE_DEPTH ; 75 delete [] in_BRANCH_COMPLETE_ADDRESS ; 76 delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; 77 delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; 78 // delete [] out_BRANCH_COMPLETE_TAKE ; 79 // delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ; 80 // delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ; 31 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); 33 DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); 34 DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); 35 DELETE1_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID,_param->_nb_inst_predict,_param->_size_depth); 36 DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict,_param->_size_instruction_address); 37 DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict,_param->_size_instruction_address); 38 DELETE1_SIGNAL( in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict,_param->_size_branch_condition); 39 DELETE1_SIGNAL( in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict,1); 40 DELETE1_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict,1); 41 DELETE1_SIGNAL( in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict,_param->_size_history); 42 DELETE1_SIGNAL( in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict,_param->_size_instruction_address); 43 DELETE1_SIGNAL( in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict,_param->_max_size_ras_index); 44 45 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 46 DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); 47 DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); 48 DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); 49 DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address); 50 DELETE1_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address); 51 DELETE1_SIGNAL( in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); 52 DELETE1_SIGNAL( in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod,1); 53 DELETE1_SIGNAL( in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address); 54 DELETE1_SIGNAL( in_DECOD_RAS_INDEX ,_param->_nb_inst_decod,_param->_max_size_ras_index); 55 DELETE1_SIGNAL( in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod,1); 56 DELETE1_SIGNAL( in_DECOD_MISS_DECOD ,_param->_nb_inst_decod,1); 57 DELETE1_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth); 58 // DELETE1_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod,_param->_size_depth); 59 DELETE1_SIGNAL( in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod,1); 60 DELETE1_SIGNAL(out_DECOD_CAN_CONTINUE ,_param->_nb_inst_decod,1); 61 62 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 63 DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); 64 DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); 65 DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); 66 DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); 67 DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 68 DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); 69 DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); 70 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); 71 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 72 // DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); 81 73 82 74 // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 90 82 DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); 91 83 92 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 93 delete [] out_UPDATE_VAL ; 94 delete [] in_UPDATE_ACK ; 95 if (_param->_have_port_context_id) 96 delete [] out_UPDATE_CONTEXT_ID ; 97 delete [] out_UPDATE_MISS_PREDICTION ; 98 delete [] out_UPDATE_DIRECTION_GOOD ; 99 delete [] out_UPDATE_BTB_VAL ; 100 delete [] out_UPDATE_BTB_ADDRESS_SRC ; 101 delete [] out_UPDATE_BTB_ADDRESS_DEST ; 102 delete [] out_UPDATE_BTB_CONDITION ; 103 delete [] out_UPDATE_DIR_VAL ; 104 if (_param->_have_port_history) 105 delete [] out_UPDATE_DIR_HISTORY ; 106 delete [] out_UPDATE_RAS_VAL ; 107 delete [] out_UPDATE_RAS_FLUSH ; 108 delete [] out_UPDATE_RAS_PUSH ; 109 delete [] out_UPDATE_RAS_ADDRESS ; 110 delete [] out_UPDATE_RAS_INDEX ; 111 delete [] out_UPDATE_RAS_PREDICTION_IFETCH; 84 // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 85 DELETE1_SIGNAL(out_UPDATE_VAL ,_param->_nb_inst_update,1); 86 DELETE1_SIGNAL( in_UPDATE_ACK ,_param->_nb_inst_update,1); 87 DELETE1_SIGNAL(out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); 88 DELETE1_SIGNAL(out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update,1); 89 DELETE1_SIGNAL(out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update,1); 90 DELETE1_SIGNAL(out_UPDATE_PREDICTION_IFETCH ,_param->_nb_inst_update,1); 91 DELETE1_SIGNAL(out_UPDATE_BTB_VAL ,_param->_nb_inst_update,1); 92 DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update,_param->_size_instruction_address); 93 DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update,_param->_size_instruction_address); 94 DELETE1_SIGNAL(out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update,_param->_size_branch_condition); 95 DELETE1_SIGNAL(out_UPDATE_DIR_VAL ,_param->_nb_inst_update,1); 96 DELETE1_SIGNAL(out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update,_param->_size_history); 97 DELETE1_SIGNAL(out_UPDATE_RAS_VAL ,_param->_nb_inst_update,1); 98 DELETE1_SIGNAL(out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update,1); 99 DELETE1_SIGNAL(out_UPDATE_RAS_PUSH ,_param->_nb_inst_update,1); 100 DELETE1_SIGNAL(out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); 101 DELETE1_SIGNAL(out_UPDATE_RAS_INDEX ,_param->_nb_inst_update,_param->_max_size_ras_index); 112 102 113 103 // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 162 152 DELETE1(reg_EVENT_VAL ,_param->_nb_context); 163 153 DELETE1(reg_EVENT_UPT_PTR ,_param->_nb_context); 154 DELETE1(reg_EVENT_UPT_FULL ,_param->_nb_context); 164 155 165 156 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 166 DELETE1(reg_EVENT_ SOURCE,_param->_nb_context);157 DELETE1(reg_EVENT_IS_BRANCH ,_param->_nb_context); 167 158 DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); 168 159 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r111 r112 98 98 Tcontrol_t miss_prediction ; 99 99 Tcontrol_t direction_good ; 100 Tcontrol_t prediction_ifetch ; 100 101 Tcontrol_t btb_val ; 101 102 Taddress_t btb_address_src ; … … 109 110 Taddress_t ras_address ; 110 111 Tptr_t ras_index ; 111 Tcontrol_t ras_prediction_ifetch;112 112 113 113 // Test if update fetch prediction table need update port … … 133 133 miss_prediction = 1; 134 134 // direction_good = ; 135 prediction_ifetch = 1; 135 136 btb_val = 0; // don't update btb (is update by the event branch) 136 // btb_address_src = ;137 // btb_address_dest = ;138 // btb_condition = ;139 dir_val = 0; // don't update btb (is update by the event branch (if conditionnal branch))140 // dir_history =;137 // btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 138 // btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 139 // btb_condition = condition; 140 dir_val = update_ras(condition); 141 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history; 141 142 // repop/ repush data -> don't corrupt ras 142 143 ras_val = update_ras(condition); … … 145 146 ras_address = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras; 146 147 ras_index = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._index_ras; 147 ras_prediction_ifetch = 1;148 148 149 149 internal_UPDATE_FROM_UFPT [i] = true; … … 200 200 miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); 201 201 direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; 202 prediction_ifetch = ifetch; 202 203 btb_val = state_is_ok_ko and update_btb(condition); 203 204 btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 204 205 btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 205 206 btb_condition = condition; 206 dir_val = state_is_ok_ko and update_dir(condition) and ifetch; // if not ifetch, then static prediction 207 dir_val = // state_is_ok_ko and 208 update_dir(condition); // if not ifetch, then static prediction 207 209 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; 208 210 ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras … … 213 215 ras_address = (ras_flush)?(reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src+2):reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; 214 216 ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; 215 ras_prediction_ifetch = ifetch;216 217 217 218 internal_UPDATE_FROM_UFPT [i] = false; … … 257 258 PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],miss_prediction ); 258 259 PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],direction_good ); 260 PORT_WRITE(out_UPDATE_PREDICTION_IFETCH [i],prediction_ifetch ); 259 261 PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val ); 260 262 PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],btb_address_src ); … … 269 271 PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],ras_address ); 270 272 PORT_WRITE(out_UPDATE_RAS_INDEX [i],ras_index ); 271 PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ras_prediction_ifetch);272 273 } 273 274 } … … 290 291 } 291 292 } 293 else 294 { 295 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 296 { 297 internal_UPDATE_VAL [i] = 0; 298 internal_UPDATE_VAL_WITHOUT_ACK [i] = 0; 299 } 300 for (uint32_t i=0; i<_param->_nb_context; i++) 301 { 302 internal_BRANCH_EVENT_VAL [i] = 0; 303 } 304 } 305 292 306 293 307 log_end(Update_Prediction_Table,FUNCTION); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r111 r112 53 53 reg_EVENT_VAL [i] = false; 54 54 reg_EVENT_STATE [i] = EVENT_STATE_OK; 55 reg_EVENT_IS_BRANCH [i] = true; 55 56 } 56 57 } … … 100 101 // Test if state is end 101 102 // if (end_ok or end_ko) 103 104 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end); 105 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",reg_UPT_BOTTOM [i]); 106 102 107 if (end) 103 108 { … … 108 113 branchement_log_file [num_thread] 109 114 << std::hex 110 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "111 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "115 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " " 116 << "0x" << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " " 112 117 << std::dec 113 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " " 118 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - " 119 << "[" << sc_simulation_time() << "] " << " " 120 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " " 121 << reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " " 122 << "(" << (uint32_t)reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition << ")" 114 123 << std::endl; 115 124 } … … 128 137 // if (bottom = reg_UPT_UPDATE [i]) 129 138 // reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; 130 131 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 139 }// @@@ 140 141 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]); 142 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); 143 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); 144 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL[i]); 145 146 if (reg_EVENT_VAL [i] and (reg_EVENT_UPT_PTR [i] == bottom)) 147 { 148 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); 149 150 if ((reg_EVENT_IS_BRANCH [i] == false) and (reg_EVENT_UPT_FULL [i] == false)) 151 reg_EVENT_STATE[i] = EVENT_STATE_OK; 152 153 if ((reg_EVENT_IS_BRANCH [i] == true) or (reg_EVENT_UPT_FULL [i] == false)) 132 154 { 133 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * END EVENT"); 134 135 reg_EVENT_VAL [i] = false; 136 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 137 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 138 139 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 140 reg_UPT_EMPTY [i] = false; 141 142 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 143 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 144 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 145 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 155 reg_EVENT_VAL [i] = false; 156 // reg_EVENT_IS_BRANCH [i] = true; 157 reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; 158 reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; 159 160 if (reg_UPT_BOTTOM [i] != reg_UPT_TOP [i]) 161 reg_UPT_EMPTY [i] = false; 146 162 } 147 163 164 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 165 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); 166 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 167 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 168 148 169 } 170 171 if (end) 172 reg_EVENT_UPT_FULL [i] = false; 149 173 } 150 174 } … … 245 269 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context); 246 270 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 271 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; 247 272 } 248 273 else … … 251 276 reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT; 252 277 } 253 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UFPT;254 278 255 279 // Flush UPFT 256 280 flush_UFPT [context] = true; 257 281 282 reg_EVENT_IS_BRANCH [context] = true; 258 283 reg_EVENT_DEPTH [context] = upt_ptr_write; 259 284 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State … … 357 382 (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) 358 383 { 359 Tdepth_t depth = internal_UPDATE_DEPTH 384 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 360 385 361 386 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); … … 369 394 // if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) 370 395 if ((--reg_UFPT_NB_UPDATE [context])==0) 371 switch (reg_EVENT_STATE [context]) 372 { 373 case EVENT_STATE_MISS_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; 374 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 375 case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; 376 case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; 377 case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; 378 default : break; 379 } 396 { 397 switch (reg_EVENT_STATE [context]) 398 { 399 case EVENT_STATE_MISS_FLUSH_UFPT : 400 { 401 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 402 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UFPT; 403 404 break; 405 } 406 // impossible to have an update on ufpt and reg_upt_update>reg_upt_top 407 case EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT ; break; 408 case EVENT_STATE_EVENT_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_OK ; break; 409 case EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT: reg_EVENT_STATE [context] = EVENT_STATE_EVENT_FLUSH_UPT; break; 410 default : break; 411 } 412 } 380 413 381 414 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); … … 405 438 { 406 439 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 407 440 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]); 441 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 442 408 443 // Change state 409 444 #ifdef DEBUG_TEST … … 430 465 431 466 if (ok or ko) 432 reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; 467 { 468 reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true; 469 reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko; 470 } 433 471 434 472 // Have an update, test the state to transiste to the good state … … 444 482 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; 445 483 446 reg_EVENT_VAL [context] = true; 447 reg_EVENT_UPT_PTR [context] = depth; 484 reg_EVENT_VAL [context] = true; 485 reg_EVENT_UPT_PTR [context] = depth; 486 // reg_EVENT_UPT_FULL [context] = 0; 487 // reg_EVENT_UPT_FULL [i] = (not reg_UPT_EMPTY [i] and (bottom == reg_UPT_TOP [i])); 488 448 489 449 490 #ifdef STATISTICS … … 473 514 // Update pointer 474 515 // * if update RAS : update pointer is decreaste until it equal at top pointer 516 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]); 517 475 518 if (internal_UPDATE_RAS [i]) 476 519 { 477 520 // if end_event, restart too bottom, else decrease pointer 478 521 bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); 522 523 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event); 524 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]); 479 525 480 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);481 526 if (end_event) 482 527 { 483 // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 528 reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); 529 // reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; 484 530 485 531 if (reg_EVENT_STATE [context] == EVENT_STATE_EVENT_FLUSH_UPT) … … 488 534 } 489 535 else 490 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 536 { 537 reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; 538 // reg_EVENT_SOURCE[context] = EVENT_SOURCE_UPT; 539 } 491 540 } 492 541 else … … 497 546 else 498 547 { 548 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update"); 549 499 550 // increase pointer 500 551 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; … … 502 553 503 554 // Free the branch with no accurate ? 504 if ( 555 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko) 505 556 reg_IS_ACCURATE [context] = true; 557 558 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]); 559 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 506 560 } 507 561 } … … 513 567 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 514 568 } 515 516 569 517 570 // =================================================================== … … 533 586 534 587 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 535 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 536 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 537 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 588 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 589 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 590 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 591 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 538 592 539 593 if (miss) … … 546 600 event_state_t event_state = reg_EVENT_STATE [context]; 547 601 upt_state_t event_top = reg_UPDATE_PREDICTION_TABLE [context][top]._state; 602 603 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_top : %s",toString(event_top).c_str()); 604 548 605 bool previous_ufpt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 549 606 (event_state == EVENT_STATE_MISS_FLUSH_UFPT ) or … … 551 608 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT )); 552 609 553 bool previous_upt_event = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 554 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 555 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 556 (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) or 557 (event_top == UPDATE_PREDICTION_STATE_END_KO ) or 558 (event_top == UPDATE_PREDICTION_STATE_KO ) 559 // (event_state == EVENT_STATE_WAIT_END_EVENT ) or 560 // ((event_state == EVENT_STATE_UPDATE_CONTEXT ) and 561 // (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) 562 ); 610 bool previous_upt_event = (false 611 or (event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) 612 or (event_state == EVENT_STATE_MISS_FLUSH_UPT ) 613 or (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) 614 or (event_state == EVENT_STATE_EVENT_FLUSH_UPT ) 615 or (event_top == UPDATE_PREDICTION_STATE_END_KO ) 616 or (event_top == UPDATE_PREDICTION_STATE_KO ) 617 // or (event_state == EVENT_STATE_WAIT_END_EVENT ) 618 // or ((event_state == EVENT_STATE_UPDATE_CONTEXT ) 619 // and (reg_EVENT_SOURCE [context] == EVENT_SOURCE_UPT)) 620 ); 563 621 // bool update_ras = (new_update != depth); 564 622 … … 568 626 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event); 569 627 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event); 570 628 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]); 629 571 630 // Have a miss !!! 572 631 // Flush UPFT 573 flush_UFPT [context] = not previous_ufpt_event;632 flush_UFPT [context] |= not previous_ufpt_event; 574 633 575 634 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END) … … 587 646 reg_UPT_TOP [context] = depth; 588 647 // reg_UPT_TOP_EVENT [context] = top; 589 648 590 649 if (not previous_upt_event) 591 650 { … … 604 663 // Have already update predictor 605 664 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END; 665 reg_UPT_UPDATE [context] = new_update; 606 666 break; 607 667 } … … 649 709 } 650 710 } 651 reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;711 // reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT; 652 712 653 713 // else no update 654 714 715 reg_EVENT_IS_BRANCH [context] = true; 655 716 reg_EVENT_DEPTH [context] = depth; 656 717 reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State … … 675 736 } 676 737 738 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s",toString(reg_EVENT_STATE [context]).c_str()); 739 677 740 // In all case : update good_take 678 741 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take; … … 686 749 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr; 687 750 } 751 688 752 689 753 // =================================================================== … … 779 843 780 844 // Flush UPT 781 Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; 782 uint32_t top = reg_UPT_TOP [i]; 783 uint32_t bottom = reg_UPT_BOTTOM [i]; 784 uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 785 // bool empty = reg_UPT_EMPTY [i]; 786 845 uint32_t bottom = reg_UPT_BOTTOM [i]; 846 847 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); 848 849 // event_state_t event_state = reg_EVENT_STATE [i]; 850 // bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 851 // (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 852 // (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 853 // (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 854 855 bool find = false; // have slot to update ??? 856 Tdepth_t top = bottom; 857 Tdepth_t update = bottom; 858 bool empty = reg_UPT_EMPTY [i]; 859 860 // flush all slot, because this event is in head of rob 861 for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) 862 { 863 Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i]; 864 865 if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and 866 (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)) 867 { 868 find = true; // find a not empty slot 869 reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT; 870 reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false; 871 update = x; 872 } 873 874 if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY) 875 top = x+1; 876 } 877 878 top = top%_param->_size_upt_queue[i]; 879 880 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 787 881 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 788 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);789 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);790 791 event_state_t event_state = reg_EVENT_STATE [i];792 bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or793 (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or794 (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or795 (event_state == EVENT_STATE_EVENT_FLUSH_UPT));796 797 bool find = false; // have slot to update ???798 Tdepth_t depth_new = depth;799 800 // flush all slot after the event801 for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];802 j!=top;803 j=(j+1)%_param->_size_upt_queue[i])804 if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and805 (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY))806 {807 find = true;808 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;809 reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false;810 }811 else812 if (not find) // while state == end or empty813 depth_new ++;814 815 if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and816 (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY))817 {818 find = true;819 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;820 reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false;821 822 }823 else824 // while state == end or empty825 depth = (depth_new+1)%_param->_size_upt_queue[i];826 827 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);828 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new);829 882 830 883 // Test if have update slot 831 884 if (find) 832 885 { 833 // // flush all slot after the event834 // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i];835 // j!=top;836 // j=(j+1)%_param->_size_upt_queue[i])837 // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT;838 839 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT;840 841 // reg_UPT_BOTTOM [i];842 886 // TODO : special case : event is an exception on branch, also depth is not valid 843 reg_UPT_TOP [i] = depth; // depth is again valid887 reg_UPT_TOP [i] = top; // depth is again valid 844 888 reg_UPT_TOP_EVENT [i] = top; 845 889 … … 847 891 reg_UPT_EMPTY [i] = true; 848 892 } 849 850 bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 851 bool update_ras = find and ((top != depth) or full); 852 853 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 854 855 if (not previous_update_ras and update_ras) 856 reg_UPT_UPDATE [i] = new_update; 893 reg_UPT_UPDATE [i] = update; 857 894 858 895 // new state : … … 862 899 // * ok : nothing 863 900 // * ko : flush upt 864 reg_EVENT_VAL [i] = true; 865 reg_EVENT_UPT_PTR [i] = depth; 866 901 reg_EVENT_VAL [i] = find; 902 reg_EVENT_IS_BRANCH [i] = false; 903 reg_EVENT_UPT_PTR [i] = top; 904 reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i])); 905 reg_EVENT_DEPTH [i] = top; 906 // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 907 // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 908 // reg_EVENT_ADDRESS_DEST [i] = good_addr; 909 910 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); 911 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 912 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]); 913 914 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]); 915 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]); 916 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]); 867 917 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 868 // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 918 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]); 919 869 920 if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or 870 921 (reg_UFPT_NB_UPDATE [i] > 0)) 871 922 { 872 if ( update_ras)923 if (find) 873 924 { 874 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT ( branch_complete - miss)",i);925 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (event - find)",i); 875 926 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; 876 927 } 877 928 else 878 929 { 879 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); 930 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (event - not find)",i); 931 // reg_EVENT_VAL [i] = false; 932 880 933 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; 881 934 } … … 883 936 else 884 937 { 885 // if (not previous_update_ras) 886 if (update_ras) 938 if (find) 887 939 { 888 940 // have ras prediction ? 889 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT ( branch_complete - miss)",i);941 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - find)",i); 890 942 891 943 reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; … … 894 946 { 895 947 // special case : nothing 896 reg_EVENT_VAL [i] = false; 948 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (event - not find)",i); 949 950 // reg_EVENT_VAL [i] = false; 897 951 898 952 reg_EVENT_STATE [i] = EVENT_STATE_OK; … … 902 956 // else no update 903 957 904 reg_EVENT_DEPTH [i] = depth; 905 // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 906 // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 907 // reg_EVENT_ADDRESS_DEST [i] = good_addr; 958 // Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_EVENT_DEPTH [i]):0; 959 // uint32_t top = reg_UPT_TOP [i]; 960 // uint32_t bottom = reg_UPT_BOTTOM [i]; 961 // uint32_t new_update = ((top==0)?_param->_size_upt_queue[i]:top)-1; 962 // // bool empty = reg_UPT_EMPTY [i]; 963 964 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 965 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 966 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); 967 968 // event_state_t event_state = reg_EVENT_STATE [i]; 969 // bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or 970 // (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or 971 // (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or 972 // (event_state == EVENT_STATE_EVENT_FLUSH_UPT)); 973 974 // bool find = false; // have slot to update ??? 975 // Tdepth_t depth_new = depth; 976 977 // // flush all slot, because this event is in head of rob 978 // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 979 // //uint32_t j=bottom; 980 // j!=top; 981 // j=(j+1)%_param->_size_upt_queue[i]) 982 // if ((reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_END) and 983 // (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)) 984 // { 985 // find = true; 986 // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 987 // reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = false; 988 // } 989 // else 990 // if (not find) // while state == end or empty 991 // depth_new ++; 992 993 // if ((reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_END) and 994 // (reg_UPDATE_PREDICTION_TABLE [i][depth]._state != UPDATE_PREDICTION_STATE_EMPTY)) 995 // { 996 // find = true; 997 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 998 // reg_UPDATE_PREDICTION_TABLE [i][depth]._retire_ok = false; 999 1000 // } 1001 // else 1002 // // while state == end or empty 1003 // depth = (depth_new+1)%_param->_size_upt_queue[i]; 1004 1005 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find); 1006 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth_new : %d",depth_new); 1007 1008 // // Test if have update slot 1009 // if (find) 1010 // { 1011 // // // flush all slot after the event 1012 // // for (uint32_t j=(depth+1)%_param->_size_upt_queue[i]; 1013 // // j!=top; 1014 // // j=(j+1)%_param->_size_upt_queue[i]) 1015 // // reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EVENT; 1016 1017 // // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 1018 1019 // // reg_UPT_BOTTOM [i]; 1020 // // TODO : special case : event is an exception on branch, also depth is not valid 1021 // reg_UPT_TOP [i] = depth; // depth is again valid 1022 // reg_UPT_TOP_EVENT [i] = top; 1023 1024 // if (bottom == reg_UPT_TOP [i]) 1025 // reg_UPT_EMPTY [i] = true; 1026 // } 1027 1028 // bool full = ((depth == top) and (top == bottom) and not reg_UPT_EMPTY [i]); 1029 // bool update_ras = find and ((top != depth) or full); 1030 1031 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); 1032 1033 // if (not previous_update_ras and update_ras) 1034 // reg_UPT_UPDATE [i] = new_update; 1035 1036 // // new state : 1037 // // * test if ufpt is empty 1038 // // * ok : flush upft and upt 1039 // // * ko : test if have previous flush upt 1040 // // * ok : nothing 1041 // // * ko : flush upt 1042 // reg_EVENT_VAL [i] = update_ras; 1043 // reg_EVENT_UPT_PTR [i] = depth; 1044 1045 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 1046 // // if (reg_UFPT_NB_NEED_UPDATE [i] > 0) 1047 // if ( (reg_UFPT_NB_NEED_UPDATE [i] > 0) or 1048 // (reg_UFPT_NB_UPDATE [i] > 0)) 1049 // { 1050 // if (update_ras) 1051 // { 1052 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT (branch_complete - miss)",i); 1053 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT; 1054 // } 1055 // else 1056 // { 1057 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UFPT (branch_complete - miss)",i); 1058 // // reg_EVENT_VAL [i] = false; 1059 1060 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UFPT; 1061 // } 1062 // } 1063 // else 1064 // { 1065 // // if (not previous_update_ras) 1066 // if (update_ras) 1067 // { 1068 // // have ras prediction ? 1069 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_EVENT_FLUSH_UPT (branch_complete - miss)",i); 1070 1071 // reg_EVENT_STATE [i] = EVENT_STATE_EVENT_FLUSH_UPT; 1072 // } 1073 // else 1074 // { 1075 // // special case : nothing 1076 // // reg_EVENT_VAL [i] = false; 1077 1078 // reg_EVENT_STATE [i] = EVENT_STATE_OK; 1079 // } 1080 // } 1081 1082 // // else no update 1083 1084 // reg_EVENT_DEPTH [i] = depth; 1085 // // reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State 1086 // // reg_EVENT_ADDRESS_DEST_VAL[i] = good_take; 1087 // // reg_EVENT_ADDRESS_DEST [i] = good_addr; 908 1088 909 1089 break; … … 994 1174 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]); 995 1175 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]); 1176 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]); 996 1177 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 997 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ SOURCE : %s" ,toString(reg_EVENT_SOURCE[i]).c_str());1178 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]); 998 1179 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); 999 1180 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
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