Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src

Timestamp:

Mar 18, 2009, 11:36:26 PM (15 years ago)

Author:

rosiere

Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src

Files:

• Core_allocation.cpp (modified) (5 diffs)
• Core_deallocation.cpp (modified) (1 diff)
• Parameters.cpp (modified) (8 diffs)
• Parameters_print.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp

@@ -55 +55 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
 
       ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL         ,VAL);
@@ -63 +63 @@
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS     ,"address"  ,Ticache_address_t    ,_param->_size_icache_address  );
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE        ,"type"     ,Ticache_type_t       ,_param->_size_icache_type     );
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
                                                                             
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
       
       ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL         ,VAL);
@@ -74 +76 @@
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID   ,"packet_id"  ,Tpacket_t            ,_param->_size_icache_packet_id);
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR       ,"error"      ,Ticache_error_t      ,_param->_size_icache_error);
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
     {
-      ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+      ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
       
       _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
     }
 
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
       
       ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL         ,VAL);
@@ -92 +98 @@
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA       ,"wdata"    ,Tdcache_data_t       ,_param->_size_dcache_data);
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE        ,"type"     ,Tdcache_type_t       ,_param->_size_dcache_type);
+
+      ALLOC1_INTERFACE_END(_param->_nb_dcache_port);
     }
                                                                             
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
     {
-      ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
 
       ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL         ,VAL);
@@ -104 +112 @@
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA       ,"rdata"    ,Tdcache_data_t       ,_param->_size_dcache_data);
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR       ,"error"    ,Tdcache_error_t      ,_param->_size_dcache_error);
+
+      ALLOC1_INTERFACE_END(_param->_nb_dcache_port);
     }
 
     // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread);
+      ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread);
 
       ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE      ,"enable",Tcontrol_t           ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_thread);
     }
     

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp

@@ -59 +59 @@
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
+    DELETE0(_component_glue);
+    DELETE0(_component_dcache_access);
+    DELETE0(_component_icache_access);
+    DELETE1(_component_execute_loop, _param->_nb_execute_loop);
+    DELETE1(_component_ooo_engine  , _param->_nb_ooo_engine);
+    DELETE1(_component_front_end   , _param->_nb_front_end);
+
     delete _component;
 

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp

@@ -107 +107 @@
   uint32_t              * nb_reg_free                                   ,//[nb_rename_bloc]
   uint32_t              * nb_rename_unit_bank                           ,//[nb_rename_bloc]
-  uint32_t              * size_read_counter                             ,//[nb_rename_bloc]
+//   uint32_t              * size_read_counter                             ,//[nb_rename_bloc]
 
   // Read bloc
@@ -262 +262 @@
     _nb_reg_free                             = nb_reg_free                             ;
     _nb_rename_unit_bank                     = nb_rename_unit_bank                     ;
-    _size_read_counter                       = size_read_counter                       ;
+//     _size_read_counter                       = size_read_counter                       ;
 
     _nb_read_bloc                            = nb_read_bloc                            ;
@@ -974 +974 @@
     ALLOC2(_ooo_engine_nb_reg_free                        ,uint32_t         ,_nb_ooo_engine,_nb_rename_unit[it1]);
     ALLOC2(_ooo_engine_nb_rename_unit_bank                ,uint32_t         ,_nb_ooo_engine,_nb_rename_unit[it1]);
-    ALLOC2(_ooo_engine_size_read_counter                  ,uint32_t         ,_nb_ooo_engine,_nb_rename_unit[it1]);
+//     ALLOC2(_ooo_engine_size_read_counter                  ,uint32_t         ,_nb_ooo_engine,_nb_rename_unit[it1]);
 
     for (uint32_t i=0; i<_nb_ooo_engine; ++i)
@@ -997 +997 @@
             _ooo_engine_nb_reg_free                       [i][j] = _nb_reg_free                       [num_rename_bloc];
             _ooo_engine_nb_rename_unit_bank               [i][j] = _nb_rename_unit_bank               [num_rename_bloc];
-            _ooo_engine_size_read_counter                 [i][j] = _size_read_counter                 [num_rename_bloc];
+//             _ooo_engine_size_read_counter                 [i][j] = _size_read_counter                 [num_rename_bloc];
           }
       }
@@ -1918 +1918 @@
        _ooo_engine_nb_reg_free                       [i],
        _ooo_engine_nb_rename_unit_bank               [i],
-       _ooo_engine_size_read_counter                 [i],
+//        _ooo_engine_size_read_counter                 [i],
        _ooo_engine_nb_load_store_unit                [i],
        _ooo_engine_size_store_queue                  [i],
@@ -2134 +2134 @@
     DELETE4(_ooo_engine_implement_group                             ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2],NB_GROUP);
     DELETE3(_ooo_engine_link_load_store_unit_with_context           ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]);
+    DELETE3(_ooo_engine_nb_inst_memory                              ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]);
     DELETE3(_ooo_engine_size_load_queue                             ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]);
     DELETE3(_ooo_engine_size_store_queue                            ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]);
@@ -2142 +2143 @@
     DELETE3(_ooo_engine_table_routing                               ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]);
     DELETE4(_network_table_dispatch                                 ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_execute_loop,_nb_read_unit[it3]);
-    DELETE2(_ooo_engine_size_read_counter                           ,_nb_ooo_engine,_nb_rename_unit[it1]);
+//     DELETE2(_ooo_engine_size_read_counter                           ,_nb_ooo_engine,_nb_rename_unit[it1]);
     DELETE2(_ooo_engine_nb_rename_unit_bank                         ,_nb_ooo_engine,_nb_rename_unit[it1]);
     DELETE2(_ooo_engine_nb_reg_free                                 ,_nb_ooo_engine,_nb_rename_unit[it1]);
@@ -2151 +2152 @@
     DELETE2(_ooo_engine_rename_select_priority                      ,_nb_ooo_engine,_nb_rename_unit[it1]);
     DELETE2(_ooo_engine_nb_inst_retire                              ,_nb_ooo_engine,_nb_rename_unit[it1]);
+    DELETE1(_ooo_engine_nb_inst_insert_rob                          ,_nb_ooo_engine);
     DELETE2(_ooo_engine_nb_inst_insert                              ,_nb_ooo_engine,_nb_rename_unit[it1]);
     DELETE2(_ooo_engine_link_rename_unit_with_front_end             ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]);
     DELETE3(_ooo_engine_nb_branch_speculated                        ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]);
     DELETE2(_ooo_engine_nb_inst_execute                             ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]);
+    DELETE3(_ooo_engine_translate_num_context_to_num_thread         ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]);
     DELETE2(_ooo_engine_nb_inst_decod                               ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]);
     DELETE2(_ooo_engine_nb_context                                  ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]);

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp

@@ -81 +81 @@
     str+= toString(MSG_INFORMATION)+"     * nb_reg_free                                 : "+toString<uint32_t         >(_nb_reg_free                      [i])+"\n";
     str+= toString(MSG_INFORMATION)+"     * nb_rename_unit_bank                         : "+toString<uint32_t         >(_nb_rename_unit_bank              [i])+"\n";
-    str+= toString(MSG_INFORMATION)+"     * size_read_counter                           : "+toString<uint32_t         >(_size_read_counter                [i])+"\n";
+//     str+= toString(MSG_INFORMATION)+"     * size_read_counter                           : "+toString<uint32_t         >(_size_read_counter                [i])+"\n";
       }