Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp

Timestamp:

Mar 18, 2009, 11:36:26 PM (15 years ago)

Author:

rosiere

Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp

@@ -55 +55 @@
     // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port);
 
       ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL         ,VAL);
@@ -63 +63 @@
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS     ,"address"  ,Ticache_address_t    ,_param->_size_icache_address  );
       ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE        ,"type"     ,Ticache_type_t       ,_param->_size_icache_type     );
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
                                                                             
     // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
+      ALLOC1_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port);
       
       ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL         ,VAL);
@@ -74 +76 @@
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID   ,"packet_id"  ,Tpacket_t            ,_param->_size_icache_packet_id);
       ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR       ,"error"      ,Ticache_error_t      ,_param->_size_icache_error);
+
+      ALLOC1_INTERFACE_END(_param->_nb_icache_port);
     }
     {
-      ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+      ALLOC2_INTERFACE_BEGIN("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
       
       _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
+
+      ALLOC2_INTERFACE_END(_param->_nb_icache_port,_param->_icache_nb_instruction[it1]);
     }
 
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port);
       
       ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL         ,VAL);
@@ -92 +98 @@
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA       ,"wdata"    ,Tdcache_data_t       ,_param->_size_dcache_data);
       ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE        ,"type"     ,Tdcache_type_t       ,_param->_size_dcache_type);
+
+      ALLOC1_INTERFACE_END(_param->_nb_dcache_port);
     }
                                                                             
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
     {
-      ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
+      ALLOC1_INTERFACE_BEGIN("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port);
 
       ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL         ,VAL);
@@ -104 +112 @@
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA       ,"rdata"    ,Tdcache_data_t       ,_param->_size_dcache_data);
       ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR       ,"error"    ,Tdcache_error_t      ,_param->_size_dcache_error);
+
+      ALLOC1_INTERFACE_END(_param->_nb_dcache_port);
     }
 
     // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread);
+      ALLOC1_INTERFACE_BEGIN("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread);
 
       ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE      ,"enable",Tcontrol_t           ,1);
+
+      ALLOC1_INTERFACE_END(_param->_nb_thread);
     }