Ignore:
Timestamp:
Mar 18, 2009, 11:36:26 PM (15 years ago)
Author:
rosiere
Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp

    r109 r112  
    4949    // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5050    {
    51       ALLOC0_INTERFACE("insert", IN, WEST, _("Interface of data write."));
     51      ALLOC0_INTERFACE_BEGIN("insert", IN, WEST, _("Interface of data write."));
    5252     
    5353      ALLOC0_VALACK_IN ( in_INSERT_VAL  ,VAL);
    5454      ALLOC0_VALACK_OUT(out_INSERT_ACK  ,ACK);
    5555      ALLOC0_SIGNAL_IN ( in_INSERT_DATA ,"data",Tdata_t,_param->_size_data);
     56
     57      ALLOC0_INTERFACE_END();
    5658    }
    5759
    5860    // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5961    {
    60       ALLOC0_INTERFACE("retire", OUT, EAST, _("Interface of data read."));
     62      ALLOC0_INTERFACE_BEGIN("retire", OUT, EAST, _("Interface of data read."));
    6163     
    6264      ALLOC0_VALACK_OUT(out_RETIRE_VAL  ,VAL);
    6365      ALLOC0_VALACK_IN ( in_RETIRE_ACK  ,ACK);
    6466      ALLOC0_SIGNAL_OUT(out_RETIRE_DATA ,"data",Tdata_t,_param->_size_data);
     67
     68      ALLOC0_INTERFACE_END();
    6569    }
    6670
    6771    // ~~~~~[ Interface "slot" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    6872    {
    69       ALLOC1_INTERFACE("slot", OUT, NORTH, _("Internal slot."),_param->_nb_port_slot);
     73      ALLOC1_INTERFACE_BEGIN("slot", OUT, NORTH, _("Internal slot."),_param->_nb_port_slot);
    7074     
    7175      ALLOC1_VALACK_OUT(out_SLOT_VAL  ,VAL);
    7276      ALLOC1_SIGNAL_OUT(out_SLOT_DATA ,"data",Tdata_t,_param->_size_data);
     77
     78      ALLOC1_INTERFACE_END(_param->_nb_port_slot);
    7379    }
    7480
     
    7682    if (_param->_have_port_ptr)
    7783    {
    78       ALLOC0_INTERFACE("ptr", OUT, SOUTH, _("Internal pointer."));
     84      ALLOC0_INTERFACE_BEGIN("ptr", OUT, SOUTH, _("Internal pointer."));
    7985     
    8086      if (_param->_have_port_ptr_write)
     
    8288      if (_param->_have_port_ptr_read )
    8389      ALLOC0_SIGNAL_OUT(out_PTR_READ  ,"read" ,Tptr_t,_param->_size_ptr);
     90
     91      ALLOC0_INTERFACE_END();
    8492    }
    8593     
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