- Timestamp:
- Mar 18, 2009, 11:36:26 PM (15 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp
r109 r112 7 7 8 8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 33 34 , IN 34 35 ,SOUTH 35 , "Generalist interface"36 ,_("Generalist interface") 36 37 #endif 37 38 ); … … 40 41 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 41 42 } 43 42 44 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 45 { 46 ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read); 43 47 44 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; 45 out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; 46 if (_param->_have_port_address) 47 in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; 48 out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; 48 ALLOC1_VALACK_IN ( in_READ_VAL ,VAL); 49 ALLOC1_VALACK_OUT(out_READ_ACK ,ACK); 50 ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t,_param->_size_address); 51 ALLOC1_SIGNAL_OUT(out_READ_DATA ,"data" ,Tdata_t ,_param->_size_word); 49 52 50 for (uint32_t i=0; i<_param->_nb_port_read; i++) 51 { 52 Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) 53 #ifdef POSITION 54 , IN 55 ,WEST 56 , "Interface Read" 57 #endif 58 ); 59 60 in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 61 out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 62 if (_param->_have_port_address) 63 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address); 64 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word); 65 } 53 ALLOC1_INTERFACE_END(_param->_nb_port_read); 54 } 66 55 67 56 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 57 { 58 ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write); 68 59 69 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; 70 out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; 71 if (_param->_have_port_address) 72 in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; 73 in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; 74 75 for (uint32_t i=0; i<_param->_nb_port_write; i++) 76 { 77 Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) 78 #ifdef POSITION 79 , IN 80 ,EAST 81 , "Interface Write" 82 #endif 83 ); 60 ALLOC1_VALACK_IN ( in_WRITE_VAL ,VAL); 61 ALLOC1_VALACK_OUT(out_WRITE_ACK ,ACK); 62 ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); 63 ALLOC1_SIGNAL_IN ( in_WRITE_DATA ,"data" ,Tdata_t ,_param->_size_word); 84 64 85 in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 86 out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 87 if (_param->_have_port_address) 88 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address); 89 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word); 90 } 65 ALLOC1_INTERFACE_END(_param->_nb_port_write); 66 } 91 67 92 68 // ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 69 { 70 ALLOC1_INTERFACE_BEGIN("read_write",IN,WEST,_("Interface Read_Write"),_param->_nb_port_read_write); 93 71 94 in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; 95 out_READ_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read_write]; 96 in_READ_WRITE_RW = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; 97 if (_param->_have_port_address) 98 in_READ_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read_write]; 99 in_READ_WRITE_WDATA = new SC_IN (Tdata_t ) * [_param->_nb_port_read_write]; 100 out_READ_WRITE_RDATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read_write]; 72 ALLOC1_VALACK_IN ( in_READ_WRITE_VAL ,VAL); 73 ALLOC1_VALACK_OUT(out_READ_WRITE_ACK ,ACK); 74 ALLOC1_SIGNAL_IN ( in_READ_WRITE_RW ,"rw" ,Tcontrol_t,1); 75 ALLOC1_SIGNAL_IN ( in_READ_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); 76 ALLOC1_SIGNAL_IN ( in_READ_WRITE_WDATA ,"wdata" ,Tdata_t ,_param->_size_word); 77 ALLOC1_SIGNAL_OUT(out_READ_WRITE_RDATA ,"rdata" ,Tdata_t ,_param->_size_word); 101 78 102 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 103 { 104 Interface_fifo * interface = _interfaces->set_interface("read_write_"+toString(i) 105 #ifdef POSITION 106 , IN 107 ,WEST 108 , "Interface Read_Write" 109 #endif 110 ); 79 ALLOC1_INTERFACE_END(_param->_nb_port_read_write); 80 } 111 81 112 in_READ_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL);113 out_READ_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);114 in_READ_WRITE_RW [i] = interface->set_signal_valack_in ("rw" , VAL);115 if (_param->_have_port_address)116 in_READ_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);117 in_READ_WRITE_WDATA [i] = interface->set_signal_in <Tdata_t > ("wdata" , _param->_size_word);118 out_READ_WRITE_RDATA [i] = interface->set_signal_out <Tdata_t > ("rdata" , _param->_size_word);119 }120 121 // ----- Register122 82 if (usage_is_set(_usage,USE_SYSTEMC)) 123 reg_DATA = new Tdata_t [_param->_nb_word];83 ALLOC1(reg_DATA,Tdata_t,_param->_nb_word); 124 84 125 85 #ifdef POSITION -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp
r88 r112 2 2 * $Id$ 3 3 * 4 * [ 4 * [ Description ] 5 5 * 6 6 */ 7 7 8 8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 22 23 delete in_CLOCK; 23 24 delete in_NRESET; 24 // ----- Interface Read 25 delete [] in_READ_VAL ; 26 delete [] out_READ_ACK ; 27 if (_param->_have_port_address) 28 delete [] in_READ_ADDRESS; 29 delete [] out_READ_DATA ; 30 31 // ----- Interface Write 32 delete [] in_WRITE_VAL ; 33 delete [] out_WRITE_ACK ; 34 if (_param->_have_port_address) 35 delete [] in_WRITE_ADDRESS; 36 delete [] in_WRITE_DATA ; 37 38 // ----- Interface Read_Write 39 delete [] in_READ_WRITE_VAL ; 40 delete [] out_READ_WRITE_ACK ; 41 delete [] in_READ_WRITE_RW ; 42 if (_param->_have_port_address) 43 delete [] in_READ_WRITE_ADDRESS; 44 delete [] in_READ_WRITE_WDATA ; 45 delete [] out_READ_WRITE_RDATA ; 46 47 // ----- Register 48 delete [] reg_DATA; 25 26 DELETE1_SIGNAL( in_READ_VAL ,_param->_nb_port_read,1); 27 DELETE1_SIGNAL(out_READ_ACK ,_param->_nb_port_read,1); 28 DELETE1_SIGNAL( in_READ_ADDRESS ,_param->_nb_port_read,_param->_size_address); 29 DELETE1_SIGNAL(out_READ_DATA ,_param->_nb_port_read,_param->_size_word); 30 31 DELETE1_SIGNAL( in_WRITE_VAL ,_param->_nb_port_write,1); 32 DELETE1_SIGNAL(out_WRITE_ACK ,_param->_nb_port_write,1); 33 DELETE1_SIGNAL( in_WRITE_ADDRESS,_param->_nb_port_write,_param->_size_address); 34 DELETE1_SIGNAL( in_WRITE_DATA ,_param->_nb_port_write,_param->_size_word); 35 36 DELETE1_SIGNAL( in_READ_WRITE_VAL ,_param->_nb_port_read_write,1); 37 DELETE1_SIGNAL(out_READ_WRITE_ACK ,_param->_nb_port_read_write,1); 38 DELETE1_SIGNAL( in_READ_WRITE_RW ,_param->_nb_port_read_write,1); 39 DELETE1_SIGNAL( in_READ_WRITE_ADDRESS,_param->_nb_port_read_write,_param->_size_address); 40 DELETE1_SIGNAL( in_READ_WRITE_WDATA ,_param->_nb_port_read_write,_param->_size_word); 41 DELETE1_SIGNAL(out_READ_WRITE_RDATA ,_param->_nb_port_read_write,_param->_size_word); 42 43 DELETE1(reg_DATA,_param->_nb_word); 49 44 } 50 45 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp
r88 r112 7 7 8 8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 36 37 ,IN 37 38 ,SOUTH, 38 "Generalist interface"39 _("Generalist interface") 39 40 #endif 40 41 ); … … 43 44 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 44 45 45 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 46 // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 47 { 48 ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read); 46 49 47 in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; 48 out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; 49 if (_param->_have_port_address == true) 50 in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; 51 out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; 50 ALLOC1_VALACK_IN ( in_READ_VAL ,VAL); 51 ALLOC1_VALACK_OUT(out_READ_ACK ,ACK); 52 ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t, _param->_size_address); 53 ALLOC1_SIGNAL_OUT(out_READ_DATA ,"data" ,Tdata_t , _param->_size_word); 52 54 53 for (uint32_t i=0; i<_param->_nb_port_read; i++) 54 { 55 Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) 56 #ifdef POSITION 57 , IN 58 ,WEST 59 , "Interface Read" 60 #endif 61 ); 55 ALLOC1_INTERFACE_END(_param->_nb_port_read); 56 } 57 58 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 59 { 60 ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write); 62 61 63 in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 64 out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 65 if (_param->_have_port_address == true) 66 in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); 67 out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word); 68 } 62 ALLOC1_VALACK_IN ( in_WRITE_VAL ,VAL); 63 ALLOC1_VALACK_OUT(out_WRITE_ACK ,ACK); 64 ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address); 65 ALLOC1_SIGNAL_IN ( in_WRITE_DATA ,"data" ,Tdata_t ,_param->_size_word); 69 66 70 // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 71 72 in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; 73 out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; 74 if (_param->_have_port_address == true) 75 in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; 76 in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; 77 78 for (uint32_t i=0; i<_param->_nb_port_write; i++) 79 { 80 Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) 81 #ifdef POSITION 82 , IN 83 ,EAST 84 , "Interface Write" 85 #endif 86 ); 87 88 in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); 89 out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); 90 if (_param->_have_port_address == true) 91 in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); 92 in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word); 67 ALLOC1_INTERFACE_END(_param->_nb_port_write); 93 68 } 94 69 95 70 if (usage_is_set(_usage,USE_SYSTEMC)) 96 71 { 97 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 72 // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 ALLOC2(reg_DATA,Tdata_t,_param->_nb_bank,_param->_nb_word); 98 74 99 reg_DATA = new Tdata_t * [_param->_nb_bank]; 100 101 for (uint32_t i=0; i<_param->_nb_bank; i++) 102 { 103 reg_DATA [i] = new Tdata_t [_param->_nb_word]; 104 } 105 106 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 107 internal_WRITE_VAL = new bool [_param->_nb_port_write]; 108 internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; 109 internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; 75 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 76 ALLOC1(internal_WRITE_VAL ,bool ,_param->_nb_port_write); 77 ALLOC1(internal_WRITE_BANK ,Taddress_t,_param->_nb_port_write); 78 ALLOC1(internal_WRITE_NUM_REG,Taddress_t,_param->_nb_port_write); 110 79 } 111 80 112 81 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 114 82 #ifdef POSITION 115 83 if (usage_is_set(_usage,USE_POSITION)) 116 84 _component->generate_file(); 117 85 #endif 118 86 119 87 log_printf(FUNC,RegisterFile_Multi_Banked,"allocation","End"); 120 88 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp
r88 r112 2 2 * $Id$ 3 3 * 4 * [ 4 * [ Description ] 5 5 * 6 6 */ 7 7 8 8 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 23 24 delete in_CLOCK; 24 25 delete in_NRESET; 26 27 DELETE1_SIGNAL( in_READ_VAL ,_param->_nb_port_read,1); 28 DELETE1_SIGNAL(out_READ_ACK ,_param->_nb_port_read,1); 29 DELETE1_SIGNAL( in_READ_ADDRESS ,_param->_nb_port_read,_param->_size_address); 30 DELETE1_SIGNAL(out_READ_DATA ,_param->_nb_port_read,_param->_size_word); 25 31 26 // ----- Interface Read 27 delete [] in_READ_VAL ; 28 delete [] out_READ_ACK ; 29 if (_param->_have_port_address == true) 30 delete [] in_READ_ADDRESS; 31 delete [] out_READ_DATA ; 32 DELETE1_SIGNAL( in_WRITE_VAL ,_param->_nb_port_write,1); 33 DELETE1_SIGNAL(out_WRITE_ACK ,_param->_nb_port_write,1); 34 DELETE1_SIGNAL( in_WRITE_ADDRESS,_param->_nb_port_write,_param->_size_address); 35 DELETE1_SIGNAL( in_WRITE_DATA ,_param->_nb_port_write,_param->_size_word); 32 36 33 // ----- Interface Write 34 delete [] in_WRITE_VAL ; 35 delete [] out_WRITE_ACK ; 36 if (_param->_have_port_address == true) 37 delete [] in_WRITE_ADDRESS; 38 delete [] in_WRITE_DATA ; 37 DELETE2(reg_DATA ,_param->_nb_bank,_param->_nb_word); 39 38 40 // ----- Register 41 delete [] reg_DATA; 42 43 // ----- Internal 44 delete [] internal_WRITE_VAL; 45 delete [] internal_WRITE_BANK; 46 delete [] internal_WRITE_NUM_REG; 39 DELETE1(internal_WRITE_VAL ,_param->_nb_port_write); 40 DELETE1(internal_WRITE_BANK ,_param->_nb_port_write); 41 DELETE1(internal_WRITE_NUM_REG ,_param->_nb_port_write); 47 42 } 48 43 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/include/test.h
r81 r112 15 15 #include <sys/time.h> 16 16 17 #include "Common/include/Time.h" 17 18 #include "Behavioural/Generic/RegisterFile/include/RegisterFile.h" 18 19 … … 26 27 morpheo::behavioural::generic::registerfile::Parameters * param); 27 28 28 class Time29 {30 private : timeval time_begin;31 // private : timeval time_end;32 33 public : Time ()34 {35 gettimeofday(&time_begin ,NULL);36 };37 38 public : ~Time ()39 {40 cout << *this;41 };42 43 public : friend ostream& operator<< (ostream& output_stream,44 const Time & x)45 {46 timeval time_end;47 48 gettimeofday(&time_end ,NULL);49 50 uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time());51 52 double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec);53 54 output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl;55 56 return output_stream;57 }58 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/RegisterFile.h
r82 r112 53 53 54 54 public : Component * _component; 55 private : Interfaces * _interfaces; 55 56 56 57 #ifdef SYSTEMC
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