Changeset 112 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp

Timestamp:

Mar 18, 2009, 11:36:26 PM (15 years ago)

Author:

rosiere

Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (modified) (3 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp

@@ -7 +7 @@
 
 #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -36 +37 @@
                                                          ,IN
                                                          ,SOUTH,
-                                                         "Generalist interface"
+                                                         _("Generalist interface")
 #endif
                                                          );
@@ -43 +44 @@
      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
 
-    // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+     // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+     { 
+       ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read);
 
-     in_READ_VAL         = new SC_IN (Tcontrol_t) * [_param->_nb_port_read];
-    out_READ_ACK         = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read];
-    if (_param->_have_port_address == true)
-     in_READ_ADDRESS     = new SC_IN (Taddress_t) * [_param->_nb_port_read];
-    out_READ_DATA        = new SC_OUT(Tdata_t   ) * [_param->_nb_port_read];
+       ALLOC1_VALACK_IN ( in_READ_VAL    ,VAL);
+       ALLOC1_VALACK_OUT(out_READ_ACK    ,ACK);
+       ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t, _param->_size_address);
+       ALLOC1_SIGNAL_OUT(out_READ_DATA   ,"data"   ,Tdata_t   , _param->_size_word);
 
-    for (uint32_t i=0; i<_param->_nb_port_read; i++)
-      { 
-        Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i)
-#ifdef POSITION
-                                                                , IN  
-                                                                ,WEST
-                                                                , "Interface Read"
-#endif
-                                                                );
+       ALLOC1_INTERFACE_END(_param->_nb_port_read);
+     }
+     
+     // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+     {
+       ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write);
 
-         in_READ_VAL     [i]  = interface->set_signal_valack_in        ("val"    , VAL);
-        out_READ_ACK     [i]  = interface->set_signal_valack_out       ("ack"    , ACK);
-        if (_param->_have_port_address == true)
-         in_READ_ADDRESS [i]  = interface->set_signal_in  <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word)));
-        out_READ_DATA    [i]  = interface->set_signal_out <Tdata_t   > ("data"   , _param->_size_word);
-      }
+       ALLOC1_VALACK_IN ( in_WRITE_VAL    ,VAL);
+       ALLOC1_VALACK_OUT(out_WRITE_ACK    ,ACK);
+       ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address);
+       ALLOC1_SIGNAL_IN ( in_WRITE_DATA   ,"data"   ,Tdata_t   ,_param->_size_word);
 
-    // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-     in_WRITE_VAL        = new SC_IN (Tcontrol_t) * [_param->_nb_port_write];
-    out_WRITE_ACK        = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write];
-    if (_param->_have_port_address == true)
-     in_WRITE_ADDRESS    = new SC_IN (Taddress_t) * [_param->_nb_port_write];
-     in_WRITE_DATA       = new SC_IN (Tdata_t   ) * [_param->_nb_port_write];
-    
-    for (uint32_t i=0; i<_param->_nb_port_write; i++)
-      {
-        Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i)
-#ifdef POSITION
-                                                                , IN  
-                                                                ,EAST
-                                                                , "Interface Write"
-#endif
-                                                                );
-
-         in_WRITE_VAL     [i]  = interface->set_signal_valack_in        ("val"    , VAL);
-        out_WRITE_ACK     [i]  = interface->set_signal_valack_out       ("ack"    , ACK);
-        if (_param->_have_port_address == true)
-         in_WRITE_ADDRESS [i]  = interface->set_signal_in  <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word)));
-         in_WRITE_DATA    [i]  = interface->set_signal_in  <Tdata_t   > ("data"   , _param->_size_word);
+       ALLOC1_INTERFACE_END(_param->_nb_port_write);
       }
 
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-    // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        ALLOC2(reg_DATA,Tdata_t,_param->_nb_bank,_param->_nb_word);
 
-    reg_DATA = new Tdata_t * [_param->_nb_bank];
-
-    for (uint32_t i=0; i<_param->_nb_bank; i++)
-      {
-        reg_DATA [i] = new Tdata_t [_param->_nb_word];
-      }
-
-    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-    internal_WRITE_VAL     = new bool       [_param->_nb_port_write];
-    internal_WRITE_BANK    = new Taddress_t [_param->_nb_port_write];
-    internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write];
+        // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        ALLOC1(internal_WRITE_VAL    ,bool      ,_param->_nb_port_write);
+        ALLOC1(internal_WRITE_BANK   ,Taddress_t,_param->_nb_port_write);
+        ALLOC1(internal_WRITE_NUM_REG,Taddress_t,_param->_nb_port_write);
       }
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-
 #ifdef POSITION
     if (usage_is_set(_usage,USE_POSITION))
       _component->generate_file();
 #endif
-
+    
     log_printf(FUNC,RegisterFile_Multi_Banked,"allocation","End");
   };