Ignore:
Timestamp:
Mar 18, 2009, 11:36:26 PM (15 years ago)
Author:
rosiere
Message:

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

File:
1 edited

Legend:

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Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

    r103 r112  
    6666                                @\
    6767                                $(ECHO) "Create work-space  : $@"; \
    68                                 $(MODELTECH_VLIB) $@;
     68                                $(MODELTECH_VLIB) $@; \
     69                                $(MODELTECH_VMAP) $(XILINX_CORELIB);
    6970
    7071$(DIR_LOG)/%.sim.log            : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
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