Ignore:
Timestamp:
Apr 14, 2009, 8:39:12 PM (15 years ago)
Author:
rosiere
Message:

1) Add modelsim simulation systemC
2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit)
3) Add multi architecture
5) Add template for comparator, multiplier and divider
6) Change Message
Warning) Various test macro have change, many selftest can't compile

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_genMealy.cpp

    r81 r113  
    1818    log_printf(FUNC,Counter,"genMealy","Begin");
    1919
    20     for (uint32_t i=0; i<_param._nb_port; i++)
     20    for (uint32_t i=0; i<_param->_nb_port; i++)
    2121      {
    2222        Tcontrol_t addsub  = PORT_READ(in_COUNTER_ADDSUB [i]);
     
    2828        if (addsub == 1)
    2929          {
    30             if (data_out < _param._data_max)
     30            if (data_out < _param->_data_max)
    3131              data_out++;
    3232          }
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