Ignore:
Timestamp:
Apr 14, 2009, 8:39:12 PM (15 years ago)
Author:
rosiere
Message:

1) Add modelsim simulation systemC
2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit)
3) Add multi architecture
5) Add template for comparator, multiplier and divider
6) Change Message
Warning) Various test macro have change, many selftest can't compile

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_set_port.cpp

    r81 r113  
    2121        (_presence_port == CLOCK_VHDL_YES)              or
    2222        (_presence_port == RESET_VHDL_YES))
    23       vhdl->set_port (_name,_direction,_size);
     23      vhdl->set_port (_name,_direction,get_size());
    2424
    2525    log_printf(FUNC,Behavioural,"set_port (Vhdl)","End");
     
    3838//      or (_presence_port == RESET_VHDL_NO )
    3939        )
    40       vhdl->set_signal (_name        ,_size);
     40      vhdl->set_signal (_name        ,get_size());
    4141
    4242    if (_direction == OUT)
    43       vhdl->set_signal (_name+"_test",_size);
     43      vhdl->set_signal (_name+"_test",get_size());
    4444
    4545    log_printf(FUNC,Behavioural,"set_signal (Vhdl)","End");
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