Changeset 116 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
- Timestamp:
- Apr 30, 2009, 3:51:41 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
r100 r116 58 58 } 59 59 60 61 if (reg_BUSY_IN and not reg_BUSY_OUT) 62 // if (not reg_BUSY_OUT_old or) 63 { 64 reg_BUSY_OUT = reg_BUSY_IN; 65 reg_BUSY_IN = false; 66 67 _execute_operation_out->_timing = _execute_operation_in->_timing ; 68 _execute_operation_out->_context_id = _execute_operation_in->_context_id ; 69 _execute_operation_out->_front_end_id = _execute_operation_in->_front_end_id ; 70 _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id; 71 _execute_operation_out->_packet_id = _execute_operation_in->_packet_id ; 72 _execute_operation_out->_operation = _execute_operation_in->_operation ; 73 _execute_operation_out->_type = _execute_operation_in->_type ; 74 _execute_operation_out->_has_immediat = _execute_operation_in->_has_immediat ; 75 _execute_operation_out->_immediat = _execute_operation_in->_immediat ; 76 _execute_operation_out->_data_ra = _execute_operation_in->_data_ra ; 77 _execute_operation_out->_data_rb = _execute_operation_in->_data_rb ; 78 _execute_operation_out->_data_rc = _execute_operation_in->_data_rc ; 79 _execute_operation_out->_data_rd = _execute_operation_in->_data_rd ; 80 _execute_operation_out->_data_re = _execute_operation_in->_data_re ; 81 _execute_operation_out->_write_rd = _execute_operation_in->_write_rd ; 82 _execute_operation_out->_num_reg_rd = _execute_operation_in->_num_reg_rd ; 83 _execute_operation_out->_write_re = _execute_operation_in->_write_re ; 84 _execute_operation_out->_num_reg_re = _execute_operation_in->_num_reg_re ; 85 _execute_operation_out->_exception = _execute_operation_in->_exception ; 86 _execute_operation_out->_no_sequence = _execute_operation_in->_no_sequence ; 87 _execute_operation_out->_address = _execute_operation_in->_address ; 88 } 89 90 91 60 92 // Test if push 61 93 execute_register_t * execute_register = NULL; … … 178 210 } 179 211 180 if (reg_BUSY_IN and not reg_BUSY_OUT)181 {182 reg_BUSY_OUT = reg_BUSY_IN;183 reg_BUSY_IN = false;184 185 _execute_operation_out->_timing = _execute_operation_in->_timing ;186 _execute_operation_out->_context_id = _execute_operation_in->_context_id ;187 _execute_operation_out->_front_end_id = _execute_operation_in->_front_end_id ;188 _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id;189 _execute_operation_out->_packet_id = _execute_operation_in->_packet_id ;190 _execute_operation_out->_operation = _execute_operation_in->_operation ;191 _execute_operation_out->_type = _execute_operation_in->_type ;192 _execute_operation_out->_has_immediat = _execute_operation_in->_has_immediat ;193 _execute_operation_out->_immediat = _execute_operation_in->_immediat ;194 _execute_operation_out->_data_ra = _execute_operation_in->_data_ra ;195 _execute_operation_out->_data_rb = _execute_operation_in->_data_rb ;196 _execute_operation_out->_data_rc = _execute_operation_in->_data_rc ;197 _execute_operation_out->_data_rd = _execute_operation_in->_data_rd ;198 _execute_operation_out->_data_re = _execute_operation_in->_data_re ;199 _execute_operation_out->_write_rd = _execute_operation_in->_write_rd ;200 _execute_operation_out->_num_reg_rd = _execute_operation_in->_num_reg_rd ;201 _execute_operation_out->_write_re = _execute_operation_in->_write_re ;202 _execute_operation_out->_num_reg_re = _execute_operation_in->_num_reg_re ;203 _execute_operation_out->_exception = _execute_operation_in->_exception ;204 _execute_operation_out->_no_sequence = _execute_operation_in->_no_sequence ;205 _execute_operation_out->_address = _execute_operation_in->_address ;206 }207 212 208 213 // each cycle : decrease the latence … … 210 215 _execute_operation_out->_timing._latence --; 211 216 } 212 217 213 218 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 214 219 end_cycle ();
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