Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp

Timestamp:

May 16, 2009, 4:42:39 PM (15 years ago)

Author:

rosiere

Message:

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench?
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp

@@ -49 +49 @@
         PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL            [i], WRITE_RE          );
 
-        PORT_WRITE(out_INSERT_STAT_LIST_READ_RA            [i], READ_RA           );
-        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RA_PHY     [i], NUM_REG_RA_PHY    );
-        PORT_WRITE(out_INSERT_STAT_LIST_READ_RB            [i], READ_RB           );
-        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RB_PHY     [i], NUM_REG_RB_PHY    );
-        PORT_WRITE(out_INSERT_STAT_LIST_READ_RC            [i], READ_RC           );
-        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RC_PHY     [i], NUM_REG_RC_PHY    );
+        PORT_WRITE(out_INSERT_STAT_LIST_READ_RA            [i], READ_RA           );
+        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RA_PHY     [i], NUM_REG_RA_PHY    );
+        PORT_WRITE(out_INSERT_STAT_LIST_READ_RB            [i], READ_RB           );
+        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RB_PHY     [i], NUM_REG_RB_PHY    );
+        PORT_WRITE(out_INSERT_STAT_LIST_READ_RC            [i], READ_RC           );
+        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RC_PHY     [i], NUM_REG_RC_PHY    );
         PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RD           [i], WRITE_RD          );
+        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD [i], NUM_REG_RD_PHY_OLD);
         PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW [i], NUM_REG_RD_PHY_NEW);
         PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RE           [i], WRITE_RE          );
+        PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD [i], NUM_REG_RE_PHY_OLD);
         PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW [i], NUM_REG_RE_PHY_NEW);