Changeset 117 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

Timestamp:

May 16, 2009, 4:42:39 PM (16 years ago)

Author:

rosiere

Message:

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench?
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (modified) (3 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

@@ -11 +11 @@
 DIR_VHDL                        = .
 WORK_NAME                       = work
-DIR_WORK                        = $(MORPHEO_TMP)/$(WORK_NAME)
+DIR_WORK                        = $(DIR_TMP)/$(WORK_NAME)
 
 FPGA_CFG_FILE_LOCAL             = mkf.info
@@ -95 +95 @@
                                 $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@;
 
-$(DIR_WORK)                     : $(XILINX_CORELIB)
+$(DIR_WORK)                     : 
                                 @\
                                 $(ECHO) "Create work-space  : $@";                                                      \
+                                mkdir -p $@; \
                                 $(MODELTECH_VLIB) $@;                                                                   \
                                 $(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR);                                   \
@@ -104 +105 @@
                                    $(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory";       \
                                 fi;                                  
-
-$(XILINX_CORELIB)               :
-                                @\
-                                $(ECHO) "Create Corelib     : $@"; \
-                                $(MODELTECH_ENV); $(XILINX_COMPXLIB)
-
-#                               $(MODELTECH_ENV); $(XILINX_COMPXLIB) -s mti_se -arch all -lib all -l vhdl -dir $(XILINX_CORELIB) -w -p $(MODELTECH_BIN) -smartmodel_setup
-                                
 
 $(DIR_LOG)/%.sim.log            : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log