Changeset 119 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src

Timestamp:

May 25, 2009, 7:40:26 PM (15 years ago)

Author:

rosiere

Message:

1) Prediction unit : static prediction not blocking

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src

Files:

• Ifetch_queue_genMoore.cpp (modified) (1 diff)
• Ifetch_queue_transition.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp

@@ -26 +26 @@
     // =====[ ADDRESS ]==========================================
     // ==========================================================
-    internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
-
-    PORT_WRITE(out_ADDRESS_ACK            , internal_ADDRESS_ACK);
-    if (_param->_have_port_ifetch_queue_ptr)
-    PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
+    {
+      internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY);
+      
+      PORT_WRITE(out_ADDRESS_ACK            , internal_ADDRESS_ACK);
+      if (_param->_have_port_ifetch_queue_ptr)
+      PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE);
+    }
 
     // ==========================================================
     // =====[ DECOD ]============================================
     // ==========================================================
-    bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP);
-
-    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-      {
-        internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i];
-        PORT_WRITE(out_DECOD_VAL         [i], internal_DECOD_VAL [i]);
-        PORT_WRITE(out_DECOD_INSTRUCTION [i],         _queue[reg_PTR_READ]->_instruction        [i]);
-      }
-
-    PORT_WRITE(out_DECOD_ADDRESS                    , _queue[reg_PTR_READ]->_address                    );
-    if (_param->_have_port_inst_ifetch_ptr)
-    PORT_WRITE(out_DECOD_INST_IFETCH_PTR            , _queue[reg_PTR_READ]->_inst_ifetch_ptr            );
-    PORT_WRITE(out_DECOD_BRANCH_STATE               , _queue[reg_PTR_READ]->_branch_state               );
-    if (_param->_have_port_depth)
-    PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id);
-    PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );
+    {
+      bool ack = (_queue[reg_PTR_READ]->_state == IFETCH_QUEUE_STATE_HAVE_RSP);
+      
+      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+        {
+          internal_DECOD_VAL [i] = ack and _queue[reg_PTR_READ]->_instruction_enable [i];
+          PORT_WRITE(out_DECOD_VAL         [i], internal_DECOD_VAL [i]);
+          PORT_WRITE(out_DECOD_INSTRUCTION [i],         _queue[reg_PTR_READ]->_instruction        [i]);
+        }
+      
+      PORT_WRITE(out_DECOD_ADDRESS                    , _queue[reg_PTR_READ]->_address                    );
+      if (_param->_have_port_inst_ifetch_ptr)
+      PORT_WRITE(out_DECOD_INST_IFETCH_PTR            , _queue[reg_PTR_READ]->_inst_ifetch_ptr            );
+      PORT_WRITE(out_DECOD_BRANCH_STATE               , _queue[reg_PTR_READ]->_branch_state               );
+      if (_param->_have_port_depth)
+      PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id);
+      PORT_WRITE(out_DECOD_EXCEPTION                  , _queue[reg_PTR_READ]->_exception                  );
+    }
 
     log_printf(FUNC,Ifetch_queue,FUNCTION,"End");

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp

@@ -23 +23 @@
   {
     log_begin(Ifetch_queue,FUNCTION);
+    log_function(Ifetch_queue,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -39 +40 @@
         if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK)
           {
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ADDRESS : Transaction");
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"    * ADDRESS       : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
+
             // New slot in ifetch_queue is allocated
             
@@ -75 +80 @@
             if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i]))
               {
+                log_printf(TRACE,Ifetch_queue,FUNCTION,"  * DECOD [%d] : Transaction",i);
+
                 have_instruction_decod = true;
                 _queue[reg_PTR_READ]->_instruction_enable [i] = false;
@@ -94 +101 @@
         if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK)
           {
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"  * ICACHE_RSP : Transaction");
+
             Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0;
             
@@ -119 +128 @@
         if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK)
           {
+            log_printf(TRACE,Ifetch_queue,FUNCTION,"  * EVENT_RESET : Transaction");
+
             // Scan all entry of queue and test the status
             for (uint32_t i=0; i<_param->_size_queue; i++)